Commit Graph

34 Commits

Author SHA1 Message Date
German Andryeyev 24299e25bd SWDEV-272496 - Fix multiple timing issues
- Don't notify if the batch is empty, because that means
the current command was processed already.
- Disable pinning optimization to avoid a race condition on stall.
- TS marker submition requires extra AQL barrier
to track the status.

Change-Id: I17eff4ad12ac66cfe1bb44048bebb1891805279d
2021-03-01 12:46:57 -05:00
Alex Xie 639d67866c SWDEV-272382 - [OCL][LNX] OCLMemoryInfo[1] subtest of oclruntime is failing
1. Fix the size of the memory when releasing.
2. Make sure we only count the device memory

Change-Id: Ib4dcda79f313c4ee9cc1c7bab53f8076bce5f583
2021-02-28 16:00:51 -05:00
Ravi C Akkenapally 0a5f9a3b10 SWDEV-179105 - Stream Operations: Add support for Wait and Write
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808
2021-02-15 17:02:38 -08:00
kjayapra-amd 2df099df9e SWDEV-270013 - Allocate kernel_arguments from kern_arg & finegrain pool instead of coarse grain.
Change-Id: Id4c6977934fdd6ef2311f6e75593801f1e51983c
2021-02-15 18:20:08 -05:00
Tony Tye c7e8d91e14 Update code object handling for GSL, PAL and ROCm
- Correct GSL path to report targets using the TargetID syntax.

- Correct GSL path to check compatibility of code objects when
  loading.

- Add concept of an device isa and create a registery used by ROCm,
  PAL and GSL.

- Support XNACK and SRAMECC target features consistently for PAL and ROCm.

- Correct logic for NullDevices and asserts to avoid memory coruption.

- Allow all NullDevices to be created for HIP.

- Numerous other code improvements.

Change-Id: I40abf3d2b22249c1492d1af5919665f8184f4e0e
2021-01-14 11:11:51 -05:00
German Andryeyev 7d3aaa7a39 Explicit page table update on all devices
HMM with xnack enabled should automatically update page tables,
but currently it doesn't perform that. For now, runtime will
force page table update on all devices unconditionally.

Change-Id: Idfa6e1c145e6c114856214dce042b8a8349e5c58
2021-01-12 23:16:46 -05:00
German Andryeyev 8698aeef0d Add HSA signal global tracking logic.
Implement the global class for signals tracking per device queue.
Switch to the new tracking mechanism.

Change-Id: I3c4dda04b34e6d18d6a95510d84102909633b415
2021-01-08 12:57:33 -05:00
Alex Xie 2505d68eba SWDEV-256126 - Linux pro Nuke app crash with "Out of memory"
Out of memory while running RIP plugin test

Change-Id: I8d6859a45b871f96ac027f8c7274f716e8524a3c
2020-12-10 11:44:54 -05:00
Alex Xie e5588f188c SWDEV-256126 - Linux pro Nuke app crash with "Out of memory "while running Rip plugin test
We unmap a memory with a different pointer.
ROCr runtime might be confused and silently ignore the unmap request

Change-Id: Ic5a1387a426cf02a985a4ef8ff8ff05e6a870cbf
2020-10-21 11:33:42 -04:00
Jason Tang 25cc965c76 Change file mode 755 back to 644
Change-Id: I4ba5d66997ffd3331c56674d4bf805160dcdf049
2020-10-19 15:09:32 -04:00
Alex Xie e4e6c46356 SWDEV-251360 - Add tracing for memory allocation/free.
This can be used to debug VM fault

Change-Id: I7685485b0450ea84d10b710639ad7b6c5ec2fcf3
2020-10-15 15:38:55 -04:00
Tao Sang bc7291e85c Fix empty cpu agent on raven system
Change-Id: I30f5e65367613152ce96b80b13e1c9f2a28da807
2020-10-05 10:54:57 -04:00
Jason Tang c33470ab4d SWDEV-239502 - Create copyImageBuffer_ without flags
Change-Id: Ifcb5992d58f3419635d2aca2d51f2dacd7cd466d
2020-08-14 17:25:58 -04:00
Vlad Sytchenko 6780a9ac66 Remove unnecessary SVM commit
Change-Id: I5cb887ead166401a59b0c980f29fd615b19745be
2020-08-13 13:21:03 -04:00
Tao Sang fdef6f722f Apply constexpr on global constant varaibles
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef
2020-07-22 22:14:13 -04:00
kjayapra-amd 16e6b65b5c SWDEV-240165 - Move all amd::MemObjMap_ reference to ROCclr and only allow base ptr to get ipc handle.
Change-Id: I9de10a0c4ba4dee3b3c8b972966840ab807001d8
2020-07-09 21:19:45 -04:00
Tao Sang da94cd0de1 Support numa policy set by user
Add hostNumaAlloc() to support numa policy set by user

Change-Id: Ib6c3e838aa53e3d9b3db9735c585df46a1c98944
2020-06-23 18:57:03 -04:00
German Andryeyev c5afd5d412 Initial HMM support
- Expose ROCclr interfaces for HIP usage
- ROCr interfaces aren't available in staging, thus control the
build with AMD_HMM_SUPPORT define

Change-Id: Iadc2bcc230e78d3b0dc22b235189c8cc80843446
2020-06-12 09:06:07 -04:00
Rahul Garg 617538074c Fix IPC create memory failure
ROCr expects granular size in hsa_amd_ipc_memory_create

Change-Id: I7c266aa2eef8304f105298a7a668f4c4b3fb5f5a
2020-06-11 13:02:54 -04:00
kjayapra-amd 1b0882e061 SWDEV-239327 - Dont call hsa_amd_memory_pool_free from ~amd::Memory() for obj created by passing devptr.
Change-Id: I315fd502df6bb1bf66dd24eac9325f1439e432ad
2020-06-05 18:42:03 -04:00
German Andryeyev 3828a61413 Make sure runtime sync before CPU access
Change-Id: I52882788ded187b3f735257a188b1b08d8502147
2020-06-05 12:00:08 -04:00
kjayapra-amd 53a890b499 SWDEV-237467 - Return proper hip error codes incase of ROCclr IPC API failures.
Change-Id: I1d018918ed71f6d80846b3017f7a15f4ab496554
2020-05-22 22:10:15 -04:00
German Andryeyev 8904848abc Set CPU access flag for SVM
Make sure all GPUs have CPU access flag for the fine grain buffer.

Change-Id: Ifc843c2807e70a271b269192ae7859205ff458f3
2020-05-13 16:05:46 -04:00
Jason Tang b4f1239f34 device/rocm: split gfxVersion to major/minor/stepping
Change-Id: I1e437eaee30794147713d9516229211670f01d90
2020-05-12 12:17:13 -04:00
Michael LIAO 503ef06555 Clear executable permission.
Change-Id: Ia0d363b1ba89d7947e5b5a55cb67edba86f0515e
2020-05-07 10:38:58 -04:00
kjayapra-amd 7458bf9964 SWDEV-229840 - Improve error messages on ROCCLR Layer.
Change-Id: Iab7d9156cdc206db86385aa05023a0095ed40f92
2020-04-19 20:01:49 -04:00
Vladislav Sytchenko c781f4d419 Don't call updateFreeMemory() if the allocation failed
Change-Id: I978cb2e463914f6a48b3d4a9057c0f67e7bdb646
2020-04-09 18:41:11 -04:00
Alex Xie 43b9863e17 SWDEV-229731 - [Lnx][Rocm][Navi]Support images in full Opencl Conformance tests
1. Enable pitch workaround
2. When we use copy image, we don't need to create the custom pitch image
3. wrtBackImageBuffer_ stores device memory object, not amd image object.

Tests:
conformance kernel read / write test pass with this code change.

Change-Id: I7dca3127adde6ac83e78dd270a2256ebed55c60d
2020-04-04 09:43:03 -04:00
Jason Tang 9cfb973c3f SWDEV-207312 - Fix images_write_cube failure for gfx10
Change-Id: I7f6a8c77eb712103e4c0a5f36bba95093ffbff98
2020-03-12 17:25:52 -04:00
Vladislav Sytchenko 696d00e71b Correct pitch alignment calculation
When we're aligning rowPitch to imagePitchAlignment, rowPitch is in pixels,
but imagePitchAlignment_ is bytes, so we end up overaligning the pitch.

Convert imagePitchAlignment_ to pixels before doing any logic.

Change-Id: Ia5ab9d54bed150fe974e86b060dbadc196165b29
2020-02-20 18:00:27 -05:00
Jason Tang 290b42625a SWDEV-207312 - Comment out incorrect cl-gl inter-op code to facilitate Linux-Pro testing
Change-Id: I273476465332ffcda50a6095f839e1bc07863c8e
2020-02-19 17:56:45 -05:00
German Andryeyev 374f612b7c SWDEV-193956
[hipclang-vdi-rocm][perf]~45% to 50% of Performance drop on
rocBLAS_int8 test

- Enable AMD_OPT_FLUSH optimization by default to match HCC
- Disable CPU writes to GPU memory on boards with large bar,
because it requires HDP flush tracking.
- Enable L2 cache on kernel arguments, because L2 will be
invalidated on memory reuse .

Change-Id: I124cf250bdd4d19c523ce542c163813828f8fbdc
2020-02-18 14:26:00 -05:00
Laurent Morichetti b4c6143a2f Update copyright info
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
Laurent Morichetti 20c7173849 Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00