This code change is to improve error handling.
This code change does not fix issue itself.
Before this code change, hostcallBuffer_ point is initialized in the end of
create() function. If create function fails and returns early,
hostcallBuffer_ point is not initialized. This non-initialized point can
cause access violation when object is destructed.
This code change put the initialization of the pointer in the constructor.
Change-Id: I7fb6e764eb0547196dca03db237e49d3ff0fd06a
[ROCm/clr commit: 5528812aa9]
Adding virtual memory management APIs to rocclr.
The HIP layer will handle virtual allocs on devices.
Change-Id: Ia978f105c2c3fed3959c77580ba228e845105754
[ROCm/clr commit: b5f555f9ec]
Remove assert for kernel arg size, because COv5 reports a value
bigger than the actual usage in the most of cases
Change-Id: I8e15bc45a9e21b58a5894f9977511ca84408ce61
[ROCm/clr commit: 2be0b1e612]
It can be too early to allocate memory at the begining of
Device::create() under PAL
Change-Id: I4bd76db7be3f6fb246243ea68022d8b0f860471d
[ROCm/clr commit: 3af3fe10de]
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock
Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
[ROCm/clr commit: 95d55fdfa8]
OCL2.2 requires SPIR-V and runtime doesn't support it.
Make sure PAL backend doesn't report any SPIR-V support.
Change-Id: I8d179069674205b54f7d20d149bcb675bee5cdb0
[ROCm/clr commit: 0bf395af39]
Metadata in Codeobject version 5 is the extension of CO3 and CO4.
Add the detection of the new fields and program them in
the setup of the kernel arguments.
Change-Id: I27e58df77320ad00f4f16d35912668db803826af
[ROCm/clr commit: be6a06384e]
Use HSA_AMD_AGENT_INFO_COOPERATIVE_COMPUTE_UNIT_COUNT to get compute
units. This is needed to work around assymentric CU harvesting bug on
gfx90a. Add a new device property to get the max available CUs on the
device.
Change-Id: I878f38f14f16c1af01fc0a77157aea1e816a63b8
[ROCm/clr commit: 33aca5a4a6]
Report proper target id for xnack in HSAIL path. Runtime
will use ISA table and report hsailName().
Fix offline compilation path for PAL.
Change-Id: Ic0250bf6b9c193d867aec9800a319da1bf00c3ee
[ROCm/clr commit: a543d4a860]
When OCL failed to obtain function pointer from GL, we should not call it.
Change-Id: I50f69d270ce445386906a286e44c4e8c83722302
[ROCm/clr commit: 15101e704b]
With SAM on, don't force Persistent for allocations
in HIP. This makes ROCCLR go down paths we don't want
for HIP.
Change-Id: If54cc16fa891d4cfdc761c6ab21ad707627e822a
[ROCm/clr commit: 5243552768]
- Create hash values for binaries
- Add the binaries into RGP trace
- Add corresponding hash value for every dispatch
Change-Id: I2c3ce004d69f37d0d46bc4744e12f24273517f5e
[ROCm/clr commit: 2a298f2ec3]
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.
Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121
[ROCm/clr commit: 55a0cf0b0c]
Change the scope of hostcall buffer access lock during destruction.
Make sure wait() returns the signal value after timeout. That
matches ROCr behaviour for HSA signal wait.
Change-Id: I3df34207e0c2e21972ec8052777e5742bda1dca0
[ROCm/clr commit: 9a9d10a10b]
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.
Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
[ROCm/clr commit: 21ba34d0fe]
PCMark10 counts the time spent in clCreateKernel as part of execution
time, so as workaround for the PAL path, move code object loading
back to clBuildProgram.
Change-Id: I3b9cf1879ece08ab59f447ec165b0525bc8593a4
[ROCm/clr commit: 1d0364e590]
Reuse FillMemory function, that should fix the cache syncs from the host
Change-Id: Ieebec5fc3ed3a322b88d5187c8dca4805ec6f84b
[ROCm/clr commit: 24442be35a]
Redshift sees around a 3x performance uplift this change.
Turning this on for OpenCL might cause unwanted behaviour, due to
apps like RSX running in the background all the time.
Change-Id: I9f32d5f2e05b6697a8aaa9ddf74474b5531bb7e1
[ROCm/clr commit: 2f00782829]
Note that this requires base driver CL#2340320+ to have SQ interrupt
functionality enabled by default.
Change-Id: I04b936819ebe1eb7cf5de1db4fafe83af3a1b5f6
[ROCm/clr commit: 4171e9e0a3]
Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.
HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.
Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456
[ROCm/clr commit: ffbf368f4c]
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset
Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
[ROCm/clr commit: 924695fb5e]
This reverts commit 9df70fa03ce60d47247eb0e8f278e1f8dbd33d6e.
Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.
Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7
[ROCm/clr commit: 6566361144]
Christophe Paquot
Alex (Bin) Xie
Alex Xie
pghafari
German Andryeyev
kjayapra-amd
Saleel Kudchadker
Todd tiantuo Li
Payam
Satyanvesh Dittakavi
haoyuan2
Julia Jiang
Sarbojit Sarkar
Jason Tang
Vladislav Sytchenko