Below logic is causing a crash in the CL-GL interop. As a workaround,
limit it only to HIP.
Change-Id: I12e81d035ebd80a4a9a09eb6eea2fae7040d90c9
[ROCm/clr commit: 74ccf71d53]
Add ref counting to ProfilingSignal class to track the last release.
If a signal was used in the marker, then don't reuse it,
but create a new one for internal usage.
Don't rely on HSA callback for the command status update if there
are no pending dispatches.
Change-Id: I19f14ed9d80acfe79993b343b2187635f8428a20
[ROCm/clr commit: ff15c0893e]
HSA signal calback may occur during the actual marker submit. That
may cause a deadlock, because shared lock_ object. Create the new
notify_lock_ field to protect the notification.
Change-Id: I9752af84e59895530620fac3932c6fc276de8658
[ROCm/clr commit: f34c1b9ff8]
Runtime can't assign internal HSA signals for HIP events, because
HIP application can destroy the HIP stream or signal reuse may
occur internally. Switch to global HSA signals for HIP events.
Change-Id: Ieaea2d6b039e492b2e7c5112782a8f4e601e50a1
[ROCm/clr commit: ce8dad2ecc]
We do not want to release resources during setStatus in HIP because of Graphs
Change-Id: Idc7b188ab5f8be6975ea91005dd2bbf177401f8c
[ROCm/clr commit: 133287f31f]
If AMD event contains a reference to a HW event, then runtime
could check/wait for HW event. CPU status update will occur later
after HSA signal callback, but it's not important for the result.
Change-Id: I591391a953bbdba6a25ac07e2cd98aeb17cd4596
[ROCm/clr commit: 85c70a7495]
For DD, send a NOP packet so that we leverage the handler to indicate
completion.
Change-Id: Ie57ea0124a8497d39cc49da1c4575c2cd86b9319
[ROCm/clr commit: 9d0846e732]
With direct dispatch enabled make sure the queue is done before
destruction.
Change-Id: Ib80af3efb97dfb93e2dce60a11db34fb5c45f5cd
[ROCm/clr commit: a81756bba3]
Currently only clGetProgramInfo/CL_PROGRAM_KERNEL_NAMES requests it.
Change-Id: I38be16999ac2f631850fb5e07eeae54bfbe161ad
[ROCm/clr commit: f2a077f62f]
Currently LiquidFlash cannot be supported from Github Enterprise,
hence we need to be able to build with out it.
Allow this by setting -DWITH_LIQUID_FLASH=0.
Change-Id: I975e8ee16b7ba033e3eb95fe40955d8c1d4779b7
[ROCm/clr commit: 7034e749e3]
aclutGetTargetInfo() is an internal compiler lib helper functions. This
will not be imported in the HSAIL shared library build, however it is
simple enough that we can maintain our own local copy of it.
Change-Id: I91d1a336c7da027bf8a7df8fae86a25add533611
[ROCm/clr commit: 7fd1e9c10a]
This change makes HSAIL usage similar to that of Comgr. By default, the
runtime will statically link against it, however if HSAIL_DYN_DLL is
defined, then the runtime will try to dynamically load HSAIL.
Currently stick to statically linking to HSAIL. In a feature patch the
dynamic loading behaviour will be enabled.
Change-Id: I6a78a4375975cf847f236b200404c8cf941d012b
[ROCm/clr commit: c7b50bb890]
HIP tests require HIP callbacks to be processed in another thread.
This change will use a thread from HSA signal callbacks to make
sure a HIP callback was done asynchronously.
Also process the callback before changing the status of command
Change-Id: Icef85d0e0f808663882cf6881ff1be3e5eca29ac
[ROCm/clr commit: 7f32d0b425]
- Don't notify if the batch is empty, because that means
the current command was processed already.
- Disable pinning optimization to avoid a race condition on stall.
- TS marker submition requires extra AQL barrier
to track the status.
Change-Id: I17eff4ad12ac66cfe1bb44048bebb1891805279d
[ROCm/clr commit: 24299e25bd]
Skip notification for markers with direct dispatch only,
since they are blocking always
Change-Id: I6bb17650f73371dae6e29c59fd6bb2012cc062fd
[ROCm/clr commit: a9b0e20d26]
Direct disaptch doesn't insert extra barriers for Markers if
AQL barrier was the last issued command already.
Change-Id: I00fbc658547d83dd3ee64ec391ed50e5f8a08e30
[ROCm/clr commit: 0587fb7450]
- Avoid GPU wait on the marker submission and update the command
batch after HSA signal callback upon HSA barrier completion.
Change-Id: I5c1c97212aefc2ae4b99aa9e2a81627ee9a38c1c
[ROCm/clr commit: 6966d8098e]
When OCL ROCr backend performs CL_MEM_COPY_HOST_PTR it may attempt
to have access to amd::Memory object it's currently creating,
but it's not ready yet. The logic creates a temporary dummy object
to perform a copy transfer. The new change will make sure runtime
skips allocation of the same device::Memory object second time.
Change-Id: I14c6a00a3941fdcaa6aea299e9f096e4c3f5cadf
[ROCm/clr commit: 1fde842703]
Vladislav Sytchenko
German Andryeyev
kjayapra-amd
agunashe
Saleel Kudchadker
Christophe Paquot
Ravi C Akkenapally
Jason Tang
pghafari
Anusha GodavarthySurya
Sarbojit Sarkar
Satyanvesh Dittakavi
cjatin