Graf Tiomantas

4 Tiomáintí

Údar SHA1 Teachtaireacht Dáta
Sang, Tao ec8ff45a1d SWDEV-514141 - Fix zero clock rate issues (#4)
1.Remove clock functions from some tests that don't need them.
2.In some memory pool tests and coherency tests, timer-based kernel
delay isn't reliable, use pinned host based notification instead.
3.Add CHECK_PCIE_ATOMICS_SUPPORT before some tests.
4.catch/unit/memory/hipMemoryAllocateCoherent.cc is removed
as it is useless and originally excluded in building.
5.Some tests can still pass even if clock rate =0, thus they
  will be kept as is.
6.Some logic and format improvement in some tests.

Change-Id: I6b3c6bf54c61cffd45cd6f17c75998f751b75725
2025-06-11 21:11:25 +05:30
Rupam Chetia 456001c308 SWDEV-311271 - [catch2][dtest] Adding test for mempool and stream ordered memory APIs
Change-Id: Iddeb111e4b512bfc7422abc8e784b0a8e8fb133d
2024-06-18 00:22:49 -04:00
Branislav Brzak 6c23e25c86 SWDEV-448163 - Fix Doxygen warnings
Change-Id: If72e312461a72920b6a482009c9aef4cf92f2e1b
2024-03-25 05:18:34 -04:00
Nives Vukovic dbc1a9d073 EXSWHTEC-36 - Implement tests for basic hipMemPool APIs (#437)
Change-Id: Ice34feae7675699b04153d6fc3e10297428018b5
2024-02-15 19:39:31 +05:30