Add HsaMemFlags Contiguous bit for hsaKmtAllocMemory to allocate
contiguous VRAM, to support RDMA device with limited scatter-gather
ability.
Check KFD ioctl minor version >= 17.
Change-Id: I0db00dad125b2b7be523f343082641f59b850423
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
HsaMemFlag new flags added and the number of the reserved bits is
reduced, and generate value overflow compilanation error.
The reserved bits is not used, remove the init.
Change-Id: I603596977dfd558ce31ead03711d7c5ce5ee5b71
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Fix lazy pointer initialization for dedicated PC Sampling queue.
Previous implementation would always create a queue on GPU agent
creation instead of creating the queue on first use.
Change-Id: Icf300f2b162e59143ba61ba182d9bee6e1308fc1
Fix Musl libc NULL errors and unsupported pthread funcs for compatibility.
Also ensures cleanup and error handling irrespective of CPU affinity override.
Fix submitted by github dev - AngryLoki
https://github.com/ROCm/ROCR-Runtime/issues/181
Change-Id: Ia487315e504112be5d3370756f23f6e23b9ae4be
New hsa_amd_queue_get_info API to support:
- HSA_AMD_QUEUE_INFO_AGENT: Agent that owns the underlying HW queue
- HSA_AMD_QUEUE_INFO_DOORBELL_ID: KFD doorbell ID of the queue
completion signal.
Change-Id: I98842131bcbdd08552649791a5d43e578a615808
When doing a coredump, we try to park the wave and save its PC in
ttmp7/ttmp11, but these registers will be overwritten by PC Sampling
requests.
Change-Id: I60fb734eb3bed4ee3cc8d8bba9ec4a527fff9671
Flush is used by the client to retrieve data that are currently stored
in the buffers. This is used by the client to retrieve current data when
the buffers are not full.
Change-Id: Ib8304dcdfb2797cb060ec72df4970d95cf6be348
Each time there is enough data to fill the client session buffer,
callback the client data ready function to transfer the buffer contents
to the client.
Change-Id: Id79775426fa6d22e00dc2ef6f55c439eacb9b2af
Retrieve data from the buffers previously set in the 2nd level trap
handler TMA. We use a double buffering mechanism to allow the 2nd level
trap handler to write to one buffer while we are copying data from the
other.
Co-authored by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Co-authored by: James Zhu <James.Zhu@amd.com>
Change-Id: I252c381ea06b8cf927c4f9af6ea59dedc3717fbb
Code is valid for gfx9 GPUs excluding gfx94x.
1st level trap handler will use TTMP13[22] to indicate host trap and
TTMP13[21] to indicate stochastic trap.
For each PC sampling method (hosttrap and stochastic), we use a double
buffering mechanism to transfer data between GPU and host.
The GPU will dump data into one buffer while CPU may be reading data
from the other buffer. There are 2 separate signals, one for each
buffer.
When signal != 0, the buffer belongs to the GPU and the GPU can write
to it. Once the buffer has reached the high watermark, the GPU will
set the signal to 0 to wake up the host and so that the host can try
to switch the buffers and read the data.
Co-authored-by: David Yat Sin <David.YatSin@amd.com>
Change-Id: If3eb0913e52fb4788059a71e5feca334612f3d5d
Create dedicated CP queue with highest priority for PC Sampling. Reduce
the highest priority that LRT's can set for existing API so that PC
Sampling queue will always have highest priority over any other CP
queues
Change-Id: Ia70d74415edc83b4862a3e18dbdbd7cebe73ab47
Implement PC Sampling session create and destroy APIs.
Change-Id: I93370d3d01b74ee15e71b8b0e20feb8f0066a3dc
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: Vladimir Indic <Vladimir.Indic@amd.com>
Change-Id: Ib0c64356a1a4616b12d5dbeebe16273fe2a84abe
Add new PC Sampling API to list the supported PC Sampling methods and
options on a specific agent. If there is already a PC Sampling session
active on this agent, the list of methods returned will be reduced to
methods that can be run simultaneously with the current active session.
Change-Id: I42ac2b8f30d5c368faf8ed4cf37ca4134db22985
ExecutePM4() function can optionally accept extra arguments for
acquire fence scope, release fence scope andcompletion signal. When
a completion signal is provided, ExecutePM4() does not wait for the
commands to complete.
Change-Id: Ib2a433b7bce1cb6260be8b76fe902335bd5dfada
Hard limit for scratch is 4GB per XCC and checks in case user specifies
values exceeding this value
Change-Id: Ib3cade762ff66c7e7d6a2d311e482cacbcf2b0de
- Per-executable contexts should be used from now on
- Global contexts are left as is for now for backwards
compatibility and will be phased out in follow up
patches.
Change-Id: I6291abf865c7ed24ee71f5065e539afc23f5ce64
This reverts commit 5c520f4544c654e5f18e05cabd1c63d64473cfab.
Reason for revert: This patch is introducing a synchronization related bug in Unit_hipGetSetDevice_MultiThreaded testcase.
Change-Id: I367e4d4f1d75b21658ac1127c58982894a97cedb
The build tree was missing a level of nesting, causing diversions based
on in-tree/out-of-tree use.
KR: Also fixed kfdtest paths
Change-Id: I8638b6d6227daabddd8eaa2aa387ba578b8dfab8
Signed-off-by: Stella Laurenzo <stellaraccident@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>
When allocating memory for MES AQL queue structure, the PreferredNode
is set to the device index of GPU to hint the location where the BO
needs to be created. But we need to ignore the device index when calling
bind_mem_to_numa.
Change-Id: Iae69fe02bfd48c5a3bd495319f6f2706d6e8aea2
The function Init() called by one of the constructors of lazy_ptr is undefined.
Replacing with reset method sets the object to an uninitialized state and assigns a new constructor function
Fix submitted on github by zhoumin2 - https://github.com/ROCm/ROCR-Runtime/pull/184
Change-Id: I7d906d526ce7fe7e2548b01810e6395b13497bf3
Add pc sampling support.
Change-Id: I08199024ba5a8eb2845c048d499fc8fcd260d2e8
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
Add pc sampling support
Change-Id: I2c472ce00ff8648904cf7e585687e81d3f493049
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>
To allocate GTT memory for MES AQL queue structure, KFD will create GART
mapping for the memory to be accessed by MES.
Change-Id: Iae7b33d1e70861109f1551d3a71dc60dfde9de61
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
The purpose of this patch is to add KFDQMTest.QueueLatency to
kfdtest.exclude file temporarily for the following ASIC filters:
-GFX940
-GFX941
-GFX942
This test is failing due to an issue with the way it was coded,
not due to an issue with the ASICs it is now blacklisted on.
Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: Ic993629a2400449f598e73fe616a4572a38e2310
Reduce test case size if running on emulator.
Also, refactor code as both test cases had more than 80% same code.
Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I5899ee24244a6f0aa6b56fa8a4701b0b1e344b9f
Reduce number of iteration for test case to run in reasonable amount of
time.
Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I19a7ec0d5f03c54d6691aae3cf7432754c7481cc
David Yat Sin
amd-jmacaran
David Galiffi
Philip Yang
Shweta.Khatri
Joseph Greathouse
Konstantin Zhuravlyov
Stella Laurenzo
Mihai Preda
James Zhu
Ori Messinger
David Belanger
Xinmudotmoe