Commit Graph

40 Commits

Author SHA1 Message Date
Sean Keely 3959e99131 Add deallocation callback test to rocrtst.
Change-Id: Ia20abd8f1f64213eea0c3c1c771cc229cf38fd5d


[ROCm/ROCR-Runtime commit: 4fafdcb00c]
2019-07-19 14:17:21 -04:00
Chris Freehill 970cca3731 Temporarily disable Debug test
Change-Id: Iabb238fcd78b9c2eb0c085b19ab93b8c9e538140


[ROCm/ROCR-Runtime commit: 8caa6c0b01]
2019-06-29 04:55:35 -04:00
Chris Freehill 9d70b6a420 rocrtst fixes for hsa_signal cleanup and aql packet dispatch
In several places aql packets were written to queue all at once
instead of doing the header atomically. These cases have been
fixed.

There were a few hsa_signal leaked that have been addressed.

There was some duplication of code that has been addressed.

Addresses ROCMOPS-456

Change-Id: Ia1869bc370f92e49ac560301df47741d5f76978e


[ROCm/ROCR-Runtime commit: 081a2cc875]
2019-06-21 17:34:10 -05:00
Chris Freehill 74eb2440c3 Temporarily disable some failing tests
Change-Id: Iee713bb963db812c36ce2568aee2a4f8409c52e5


[ROCm/ROCR-Runtime commit: 259a1bac18]
2019-06-14 08:36:11 -05:00
Chris Freehill 8f1a9494cd Fix async memory test; temporarily disable NUMA memory test
Change-Id: I1c0618f5dba513c1cf8fafb5fc64e5c811df8454


[ROCm/ROCR-Runtime commit: 626f13a88b]
2019-01-31 09:14:54 -05:00
rohit pathania d7602a31fc Kernel group memory dynamic allocation, basic allocation and free test
Change-Id: I17fdb77f17567ac1b429d9a571cac70ac1e64dd4


[ROCm/ROCR-Runtime commit: 6df6ef778d]
2018-06-15 10:49:10 +05:30
rohit pathania 189bd446b5 Modified memory atomics on non Large bar system and pool info test memcmp issue fix
Change-Id: I951fdb6c91508f43b1c51f7eb92870543fc58e53


[ROCm/ROCR-Runtime commit: d8e47ba115]
2018-06-11 18:49:29 +05:30
Chris Freehill bb280f26f8 More emulator friendly tests/examples
Change-Id: I27ab26add14743dfb065238129c14b48913d9df8


[ROCm/ROCR-Runtime commit: 12a81ae96f]
2018-06-08 17:58:37 -04:00
Chris Freehill a2e031949f Disable Signal tests
They are breaking Jenkins builds.

Change-Id: I1647049abee0ebc2a4751e66d9ceed56cadc4c3e


[ROCm/ROCR-Runtime commit: 8a6f0d6b24]
2018-06-08 15:47:09 -04:00
srinivas Charupally c6b1838f36 Adding Signal Kernel tests
Change-Id: Ie34de41741a7c4731a0ff3761e940971b6f08745


[ROCm/ROCR-Runtime commit: f0a1b310fd]
2018-06-06 16:25:18 +05:30
rohit pathania 1e991128f5 Concurrent testing for queue write index
Change-Id: If5b60b943a861d8f97d01b7fd8f757fdb36845c6


[ROCm/ROCR-Runtime commit: d0f6da277d]
2018-06-05 11:57:38 +05:30
Chris Freehill 01433053cd Make emulator friendly
Disable some tests that rely on features not typically available
in emulator and use smaller data and iteration sets

Change-Id: I587bf83162b114719e0361109ed44c6bf2adf34c


[ROCm/ROCR-Runtime commit: 2c8cbf61c3]
2018-06-04 18:51:09 -05:00
Chris Freehill 8b6b062957 Disable Aql_Barrier_* tests
Change-Id: Ibe08b88c101a60e4c6f0c61cda756e2cb5857d7d


[ROCm/ROCR-Runtime commit: 845a539478]
2018-06-04 11:46:08 -04:00
srinivas Charupally 15a708e717 Adding Aql tests
Change-Id: Id22dcafbf0ea0b346f3a03d4acef27350b706f36


[ROCm/ROCR-Runtime commit: a632bfddb2]
2018-05-31 15:29:37 +05:30
srinivas Charupally 87a76fb0ec Adding Signal tests
Change-Id: I1815267a0e19614a84013e797bd3df3e77ee8179


[ROCm/ROCR-Runtime commit: 2c551d38b6]
2018-05-30 01:40:31 -04:00
rohit pathania a9638cd006 Different Atomic operation tests on GPU and system memory
Change-Id: I04154b588086d49142a64c8fe4826d041ded2991


[ROCm/ROCR-Runtime commit: 044fb8dc27]
2018-05-28 22:18:48 +05:30
rohit pathania d77f587d15 Queue validation tests and memory alignment tests
Change-Id: I96d8c2898795240288517bdcbc2b48ff2cc04f66


[ROCm/ROCR-Runtime commit: 08a253684b]
2018-05-28 14:26:05 +05:30
srinivas Charupally c35946cb79 Adding concurrent shutdown, reference count and max reference count tests
Change-Id: Ib6f40585bf1ab2b1d6f33bbb1675e13545a23a4e


[ROCm/ROCR-Runtime commit: 2c1919c681]
2018-05-28 00:51:05 -04:00
Qingchuan Shi 91b3e8d552 Add debug trap rocrtst.
Change-Id: I73682d7a2ad51eed9988075e012478a1afc76c7c


[ROCm/ROCR-Runtime commit: 3a46556dcc]
2018-05-22 13:31:45 -04:00
rohit pathania 32ffaeb7d1 Memory Concurrent tests for pool Memory allocate, Memory free and get pool info
Change-Id: I6a1343348e400fe466e041d651adaa67be561a21


[ROCm/ROCR-Runtime commit: 47af1d673e]
2018-05-14 01:30:54 -04:00
Chris Freehill 43a9e81e4a Added rocm-smi-lib calls with updated interface
Change-Id: I62b59dca5135ec012f11b249c78b04e5e8e2dd9a


[ROCm/ROCR-Runtime commit: 11e13704ea]
2018-04-27 18:36:54 -04:00
srinivas Charupally ee40fbd721 Adding concurrent init and init shutdown tests
Change-Id: Ifdbda16ae6c93a86373557f26eb414e40775d343


[ROCm/ROCR-Runtime commit: 8c8cd2dbd0]
2018-04-24 11:56:50 +05:30
rohit pathania 3cf867da15 Memory Allocation Negative tests
Change-Id: Icdd355f2351968dd76a3bc466636e223573cfb16


[ROCm/ROCR-Runtime commit: b1b036acb8]
2018-04-23 01:49:43 -04:00
Chris Freehill 51ac0cfd8c Revert "Re-enable rocm-smi with new c api"
This reverts commit 075f246147.

Change-Id: I9866610597a6de97a3c06ef9646f0afc85f149f4


[ROCm/ROCR-Runtime commit: 0d9e71a63a]
2018-04-07 19:59:13 -04:00
Chris Freehill 075f246147 Re-enable rocm-smi with new c api
Change-Id: Idf393f31522bac8ac0c3c03a930ef66d97ce5fa2


[ROCm/ROCR-Runtime commit: 2e81d33395]
2018-04-07 18:55:30 -04:00
Chris Freehill 827e36d1b8 Reenable Memory_Max_Mem test
Change-Id: I2da50f886cd8d28d0f9ad8b8f77cfa13d392bf01


[ROCm/ROCR-Runtime commit: 81c923b26f]
2018-02-13 17:37:25 -06:00
Chris Freehill 942295129d Completely disable rocm-smi (take 2)
Change-Id: I68f403c539163bfe00ee2b59dbd36d1c6d7669f1


[ROCm/ROCR-Runtime commit: 146b3871df]
2018-02-12 06:43:47 -06:00
Chris Freehill 17c20b9d22 Completely disable rocm-smi from rocrtst until rocm-smi-lib is updated
Change-Id: I5cce06a2bbde7a3a48e391022c793a462794c6d1


[ROCm/ROCR-Runtime commit: bd0c4efc34]
2018-02-11 21:42:25 -06:00
Chris Freehill 2b39004aa6 Temporarily disable rocm-smi to integrate with new rocm-smi
Change-Id: I06701cd4ac80bb4f3a9ae48d5374b7d4a788f8a4


[ROCm/ROCR-Runtime commit: 8bf85cc668]
2018-01-26 06:44:01 -06:00
rohit pathania ea550637f0 Added CPU to GPU and GPU to CPU MemoryAccess Tests, Added enqueue latency Tests
Change-Id: I18643d283101b792fa25705c8149ddc5a9eefe73


[ROCm/ROCR-Runtime commit: ee917eca68]
2018-01-08 04:11:32 -05:00
Chris Freehill 62b331353a Re-enable IPC test
Fix for  fixes this.

Change-Id: I63a8d1a16d5029f240f075bb97ab6a1156b5cab2


[ROCm/ROCR-Runtime commit: 473be763ff]
2017-11-08 10:02:51 -05:00
Chris Freehill 42bbc5ee85 Undo temporary namespace change
Change-Id: I7f4c06f7037713db855b51367256cf4c7ba41860


[ROCm/ROCR-Runtime commit: 5a3230af66]
2017-10-20 20:02:13 -05:00
Chris Freehill ca41ce6730 Temporary change to namespaces to adjust for smi change
Change-Id: Ic91bfb678912a82214f0a462a4b57e531f12977a


[ROCm/ROCR-Runtime commit: 50a3d9402a]
2017-10-20 13:12:06 -04:00
Chris Freehill 05e78f7910 Make rocrtst use new rocm_smi library
Change-Id: Id688d6d6d5ff106a23f5b55eaca4e723c39433a3


[ROCm/ROCR-Runtime commit: 75eb3316aa]
2017-10-06 09:41:10 -05:00
Chris Freehill a4bc830f61 Temporarily diable Max Memory alloc. test
Change-Id: I13cfc77bd5b823354e60a3023356255c72c1fd6c


[ROCm/ROCR-Runtime commit: 0adfe5a18e]
2017-10-03 00:19:08 -04:00
Chris Freehill 76b9f76690 Add IPC test to rocrtst
Change-Id: I6a40375790a184df11afc88b863cafc3d244e92a


[ROCm/ROCR-Runtime commit: c8b92c5087]
2017-10-01 11:01:31 -04:00
Chris Freehill 27631645c4 Use rel. dir instead of abs. in CMake;Have a default number if iterations
Change-Id: I097fd229338ed520196cc4ed1ef1d00fe538e50c


[ROCm/ROCR-Runtime commit: 7d84190c4e]
2017-09-19 14:13:49 -04:00
Chris Freehill af02d06972 Async mem. copy test with NUMA awareness
Change-Id: If655ac4c087be2d379e868aad83812f2437d78b9


[ROCm/ROCR-Runtime commit: 92e46584f8]
2017-08-30 21:35:37 -04:00
Chris Freehill 9aae431f6d Added max. single mem. allocation test.
Change-Id: Ie81c6af0502fde56225b1e197801cf04b474feb2


[ROCm/ROCR-Runtime commit: cf24f7bb78]
2017-07-31 12:04:55 -05:00
Chris Freehill b39089e54c Reorganize tests
Change-Id: I45f92d61070b325bcb57bd72e4a68e7d6495463c


[ROCm/ROCR-Runtime commit: bddc89e703]
2017-07-28 11:32:20 -04:00