Make hipMemset asynchronous with respect to the host unless
destination pointer refers to pinned host memory.
Change-Id: I5ba230e0cc622aa076dc94692a4c43a57dd2df7b
Make sure the comments in the code match the actual behavior.
HDP read has internal HDP read cache and doesn't use L2.
Change-Id: I667a4643b0e0d6529008f5e1a0a3269456c55b4e
Modified hipPointerGetAttributes to support hipHostRegister ptrs and mapped device ptrs from hipHostRegister
Change-Id: I2f4cf12e09578768308f644123d6d4bdccbd77a8
CPU read updates L2 with the latest values and requires
invalidation after, because SDMA doesn't use L2 and data can become
out of sync.
Change-Id: I98d1c91ca78a103fa5409e638f97485d62d5b11e
The older compiler does not promote integral
arguments to double, instead it uses float.
This patch tries to support the old compiler
headers, and also the newer one.
Change-Id: I01e0b96a82ecddc6230cb5baf2573a318b25445b
Remove hip-hcc codes from hip code base
Simplify hip CMakeLists.txt to exclude hip-hcc
Simplify cmake cmd for hip-rocclr building
Some minor fixes
Change-Id: I1ae357ecfd638d6c25bca293c1724b026be21ecd
HIP supports compiling kernels from LLVM IR into executable.
The device LLVM IR needs to be compiled into a fat binary
object. This device object is embedded into a host object using
llvm-mc directives. Then, any host linker may link the host and
device objects together into an executable. A README was added.
Change-Id: I8ebb6ae86b7ab4290f7cba2eea5584d73a7c453e
HIP supports compiling kernels from assembly into exec.
The device assembly needs to be compiled into a fat binary
object. This device object is embedded into a host object using
llvm-mc directives. Then, any host linker may link the host and
device objects together into an executable. A README is added.
Change-Id: I59d3a8b5363073810ffc3aa0d57f21b0df272369
When OCL ROCr backend performs CL_MEM_COPY_HOST_PTR it may attempt
to have access to amd::Memory object it's currently creating,
but it's not ready yet. The logic creates a temporary dummy object
to perform a copy transfer. The new change will make sure runtime
skips allocation of the same device::Memory object second time.
Change-Id: I14c6a00a3941fdcaa6aea299e9f096e4c3f5cadf
The HIP-Clang math headers upstream have been updated
to perform type promotion on math function overloads.
If any argument has integral type, it will be cast to
double.
Change-Id: I38d9e6240c40c4092b946851469498b2ae6500ae
Make sure the logic updates the command status when it's done in
HW, but not on submission.
Add the last command tracking, otherwise queue sync logic in the HIP
upper layer may skip synchronization, assuming the queue is empty.
Change-Id: I2d046792553e74df090a10f7d7a78914610f6df2
SWDEV-261229: Change atomicAdd float implementation to use clang builtin
along with deprecating atomicAddNoRet
Change-Id: I5e98034fec54ee1a2b85d5f56273e34945d49ea3
Add a flag to record gpu TS in a marker, also disable marker flush
if there was already a marker submitted before.
Change-Id: I9cdf8e49137690c0050fe9370764dd059855a2f8
Use barrier packets for every profile marker that gets submitted
and use the completion signal to get GPU ts. This gives most accurate
dispatch time. Club cache flushes with profile marker if there is a
pending dispatch that needs cache flush. This optimization saves on
extra barrier and helps wall time
Change-Id: Ib62d6d7aabf4743827b561be6c9c5afa813203da
agodavar
jujiang
Rahul Garg
German Andryeyev
Sarbojit Sarkar
Evgeny
Vladislav Sytchenko
Satyanvesh Dittakavi
Payam
Jason Tang
Tony
Tao Sang
Aaron En Ye Shi
Alex Xie
Saleel Kudchadker
Jatin Chaudhary
Chauncey Hui
Sudheer Kumar
sumanthtg