7fb80a027a
SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261.
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Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca
2022-03-31 09:02:33 -04:00
ef3d6f7b28
SWDEV-308644 - update blit kernel setup in rocm
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Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c
2021-11-15 13:28:07 -05:00
7413b7f79b
SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
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Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85
2021-10-05 18:12:44 -04:00
cbb8d82bdb
SWDEV-292525 - [vdi] Path to streamOps shaders
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Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.
Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
21ba34d0fe
SWDEV-297448 - Add 64bit and 16bit write support
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For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.
Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
2021-09-08 12:30:04 -04:00
d96481fb36
SWDEV-293742 - Update copyright end year VDI repo
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Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261
2021-08-22 23:56:07 -07:00
093f7fa3ca
SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name
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Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622
2020-08-06 01:14:06 -04:00
b4c6143a2f
Update copyright info
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Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba
2020-02-04 09:26:14 -08:00
20c7173849
Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master
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Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe
2020-01-30 20:12:13 -08:00
kjayapra-amd
Julia Jiang
Sourabh
Saleel Kudchadker
agunashe
Anusha Godavarthy Surya
Laurent Morichetti