Dispatch_ID,Kernel_Name,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,wave_size,obj,TCC_ATOMIC[0],TCC_CYCLE[0],TCC_EA_ATOMIC[0],TCC_EA_ATOMIC_LEVEL[0],TCC_ATOMIC[1],TCC_CYCLE[1],TCC_EA_ATOMIC[1],TCC_EA_ATOMIC_LEVEL[1],TCC_ATOMIC[2],TCC_CYCLE[2],TCC_EA_ATOMIC[2],TCC_EA_ATOMIC_LEVEL[2],TCC_ATOMIC[3],TCC_CYCLE[3],TCC_EA_ATOMIC[3],TCC_EA_ATOMIC_LEVEL[3],TCC_ATOMIC[4],TCC_CYCLE[4],TCC_EA_ATOMIC[4],TCC_EA_ATOMIC_LEVEL[4],TCC_ATOMIC[5],TCC_CYCLE[5],TCC_EA_ATOMIC[5],TCC_EA_ATOMIC_LEVEL[5],TCC_ATOMIC[6],TCC_CYCLE[6],TCC_EA_ATOMIC[6],TCC_EA_ATOMIC_LEVEL[6],TCC_ATOMIC[7],TCC_CYCLE[7],TCC_EA_ATOMIC[7],TCC_EA_ATOMIC_LEVEL[7],TCC_ATOMIC[8],TCC_CYCLE[8],TCC_EA_ATOMIC[8],TCC_EA_ATOMIC_LEVEL[8],TCC_ATOMIC[9],TCC_CYCLE[9],TCC_EA_ATOMIC[9],TCC_EA_ATOMIC_LEVEL[9],TCC_ATOMIC[10],TCC_CYCLE[10],TCC_EA_ATOMIC[10],TCC_EA_ATOMIC_LEVEL[10],TCC_ATOMIC[11],TCC_CYCLE[11],TCC_EA_ATOMIC[11],TCC_EA_ATOMIC_LEVEL[11],TCC_ATOMIC[12],TCC_CYCLE[12],TCC_EA_ATOMIC[12],TCC_EA_ATOMIC_LEVEL[12],TCC_ATOMIC[13],TCC_CYCLE[13],TCC_EA_ATOMIC[13],TCC_EA_ATOMIC_LEVEL[13],TCC_ATOMIC[14],TCC_CYCLE[14],TCC_EA_ATOMIC[14],TCC_EA_ATOMIC_LEVEL[14],TCC_ATOMIC[15],TCC_CYCLE[15],TCC_EA_ATOMIC[15],TCC_EA_ATOMIC_LEVEL[15],TCC_ATOMIC[16],TCC_CYCLE[16],TCC_EA_ATOMIC[16],TCC_EA_ATOMIC_LEVEL[16],TCC_ATOMIC[17],TCC_CYCLE[17],TCC_EA_ATOMIC[17],TCC_EA_ATOMIC_LEVEL[17],TCC_ATOMIC[18],TCC_CYCLE[18],TCC_EA_ATOMIC[18],TCC_EA_ATOMIC_LEVEL[18],TCC_ATOMIC[19],TCC_CYCLE[19],TCC_EA_ATOMIC[19],TCC_EA_ATOMIC_LEVEL[19],TCC_ATOMIC[20],TCC_CYCLE[20],TCC_EA_ATOMIC[20],TCC_EA_ATOMIC_LEVEL[20],TCC_ATOMIC[21],TCC_CYCLE[21],TCC_EA_ATOMIC[21],TCC_EA_ATOMIC_LEVEL[21],TCC_ATOMIC[22],TCC_CYCLE[22],TCC_EA_ATOMIC[22],TCC_EA_ATOMIC_LEVEL[22],TCC_ATOMIC[23],TCC_CYCLE[23],TCC_EA_ATOMIC[23],TCC_EA_ATOMIC_LEVEL[23],TCC_ATOMIC[24],TCC_CYCLE[24],TCC_EA_ATOMIC[24],TCC_EA_ATOMIC_LEVEL[24],TCC_ATOMIC[25],TCC_CYCLE[25],TCC_EA_ATOMIC[25],TCC_EA_ATOMIC_LEVEL[25],TCC_ATOMIC[26],TCC_CYCLE[26],TCC_EA_ATOMIC[26],TCC_EA_ATOMIC_LEVEL[26],TCC_ATOMIC[27],TCC_CYCLE[27],TCC_EA_ATOMIC[27],TCC_EA_ATOMIC_LEVEL[27],TCC_ATOMIC[28],TCC_CYCLE[28],TCC_EA_ATOMIC[28],TCC_EA_ATOMIC_LEVEL[28],TCC_ATOMIC[29],TCC_CYCLE[29],TCC_EA_ATOMIC[29],TCC_EA_ATOMIC_LEVEL[29],TCC_ATOMIC[30],TCC_CYCLE[30],TCC_EA_ATOMIC[30],TCC_EA_ATOMIC_LEVEL[30],TCC_ATOMIC[31],TCC_CYCLE[31],TCC_EA_ATOMIC[31],TCC_EA_ATOMIC_LEVEL[31],wave_size_1,obj_1,SQC_DCACHE_REQ_READ_1,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,wave_size_2,obj_2,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,GRBM_SPI_BUSY,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TD_SPI_STALL_sum,TD_LOAD_WAVEFRONT_sum,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TCC_NC_REQ_sum,TCC_UC_REQ_sum,TCC_CC_REQ_sum,TCC_RW_REQ_sum,wave_size_3,obj_3,TCC_EA_RDREQ_IO_CREDIT_STALL[0],TCC_EA_RDREQ_LEVEL[0],TCC_EA_WRREQ[0],TCC_EA_WRREQ_64B[0],TCC_EA_RDREQ_IO_CREDIT_STALL[1],TCC_EA_RDREQ_LEVEL[1],TCC_EA_WRREQ[1],TCC_EA_WRREQ_64B[1],TCC_EA_RDREQ_IO_CREDIT_STALL[2],TCC_EA_RDREQ_LEVEL[2],TCC_EA_WRREQ[2],TCC_EA_WRREQ_64B[2],TCC_EA_RDREQ_IO_CREDIT_STALL[3],TCC_EA_RDREQ_LEVEL[3],TCC_EA_WRREQ[3],TCC_EA_WRREQ_64B[3],TCC_EA_RDREQ_IO_CREDIT_STALL[4],TCC_EA_RDREQ_LEVEL[4],TCC_EA_WRREQ[4],TCC_EA_WRREQ_64B[4],TCC_EA_RDREQ_IO_CREDIT_STALL[5],TCC_EA_RDREQ_LEVEL[5],TCC_EA_WRREQ[5],TCC_EA_WRREQ_64B[5],TCC_EA_RDREQ_IO_CREDIT_STALL[6],TCC_EA_RDREQ_LEVEL[6],TCC_EA_WRREQ[6],TCC_EA_WRREQ_64B[6],TCC_EA_RDREQ_IO_CREDIT_STALL[7],TCC_EA_RDREQ_LEVEL[7],TCC_EA_WRREQ[7],TCC_EA_WRREQ_64B[7],TCC_EA_RDREQ_IO_CREDIT_STALL[8],TCC_EA_RDREQ_LEVEL[8],TCC_EA_WRREQ[8],TCC_EA_WRREQ_64B[8],TCC_EA_RDREQ_IO_CREDIT_STALL[9],TCC_EA_RDREQ_LEVEL[9],TCC_EA_WRREQ[9],TCC_EA_WRREQ_64B[9],TCC_EA_RDREQ_IO_CREDIT_STALL[10],TCC_EA_RDREQ_LEVEL[10],TCC_EA_WRREQ[10],TCC_EA_WRREQ_64B[10],TCC_EA_RDREQ_IO_CREDIT_STALL[11],TCC_EA_RDREQ_LEVEL[11],TCC_EA_WRREQ[11],TCC_EA_WRREQ_64B[11],TCC_EA_RDREQ_IO_CREDIT_STALL[12],TCC_EA_RDREQ_LEVEL[12],TCC_EA_WRREQ[12],TCC_EA_WRREQ_64B[12],TCC_EA_RDREQ_IO_CREDIT_STALL[13],TCC_EA_RDREQ_LEVEL[13],TCC_EA_WRREQ[13],TCC_EA_WRREQ_64B[13],TCC_EA_RDREQ_IO_CREDIT_STALL[14],TCC_EA_RDREQ_LEVEL[14],TCC_EA_WRREQ[14],TCC_EA_WRREQ_64B[14],TCC_EA_RDREQ_IO_CREDIT_STALL[15],TCC_EA_RDREQ_LEVEL[15],TCC_EA_WRREQ[15],TCC_EA_WRREQ_64B[15],TCC_EA_RDREQ_IO_CREDIT_STALL[16],TCC_EA_RDREQ_LEVEL[16],TCC_EA_WRREQ[16],TCC_EA_WRREQ_64B[16],TCC_EA_RDREQ_IO_CREDIT_STALL[17],TCC_EA_RDREQ_LEVEL[17],TCC_EA_WRREQ[17],TCC_EA_WRREQ_64B[17],TCC_EA_RDREQ_IO_CREDIT_STALL[18],TCC_EA_RDREQ_LEVEL[18],TCC_EA_WRREQ[18],TCC_EA_WRREQ_64B[18],TCC_EA_RDREQ_IO_CREDIT_STALL[19],TCC_EA_RDREQ_LEVEL[19],TCC_EA_WRREQ[19],TCC_EA_WRREQ_64B[19],TCC_EA_RDREQ_IO_CREDIT_STALL[20],TCC_EA_RDREQ_LEVEL[20],TCC_EA_WRREQ[20],TCC_EA_WRREQ_64B[20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REQ_LEVEL[31],wave_size_5,obj_5,TCC_EA_RDREQ[0],TCC_EA_RDREQ_32B[0],TCC_EA_RDREQ_DRAM_CREDIT_STALL[0],TCC_EA_RDREQ_GMI_CREDIT_STALL[0],TCC_EA_RDREQ[1],TCC_EA_RDREQ_32B[1],TCC_EA_RDREQ_DRAM_CREDIT_STALL[1],TCC_EA_RDREQ_GMI_CREDIT_STALL[1],TCC_EA_RDREQ[2],TCC_EA_RDREQ_32B[2],TCC_EA_RDREQ_DRAM_CREDIT_STALL[2],TCC_EA_RDREQ_GMI_CREDIT_STALL[2],TCC_EA_RDREQ[3],TCC_EA_RDREQ_32B[3],TCC_EA_RDREQ_DRAM_CREDIT_STALL[3],TCC_EA_RDREQ_GMI_CREDIT_STALL[3],TCC_EA_RDREQ[4],TCC_EA_RDREQ_32B[4],TCC_EA_RDREQ_DRAM_CREDIT_STALL[4],TCC_EA_RDREQ_GMI_CREDIT_STALL[4],TCC_EA_RDREQ[5],TCC_EA_RDREQ_32B[5],TCC_EA_RDREQ_DRAM_CREDIT_STALL[5],TCC_EA_RDREQ_GMI_CREDIT_STALL[5],TCC_EA_RDREQ[6],TCC_EA_RDREQ_32B[6],TCC_EA_RDREQ_DRAM_CREDIT_STALL[6],TCC_EA_RDREQ_GMI_CREDIT_STALL[6],TCC_EA_RDREQ[7],TCC_EA_RDREQ_32B[7],TCC_EA_RDREQ_DRAM_CREDIT_STALL[7],TCC_EA_RDREQ_GMI_CREDIT_STALL[7],TCC_EA_RDREQ[8],TCC_EA_RDREQ_32B[8],TCC_EA_RDREQ_DRAM_CREDIT_STALL[8],TCC_EA_RDREQ_GMI_CREDIT_STALL[8],TCC_EA_RDREQ[9],TCC_EA_RDREQ_32B[9],TCC_EA_RDREQ_DRAM_CREDIT_STALL[9],TCC_EA_RDREQ_GMI_CREDIT_STALL[9],TCC_EA_RDREQ[10],TCC_EA_RDREQ_32B[10],TCC_EA_RDREQ_DRAM_CREDIT_STALL[10],TCC_EA_RDREQ_GMI_CREDIT_STALL[10],TCC_EA_RDREQ[11],TCC_EA_RDREQ_32B[11],TCC_EA_RDREQ_DRAM_CREDIT_STALL[11],TCC_EA_RDREQ_GMI_CREDIT_STALL[11],TCC_EA_RDREQ[12],TCC_EA_RDREQ_32B[12],TCC_EA_RDREQ_DRAM_CREDIT_STALL[12],TCC_EA_RDREQ_GMI_CREDIT_STALL[12],TCC_EA_RDREQ[13],TCC_EA_RDREQ_32B[13],TCC_EA_RDREQ_DRAM_CREDIT_STALL[13],TCC_EA_RDREQ_GMI_CREDIT_STALL[13],TCC_EA_RDREQ[14],TCC_EA_RDREQ_32B[14],TCC_EA_RDREQ_DRAM_CREDIT_STALL[14],TCC_EA_RDREQ_GMI_CREDIT_STALL[14],TCC_EA_RDREQ[15],TCC_EA_RDREQ_32B[15],TCC_EA_RDREQ_DRAM_CREDIT_STALL[15],TCC_EA_RDREQ_GMI_CREDIT_STALL[15],TCC_EA_RDREQ[16],TCC_EA_RDREQ_32B[16],TCC_EA_RDREQ_DRAM_CREDIT_STALL[16],TCC_EA_RDREQ_GMI_CREDIT_STALL[16],TCC_EA_RDREQ[17],TCC_EA_RDREQ_32B[17],TCC_EA_RDREQ_DRAM_CREDIT_STALL[17],TCC_EA_RDREQ_GMI_CREDIT_STALL[17],TCC_EA_RDREQ[18],TCC_EA_RDREQ_32B[18],TCC_EA_RDREQ_DRAM_CREDIT_STALL[18],TCC_EA_RDREQ_GMI_CREDIT_STALL[18],TCC_EA_RDREQ[19],TCC_EA_RDREQ_32B[19],TCC_EA_RDREQ_DRAM_CREDIT_STALL[19],TCC_EA_RDREQ_GMI_CREDIT_STALL[19],TCC_EA_RDREQ[20],TCC_EA_RDREQ_32B[20],TCC_EA_RDREQ_DRAM_CREDIT_STALL[20],TCC_EA_RDREQ_GMI_CREDIT_STALL[20],TCC_EA_RDREQ[21],TCC_EA_RDREQ_32B[21],TCC_EA_RDREQ_DRAM_CREDIT_STALL[21],TCC_EA_RDREQ_GMI_CREDIT_STALL[21],TCC_EA_RDREQ[22],TCC_EA_RDREQ_32B[22],TCC_EA_RDREQ_DRAM_CREDIT_STALL[22],TCC_EA_RDREQ_GMI_CREDIT_STALL[22],TCC_EA_RDREQ[23],TCC_EA_RDREQ_32B[23],TCC_EA_RDREQ_DRAM_CREDIT_STALL[23],TCC_EA_RDREQ_GMI_CREDIT_STALL[23],TCC_EA_RDREQ[24],TCC_EA_RDREQ_32B[24],TCC_EA_RDREQ_DRAM_CREDIT_STALL[24],TCC_EA_RDREQ_GMI_CREDIT_STALL[24],TCC_EA_RDREQ[25],TCC_EA_RDREQ_32B[25],TCC_EA_RDREQ_DRAM_CREDIT_STALL[25],TCC_EA_RDREQ_GMI_CREDIT_STALL[25],TCC_EA_RDREQ[26],TCC_EA_RDREQ_32B[26],TCC_EA_RDREQ_DRAM_CREDIT_STALL[26],TCC_EA_RDREQ_GMI_CREDIT_STALL[26],TCC_EA_RDREQ[27],TCC_EA_RDREQ_32B[27],TCC_EA_RDREQ_DRAM_CREDIT_STALL[27],TCC_EA_RDREQ_GMI_CREDIT_STALL[27],TCC_EA_RDREQ[28],TCC_EA_RDREQ_32B[28],TCC_EA_RDREQ_DRAM_CREDIT_STALL[28],TCC_EA_RDREQ_GMI_CREDIT_STALL[28],TCC_EA_RDREQ[29],TCC_EA_RDREQ_32B[29],TCC_EA_RDREQ_DRAM_CREDIT_STALL[29],TCC_EA_RDREQ_GMI_CREDIT_STALL[29],TCC_EA_RDREQ[30],TCC_EA_RDREQ_32B[30],TCC_EA_RDREQ_DRAM_CREDIT_STALL[30],TCC_EA_RDREQ_GMI_CREDIT_STALL[30],TCC_EA_RDREQ[31],TCC_EA_RDREQ_32B[31],TCC_EA_RDREQ_DRAM_CREDIT_STALL[31],TCC_EA_RDREQ_GMI_CREDIT_STALL[31],wave_size_6,obj_6,SQ_THREAD_CYCLES_VALU,SQ_IFETCH,SQ_LDS_BANK_CONFLICT,SQ_LDS_ADDR_CONFLICT,SQ_LDS_UNALIGNED_STALL,SQ_WAVES_EQ_64,SQ_WAVES_LT_64,SQ_WAVES_LT_48,TCP_TCC_WRITE_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_NC_READ_REQ_sum,TA_FLAT_WAVEFRONTS_sum,TA_FLAT_READ_WAVEFRONTS_sum,SPI_RA_BAR_CU_FULL_CSN,SPI_RA_TGLIM_CU_FULL_CSN,TCC_EA_RDREQ_DRAM_sum,TCC_TAG_STALL_sum,TCC_NORMAL_WRITEBACK_sum,TCC_ALL_TC_OP_WB_WRITEBACK_sum,wave_size_7,obj_7,TCC_RW_REQ[0],TCC_TOO_MANY_EA_WRREQS_STALL[0],TCC_WRITE[0],TCC_RW_REQ[1],TCC_TOO_MANY_EA_WRREQS_STALL[1],TCC_WRITE[1],TCC_RW_REQ[2],TCC_TOO_MANY_EA_WRREQS_STALL[2],TCC_WRITE[2],TCC_RW_REQ[3],TCC_TOO_MANY_EA_WRREQS_STALL[3],TCC_WRITE[3],TCC_RW_REQ[4],TCC_TOO_MANY_EA_WRREQS_STALL[4],TCC_WRITE[4],TCC_RW_REQ[5],TCC_TOO_MANY_EA_WRREQS_STALL[5],TCC_WRITE[5],TCC_RW_REQ[6],TCC_TOO_MANY_EA_WRREQS_STALL[6],TCC_WRITE[6],TCC_RW_REQ[7],TCC_TOO_MANY_EA_WRREQS_STALL[7],TCC_WRITE[7],TCC_RW_REQ[8],TCC_TOO_MANY_EA_WRREQS_STALL[8],TCC_WRITE[8],TCC_RW_REQ[9],TCC_TOO_MANY_EA_WRREQS_STALL[9],TCC_WRITE[9],TCC_RW_REQ[10],TCC_TOO_MANY_EA_WRREQS_STALL[10],TCC_WRITE[10],TCC_RW_REQ[11],TCC_TOO_MANY_EA_WRREQS_STALL[11],TCC_WRITE[11],TCC_RW_REQ[12],TCC_TOO_MANY_EA_WRREQS_STALL[12],TCC_WRITE[12],TCC_RW_REQ[13],TCC_TOO_MANY_EA_WRREQS_STALL[13],TCC_WRITE[13],TCC_RW_REQ[14],TCC_TOO_MANY_EA_WRREQS_STALL[14],TCC_WRITE[14],TCC_RW_REQ[15],TCC_TOO_MANY_EA_WRREQS_STALL[15],TCC_WRITE[15],TCC_RW_REQ[16],TCC_TOO_MANY_EA_WRREQS_STALL[16],TCC_WRITE[16],TCC_RW_REQ[17],TCC_TOO_MANY_EA_WRREQS_STALL[17],TCC_WRITE[17],TCC_RW_REQ[18],TCC_TOO_MANY_EA_WRREQS_STALL[18],TCC_WRITE[18],TCC_RW_REQ[19],TCC_TOO_MANY_EA_WRREQS_STALL[19],TCC_WRITE[19],TCC_RW_REQ[20],TCC_TOO_MANY_EA_WRREQS_STALL[20],TCC_WRITE[20],TCC_RW_REQ[21],TCC_TOO_MANY_EA_WRREQS_STALL[21],TCC_WRITE[21],TCC_RW_REQ[22],TCC_TOO_MANY_EA_WRREQS_STALL[22],TCC_WRITE[22],TCC_RW_REQ[23],TCC_TOO_MANY_EA_WRREQS_STALL[23],TCC_WRITE[23],TCC_RW_REQ[24],TCC_TOO_MANY_EA_WRREQS_STALL[24],TCC_WRITE[24],TCC_RW_REQ[25],TCC_TOO_MANY_EA_WRREQS_STALL[25],TCC_WRITE[25],TCC_RW_REQ[26],TCC_TOO_MANY_EA_WRREQS_STALL[26],TCC_WRITE[26],TCC_RW_REQ[27],TCC_TOO_MANY_EA_WRREQS_STALL[27],TCC_WRITE[27],TCC_RW_REQ[28],TCC_TOO_MANY_EA_WRREQS_STALL[28],TCC_WRITE[28],TCC_RW_REQ[29],TCC_TOO_MANY_EA_WRREQS_STALL[29],TCC_WRITE[29],TCC_RW_REQ[30],TCC_TOO_MANY_EA_WRREQS_STALL[30],TCC_WRITE[30],TCC_RW_REQ[31],TCC_TOO_MANY_EA_WRREQS_STALL[31],TCC_WRITE[31],wave_size_8,obj_8,SQ_WAVE_CYCLES,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_BUSY_CU_CYCLES,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,TCP_UTCL1_TRANSLATION_MISS_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TCC_EA_WRREQ_sum,TCC_EA_WRREQ_64B_sum,TCC_EA_WR_UNCACHED_32B_sum,TCC_EA_WRREQ_DRAM_sum,wave_size_9,obj_9,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,TCP_TCP_LATENCY_sum,TCP_TCC_READ_REQ_LATENCY_sum,TCP_TCC_WRITE_REQ_LATENCY_sum,TCP_TCC_READ_REQ_sum,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TCC_EA_WRREQ_STALL_sum,TCC_EA_RDREQ_sum,TCC_EA_RDREQ_32B_sum,TCC_EA_RD_UNCACHED_32B_sum,wave_size_10,obj_10,SQ_INSTS_VALU_INT64,SQ_INSTS_SMEM,SQ_INSTS_FLAT,SQ_INSTS_LDS,SQ_INSTS_GDS,SQ_INSTS_EXP_GDS,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TA_BUFFER_COALESCED_READ_CYCLES_sum,TA_BUFFER_COALESCED_WRITE_CYCLES_sum,TD_COALESCABLE_WAVEFRONT_sum,SPI_RA_RES_STALL_CSN,SPI_RA_TMP_STALL_CSN,CPC_CPC_UTCL2IU_BUSY,CPC_CPC_UTCL2IU_IDLE,CPF_CMP_UTCL1_STALL_ON_TRANSLATION,TCC_READ_sum,TCC_WRITE_sum,TCC_ATOMIC_sum,TCC_WRITEBACK_sum,wave_size_11,obj_11,TCC_HIT[0],TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_HIT[1],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_HIT[2],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_HIT[3],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_HIT[4],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_HIT[5],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_HIT[6],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_HIT[7],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_HIT[8],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_HIT[9],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_HIT[10],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_HIT[11],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_HIT[12],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_HIT[13],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_HIT[14],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_HIT[15],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_HIT[16],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_HIT[17],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_HIT[18],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_HIT[19],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_HIT[20],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_HIT[21],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_HIT[22],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_HIT[23],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_HIT[24],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_HIT[25],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_HIT[26],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_HIT[27],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_HIT[28],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_HIT[29],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_HIT[30],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_HIT[31],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],wave_size_12,obj_12,SQ_INSTS_FLAT_LDS_ONLY,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_PENDING_STALL_CYCLES_sum,wave_size_13,obj_13,SQC_ICACHE_MISSES_DUPLICATE,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,wave_size_14,obj_14,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_CC_ATOMIC_REQ_sum,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_EA_RDREQ_LEVEL_sum,TCC_EA_WRREQ_LEVEL_sum,TCC_EA_ATOMIC_LEVEL_sum,wave_size_15,obj_15,SQC_TC_DATA_WRITE_REQ,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,wave_size_16,obj_16,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SQ_INSTS_VALU_TRANS_F64,SQ_INSTS_VALU_INT32,TCP_VOLATILE_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCC_HIT_sum,TCC_MISS_sum,wave_size_17,obj_17,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_WAVES,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,SQ_INSTS_VMEM,SQ_INSTS_SALU,GRBM_COUNT,GRBM_GUI_ACTIVE,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TD_TCP_STALL_CYCLES_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TA_TA_BUSY_sum,TA_BUFFER_WAVEFRONTS_sum,TD_TD_BUSY_sum,TD_TC_STALL_sum,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TCC_CYCLE_sum,TCC_BUSY_sum,TCC_PROBE_sum,TCC_PROBE_ALL_sum,wave_size_18,obj_18,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,TCP_TCC_NC_WRITE_REQ_sum,TCP_TCC_NC_ATOMIC_REQ_sum,TCP_TCC_UC_READ_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TA_FLAT_ATOMIC_WAVEFRONTS_sum,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TCC_NORMAL_EVICT_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCC_EA_ATOMIC_sum,Start_Timestamp,End_Timestamp
0,"vecCopy(double*, double*, double*, int, int) [clone .kd]",2,1048576,256,0,0,8,0,16,64,0x7f4bd8140ec0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,0,27668,0,0,64,0x7f97f7c10ec0,32768,32768,0,64,0x7f58ffa54ec0,0,393216,163840,0,0,0,0,0,18971,0.0,0.0,0.0,32768.0,0.0,0.0,431.0,32768.0,4096,16384,352,29771,2125,0,56.0,6.0,0.0,204356.0,64,0x7f220701cec0,0,1154155,4096,4096,0,1132805,4096,4096,0,1374037,4096,4096,0,1573411,4096,4096,0,1125987,4096,4096,0,1176838,4096,4096,0,1208180,4096,4096,0,1563190,4096,4096,0,1224180,4096,4096,0,1065353,4096,4096,0,1007185,4096,4096,0,1366501,4096,4096,0,1100892,4096,4096,0,1173735,4096,4096,0,1368405,4096,4096,0,1328813,4096,4096,0,1495001,4096,4096,0,1283146,4096,4096,0,906555,4096,4096,0,1514084,4096,4096,0,1348338,4096,4096,0,1321985,4096,4096,0,1121583,4096,4096,0,1085979,4096,4096,0,1066518,4096,4096,0,1228405,4096,4096,0,1233098,4096,4096,0,1170189,4096,4096,0,1516520,4096,4096,0,1359551,4096,4096,0,1475981,4096,4096,0,1154325,4096,4096,64,0x7f6a698d8ec0,0,0,0,1040438,0,0,0,1127061,0,0,0,978940,0,0,0,1090488,0,0,0,1131301,0,0,0,1024733,0,0,0,989481,0,0,0,1078230,0,0,0,1044065,0,0,0,1003526,0,0,0,1036308,0,0,0,1037243,0,0,0,998788,98,0,0,1168561,4,0,0,1099902,0,0,0,1082115,10,0,0,1073014,0,0,0,1009868,0,0,0,1023589,0,0,0,1091845,0,0,0,1123462,0,0,0,1043279,0,0,0,980717,0,0,0,1040034,0,0,0,1015125,52,0,0,1073443,0,0,0,1061215,0,0,0,1074910,0,0,0,1076438,0,0,0,1170878,0,0,0,964103,0,0,0,1148042,64,0x7fc38ef9cec0,4096,0,0,0,4096,0,103,0,4096,0,0,0,4096,0,36,0,4096,0,0,0,4097,0,27,0,4096,0,0,0,4096,0,129,0,4096,0,0,0,4096,0,0,0,4096,0,45,0,4096,0,70,0,4096,0,89,0,4096,0,0,0,4096,0,26,0,4096,0,26,0,4096,0,87,0,4097,0,144,0,4096,0,23,0,4096,0,102,0,4096,0,233,0,4096,0,75,0,4100,0,6,0,4099,0,12,0,4096,0,267,0,4096,0,0,0,4096,0,180,0,4096,0,37,0,4096,0,355,0,4096,0,258,0,4096,0,37,0,4096,0,35,0,64,0x7f854fa90ec0,10485760,65536,0,0,0,16384,0,0,131072.0,0.0,0.0,0.0,32768.0,16384.0,0,0,131081.0,34388.0,46134.0,19402.0,64,0x7ffbc1ce8ec0,6380,0,4096,6338,0,4096,6338,0,4096,6379,0,4096,6368,0,4096,6359,0,4096,6350,0,4096,6380,0,4096,6379,0,4096,6378,0,4096,6343,0,4096,6340,0,4096,6379,0,4096,6370,0,4096,6357,0,4096,6354,0,4096,6360,0,4096,6406,0,4096,6417,0,4096,6380,0,4096,6382,0,4096,6421,0,4096,6372,0,4096,6594,0,4096,6425,0,4096,6358,0,4096,6406,0,4096,6424,0,4096,6379,0,4096,6379,0,4096,6419,0,4096,6376,0,4096,64,0x7fcfde730ec0,11288895,10008133,936698,344064,1702714,0,0,163840,832.0,515136.0,0.0,524288.0,327469.0,32768.0,532008,0,0,10924,131072.0,131072.0,0.0,131072.0,64,0x7f8db66f8ec0,114688,0,32768,32768,16384,16384,65536,49152,28282487.0,86353827.0,39916573.0,131072.0,0.0,226559.0,0,0,15840,329.0,131080.0,0.0,8.0,64,0x7f438ca68ec0,0,65536,32768,0,0,0,16384,16384,0.0,0.0,0.0,524288.0,0.0,0.0,0.0,11380,0,814,28639,0,73392.0,131072.0,0.0,65568.0,64,0x7f1d22978ec0,2268,4096,2268,6364,2261,4096,2261,6357,2279,4096,2279,6375,2256,4096,2256,6352,2233,4097,2234,6330,2269,4096,2269,6365,2258,4096,2258,6354,2329,4096,2329,6425,2332,4096,2332,6428,2265,4096,2265,6361,2260,4096,2260,6356,2278,4096,2278,6374,2256,4096,2256,6352,2232,4096,2232,6328,2270,4100,2274,6370,2316,4097,2317,6413,2257,4096,2257,6353,2303,4096,2303,6399,2256,4097,2257,6353,2284,4096,2284,6380,2273,4096,2273,6369,2316,4096,2316,6412,2268,4096,2268,6364,2390,4098,2392,6488,2227,4096,2227,6323,2260,4097,2261,6357,2306,4096,2306,6402,2259,4096,2259,6355,2285,4096,2285,6381,2274,4096,2274,6370,2315,4096,2315,6411,2275,4096,2275,6371,64,0x7f4241794ec0,0,0,0,0,0,0,168,56,131072.0,131072.0,0.0,955258.0,64,0x7f4243eb4ec0,1212,116311,0,0,65536,63800,56,1680,64,0x7f49646a0ec0,131072,0,0,0,0,0,0,0,0.0,0.0,0.0,0.0,16384,0,41690584.0,36097819.0,0.0,64,0x7f06d4278ec0,0,0,0,224,0,65536,64187,56,64,0x7f1380294ec0,0,0,0,0,0,0,0,114688,2097152.0,2097152.0,1048576.0,1048576.0,0.0,0.0,0.0,16384.0,13321,18984,8100,545,0,27099,204116.0,0.0,73037.0,131079.0,64,0x7f4060cbcec0,227200,127301,16384,0,16384,16384,32768,49152,28399,28399,1932520.0,1342467.0,3677.0,156725.0,1047685.0,0.0,1334488.0,1037061.0,225489,135416,28399,0,28399,0,908768.0,487455.0,0.0,0.0,64,0x7f6eaebd8ec0,0,0,1048576,0,0,0,0,0,0.0,0.0,0.0,0.0,16384.0,0.0,0,32768,65551.0,0.0,0.0,0.0,1411987252061945,1411987252082105