Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA0_WRREQ_64B[45],TCC_EA0_WRREQ_LEVEL[45],TCC_HIT[45],TCC_EA0_WRREQ[46],TCC_EA0_WRREQ_64B[46],TCC_EA0_WRREQ_LEVEL[46],TCC_HIT[46],TCC_EA0_WRREQ[47],TCC_EA0_WRREQ_64B[47],TCC_EA0_WRREQ_LEVEL[47],TCC_HIT[47],TCC_EA0_WRREQ[48],TCC_EA0_WRREQ_64B[48],TCC_EA0_WRREQ_LEVEL[48],TCC_HIT[48],TCC_EA0_WRREQ[49],TCC_EA0_WRREQ_64B[49],TCC_EA0_WRREQ_LEVEL[49],TCC_HIT[49],TCC_EA0_WRREQ[50],TCC_EA0_WRREQ_64B[50],TCC_EA0_WRREQ_LEVEL[50],TCC_HIT[50],TCC_EA0_WRREQ[51],TCC_EA0_WRREQ_64B[51],TCC_EA0_WRREQ_LEVEL[51],TCC_HIT[51],TCC_EA0_WRREQ[52],TCC_EA0_WRREQ_64B[52],TCC_EA0_WRREQ_LEVEL[52],TCC_HIT[52],TCC_EA0_WRREQ[53],TCC_EA0_WRREQ_64B[53],TCC_EA0_WRREQ_LEVEL[53],TCC_HIT[53],TCC_EA0_WRREQ[54],TCC_EA0_WRREQ_64B[54],TCC_EA0_WRREQ_LEVEL[54],TCC_HIT[54],TCC_EA0_WRREQ[55],TCC_EA0_WRREQ_64B[55],TCC_EA0_WRREQ_LEVEL[55],TCC_HIT[55],TCC_EA0_WRREQ[56],TCC_EA0_WRREQ_64B[56],TCC_EA0_WRREQ_LEVEL[56],TCC_HIT[56],TCC_EA0_WRREQ[57]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ED_WRITE_CYCLES_sum,TCC_ATOMIC_sum,TCC_READ_sum,TCC_WRITEBACK_sum,TCC_WRITE_sum,TCP_TOTAL_ATOMIC_WITHOUT_RET_sum,TCP_TOTAL_ATOMIC_WITH_RET_sum,TCP_TOTAL_CACHE_ACCESSES_sum,TCP_TOTAL_WRITEBACK_INVALIDATES_sum,TD_COALESCABLE_WAVEFRONT_sum,Wave_Size_5,Correlation_ID_5,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA0_ATOMIC_sum,TCC_NORMAL_EVICT_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,Wave_Size_6,Correlation_ID_6,XCC_Index_6,TCC_MISS[0],TCC_READ[0],TCC_REQ[0],TCC_RW_REQ[0],TCC_MISS[1],TCC_READ[1],TCC_REQ[1],TCC_RW_REQ[1],TCC_MISS[2],TCC_READ[2],TCC_REQ[2],TCC_RW_REQ[2],TCC_MISS[3],TCC_READ[3],TCC_REQ[3],TCC_RW_REQ[3],TCC_MISS[4],TCC_READ[4],TCC_REQ[4],TCC_RW_REQ[4],TCC_MISS[5],TCC_READ[5],TCC_REQ[5],TCC_RW_REQ[5],TCC_MISS[6],TCC_READ[6],TCC_REQ[6],TCC_RW_REQ[6],TCC_MISS[7],TCC_READ[7],TCC_REQ[7],TCC_RW_REQ[7],TCC_MISS[8],TCC_READ[8],TCC_REQ[8],TCC_RW_REQ[8],TCC_MISS[9],TCC_READ[9],TCC_REQ[9],TCC_RW_REQ[9],TCC_MISS[10],TCC_READ[10],TCC_REQ[10],TCC_RW_REQ[10],TCC_MISS[11],TCC_READ[11],TCC_REQ[11],TCC_RW_REQ[11],TCC_MISS[12],TCC_READ[12],TCC_REQ[12],TCC_RW_REQ[12],TCC_MISS[13],TCC_READ[13],TCC_REQ[13],TCC_RW_REQ[13],TCC_MISS[14],TCC_READ[14],TCC_REQ[14],TCC_RW_REQ[14],TCC_MISS[15],TCC_READ[15],TCC_REQ[15],TCC_RW_REQ[15],TCC_MISS[16],TCC_READ[16],TCC_REQ[16],TCC_RW_REQ[16],TCC_MISS[17],TCC_READ[17],TCC_REQ[17],TCC_RW_REQ[17],TCC_MISS[18],TCC_READ[18],TCC_REQ[18],TCC_RW_REQ[18],TCC_MISS[19],TCC_READ[19],TCC_REQ[19],TCC_RW_REQ[19],TCC_MISS[20],TCC_READ[20],TCC_REQ[20],TCC_RW_REQ[20],TCC_MISS[21],TCC_READ[21],TCC_REQ[21],TCC_RW_REQ[21],TCC_MISS[22],TCC_READ[22],TCC_REQ[22],TCC_RW_REQ[22],TCC_MISS[23],TCC_READ[23],TCC_REQ[23],TCC_RW_REQ[23],TCC_MISS[24],TCC_READ[24],TCC_REQ[24],TCC_RW_REQ[24],TCC_MISS[25],TCC_READ[25],TCC_REQ[25],TCC_RW_REQ[25],TCC_MISS[26],TCC_READ[26],TCC_REQ[26],TCC_RW_REQ[26],TCC_MISS[27],TCC_READ[27],TCC_REQ[27],TCC_RW_REQ[27],TCC_MISS[28],TCC_READ[28],TCC_REQ[28],TCC_RW_REQ[28],TCC_MISS[29],TCC_READ[29],TCC_REQ[29],TCC_RW_REQ[29],TCC_MISS[30],TCC_READ[30],TCC_REQ[30],TCC_RW_REQ[30],TCC_MISS[31],TCC_READ[31],TCC_REQ[31],TCC_RW_REQ[31],TCC_MISS[32],TCC_READ[32],TCC_REQ[32],TCC_RW_REQ[32],TCC_MISS[33],TCC_READ[33],TCC_REQ[33],TCC_RW_REQ[33],TCC_MISS[34],TCC_READ[34],TCC_REQ[34],TCC_RW_REQ[34],TCC_MISS[35],TCC_READ[35],TCC_REQ[35],TCC_RW_REQ[35],TCC_MISS[36],TCC_READ[36],TCC_REQ[36],TCC_RW_REQ[36],TCC_MISS[37],TCC_READ[37],TCC_REQ[37],TCC_RW_REQ[37],TCC_MISS[38],TCC_READ[38],TCC_REQ[38],TCC_RW_REQ[38],TCC_MISS[39],TCC_READ[39],TCC_REQ[39],TCC_RW_REQ[39],TCC_MISS[40],TCC_READ[40],TCC_REQ[40],TCC_RW_REQ[40],TCC_MISS[41],TCC_READ[41],TCC_REQ[41],TCC_RW_REQ[41],TCC_MISS[42],TCC_READ[42],TCC_REQ[42],TCC_RW_REQ[42],TCC_MISS[43],TCC_READ[43],TCC_REQ[43],TCC_RW_REQ[43],TCC_MISS[44],TCC_READ[44],TCC_REQ[44],TCC_RW_REQ[44],TCC_MISS[45],TCC_READ[45],TCC_REQ[45],TCC_RW_REQ[45],TCC_MISS[46],TCC_READ[46],TCC_REQ[46],TCC_RW_REQ[46],TCC_MISS[47],TCC_READ[47],TCC_REQ[47],TCC_RW_REQ[47],TCC_MISS[48],TCC_READ[48],TCC_REQ[48],TCC_RW_REQ[48],TCC_MISS[49],TCC_READ[49],TCC_REQ[49],TCC_RW_REQ[49],TCC_MISS[50],TCC_READ[50],TCC_REQ[50],TCC_RW_REQ[50],TCC_MISS[51],TCC_READ[51],TCC_REQ[51],TCC_RW_REQ[51],TCC_MISS[52],TCC_READ[52],TCC_REQ[52],TCC_RW_REQ[52],TCC_MISS[53],TCC_READ[53],TCC_REQ[53],TCC_RW_REQ[53],TCC_MISS[54],TCC_READ[54],TCC_REQ[54],TCC_RW_REQ[54],TCC_MISS[55],TCC_READ[55],TCC_REQ[55],TCC_RW_REQ[55],TCC_MISS[56],TCC_READ[56],TCC_REQ[56],TCC_RW_REQ[56],TCC_MISS[57],TCC_READ[57],TCC_REQ[57],TCC_RW_REQ[57],TCC_MISS[58],TCC_READ[58],TCC_REQ[58],TCC_RW_REQ[58],TCC_MISS[59],TCC_READ[59],TCC_REQ[59],TCC_RW_REQ[59],TCC_MISS[60],TCC_READ[60],TCC_REQ[60],TCC_RW_REQ[60],TCC_MISS[61],TCC_READ[61],TCC_REQ[61],TCC_RW_REQ[61],TCC_MISS[62],TCC_READ[62],TCC_REQ[62],TCC_RW_REQ[62],TCC_MISS[63],TCC_READ[63],TCC_REQ[63],TCC_RW_REQ[63],TCC_MISS[64],TCC_READ[64],TCC_REQ[64],TCC_RW_REQ[64],TCC_MISS[65],TCC_READ[65],TCC_REQ[65],TCC_RW_REQ[65],TCC_MISS[66],TCC_READ[66],TCC_REQ[66],TCC_RW_REQ[66],TCC_MISS[67],TCC_READ[67],TCC_REQ[67],TCC_RW_REQ[67],TCC_MISS[68],TCC_READ[68],TCC_REQ[68],TCC_RW_REQ[68],TCC_MISS[69],TCC_READ[69],TCC_REQ[69],TCC_RW_REQ[69],TCC_MISS[70],TCC_READ[70],TCC_REQ[70],TCC_RW_REQ[70],TCC_MISS[71],TCC_READ[71],TCC_REQ[71],TCC_RW_REQ[71],TCC_MISS[72],TCC_READ[72],TCC_REQ[72],TCC_RW_REQ[72],TCC_MISS[73],TCC_READ[73],TCC_REQ[73],TCC_RW_REQ[73],TCC_MISS[74],TCC_READ[74],TCC_REQ[74],TCC_RW_REQ[74],TCC_MISS[75],TCC_READ[75],TCC_REQ[75],TCC_RW_REQ[75],TCC_MISS[76],TCC_READ[76],TCC_REQ[76],TCC_RW_REQ[76],TCC_MISS[77],TCC_READ[77],TCC_REQ[77],TCC_RW_REQ[77],TCC_MISS[78],TCC_READ[78],TCC_REQ[78],TCC_RW_REQ[78],TCC_MISS[79],TCC_READ[79],TCC_REQ[79],TCC_RW_REQ[79],TCC_MISS[80],TCC_READ[80],TCC_REQ[80],TCC_RW_REQ[80],TCC_MISS[81],TCC_READ[81],TCC_REQ[81],TCC_RW_REQ[81],TCC_MISS[82],TCC_READ[82],TCC_REQ[82],TCC_RW_REQ[82],TCC_MISS[83],TCC_READ[83],TCC_REQ[83],TCC_RW_REQ[83],TCC_MISS[84],TCC_READ[84],TCC_REQ[84],TCC_RW_REQ[84],TCC_MISS[85],TCC_READ[85],TCC_REQ[85],TCC_RW_REQ[85],TCC_MISS[86],TCC_READ[86],TCC_REQ[86],TCC_RW_REQ[86],TCC_MISS[87],TCC_READ[87],TCC_REQ[87],TCC_RW_REQ[87],TCC_MISS[88],TCC_READ[88],TCC_REQ[88],TCC_RW_REQ[88],TCC_MISS[89],TCC_READ[89],TCC_REQ[89],TCC_RW_REQ[89],TCC_MISS[90],TCC_READ[90],TCC_REQ[90],TCC_RW_REQ[90],TCC_MISS[91],TCC_READ[91],TCC_REQ[91],TCC_RW_REQ[91],TCC_MISS[92],TCC_READ[92],TCC_REQ[92],TCC_RW_REQ[92],TCC_MISS[93],TCC_READ[93],TCC_REQ[93],TCC_RW_REQ[93],TCC_MISS[94],TCC_READ[94],TCC_REQ[94],TCC_RW_REQ[94],TCC_MISS[95],TCC_READ[95],TCC_REQ[95],TCC_RW_REQ[95],Wave_Size_7,Correlation_ID_7,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_VOLATILE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,Wave_Size_8,Correlation_ID_8,XCC_Index_8,TCC_ATOMIC[0],TCC_BUBBLE[0],TCC_CYCLE[0],TCC_EA0_ATOMIC[0],TCC_ATOMIC[1],TCC_BUBBLE[1],TCC_CYCLE[1],TCC_EA0_ATOMIC[1],TCC_ATOMIC[2],TCC_BUBBLE[2],TCC_CYCLE[2],TCC_EA0_ATOMIC[2],TCC_ATOMIC[3],TCC_BUBBLE[3],TCC_CYCLE[3],TCC_EA0_ATOMIC[3],TCC_ATOMIC[4],TCC_BUBBLE[4],TCC_CYCLE[4],TCC_EA0_ATOMIC[4],TCC_ATOMIC[5],TCC_BUBBLE[5],TCC_CYCLE[5],TCC_EA0_ATOMIC[5],TCC_ATOMIC[6],TCC_BUBBLE[6],TCC_CYCLE[6],TCC_EA0_ATOMIC[6],TCC_ATOMIC[7],TCC_BUBBLE[7],TCC_CYCLE[7],TCC_EA0_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[8],TCC_CYCLE[8],TCC_EA0_ATOMIC[8],TCC_ATOMIC[9],TCC_BUBBLE[9],TCC_CYCLE[9],TCC_EA0_ATOMIC[9],TCC_ATOMIC[10],TCC_BUBBLE[10],TCC_CYCLE[10],TCC_EA0_ATOMIC[10],TCC_ATOMIC[11],TCC_BUBBLE[11],TCC_CYCLE[11],TCC_EA0_ATOMIC[11],TCC_ATOMIC[12],TCC_BUBBLE[12],TCC_CYCLE[12],TCC_EA0_ATOMIC[12],TCC_ATOMIC[13],TCC_BUBBLE[13],TCC_CYCLE[13],TCC_EA0_ATOMIC[13],TCC_ATOMIC[14],TCC_BUBBLE[14],TCC_CYCLE[14],TCC_EA0_ATOMIC[14],TCC_ATOMIC[15],TCC_BUBBLE[15],TCC_CYCLE[15],TCC_EA0_ATOMIC[15],TCC_ATOMIC[16],TCC_BUBBLE[16],TCC_CYCLE[16],TCC_EA0_ATOMIC[16],TCC_ATOMIC[17],TCC_BUBBLE[17],TCC_CYCLE[17],TCC_EA0_ATOMIC[17],TCC_ATOMIC[18],TCC_BUBBLE[18],TCC_CYCLE[18],TCC_EA0_ATOMIC[18],TCC_ATOMIC[19],TCC_BUBBLE[19],TCC_CYCLE[19],TCC_EA0_ATOMIC[19],TCC_ATOMIC[20],TCC_BUBBLE[20],TCC_CYCLE[20],TCC_EA0_ATOMIC[20],TCC_ATOMIC[21],TCC_BUBBLE[21],TCC_CYCLE[21],TCC_EA0_ATOMIC[21],TCC_ATOMIC[22],TCC_BUBBLE[22],TCC_CYCLE[22],TCC_EA0_ATOMIC[22],TCC_ATOMIC[23],TCC_BUBBLE[23],TCC_CYCLE[23],TCC_EA0_ATOMIC[23],TCC_ATOMIC[24],TCC_BUBBLE[24],TCC_CYCLE[24],TCC_EA0_ATOMIC[24],TCC_ATOMIC[25],TCC_BUBBLE[25],TCC_CYCLE[25],TCC_EA0_ATOMIC[25],TCC_ATOMIC[26],TCC_BUBBLE[26],TCC_CYCLE[26],TCC_EA0_ATOMIC[26],TCC_ATOMIC[27],TCC_BUBBLE[27],TCC_CYCLE[27],TCC_EA0_ATOMIC[27],TCC_ATOMIC[28],TCC_BUBBLE[28],TCC_CYCLE[28],TCC_EA0_ATOMIC[28],TCC_ATOMIC[29],TCC_BUBBLE[29],TCC_CYCLE[29],TCC_EA0_ATOMIC[29],TCC_ATOMIC[30],TCC_BUBBLE[30],TCC_CYCLE[30],TCC_EA0_ATOMIC[30],TCC_ATOMIC[31],TCC_BUBBLE[31],TCC_CYCLE[31],TCC_EA0_ATOMIC[31],TCC_ATOMIC[32],TCC_BUBBLE[32],TCC_CYCLE[32],TCC_EA0_ATOMIC[32],TCC_ATOMIC[33],TCC_BUBBLE[33],TCC_CYCLE[33],TCC_EA0_ATOMIC[33],TCC_ATOMIC[34],TCC_BUBBLE[34],TCC_CYCLE[34],TCC_EA0_ATOMIC[34],TCC_ATOMIC[35],TCC_BUBBLE[35],TCC_CYCLE[35],TCC_EA0_ATOMIC[35],TCC_ATOMIC[36],TCC_BUBBLE[36],TCC_CYCLE[36],TCC_EA0_ATOMIC[36],TCC_ATOMIC[37],TCC_BUBBLE[37],TCC_CYCLE[37],TCC_EA0_ATOMIC[37],TCC_ATOMIC[38],TCC_BUBBLE[38],TCC_CYCLE[38],TCC_EA0_ATOMIC[38],TCC_ATOMIC[39],TCC_BUBBLE[39],TCC_CYCLE[39],TCC_EA0_ATOMIC[39],TCC_ATOMIC[40],TCC_BUBBLE[40],TCC_CYCLE[40],TCC_EA0_ATOMIC[40],TCC_ATOMIC[41],TCC_BUBBLE[41],TCC_CYCLE[41],TCC_EA0_ATOMIC[41],TCC_ATOMIC[42],TCC_BUBBLE[42],TCC_CYCLE[42],TCC_EA0_ATOMIC[42],TCC_ATOMIC[43],TCC_BUBBLE[43],TCC_CYCLE[43],TCC_EA0_ATOMIC[43],TCC_ATOMIC[44],TCC_BUBBLE[44],TCC_CYCLE[44],TCC_EA0_ATOMIC[44],TCC_ATOMIC[45],TCC_BUBBLE[45],TCC_CYCLE[45],TCC_EA0_ATOMIC[45],TCC_ATOMIC[46],TCC_BUBBLE[46],TCC_CYCLE[46],TCC_EA0_ATOMIC[46],TCC_ATOMIC[47],TCC_BUBBLE[47],TCC_CYCLE[47],TCC_EA0_ATOMIC[47],TCC_ATOMIC[48],TCC_BUBBLE[48],TCC_CYCLE[48],TCC_EA0_ATOMIC[48],TCC_ATOMIC[49],TCC_BUBBLE[49],TCC_CYCLE[49],TCC_EA0_ATOMIC[49],TCC_ATOMIC[50],TCC_BUBBLE[50],TCC_CYCLE[50],TCC_EA0_ATOMIC[50],TCC_ATOMIC[51],TCC_BUBBLE[51],TCC_CYCLE[51],TCC_EA0_ATOMIC[51],TCC_ATOMIC[52],TCC_BUBBLE[52],TCC_CYCLE[52],TCC_EA0_ATOMIC[52],TCC_ATOMIC[53],TCC_BUBBLE[53],TCC_CYCLE[53],TCC_EA0_ATOMIC[53],TCC_ATOMIC[54],TCC_BUBBLE[54],TCC_CYCLE[54],TCC_EA0_ATOMIC[54],TCC_ATOMIC[55],TCC_BUBBLE[55],TCC_CYCLE[55],TCC_EA0_ATOMIC[55],TCC_ATOMIC[56],TCC_BUBBLE[56],TCC_CYCLE[56],TCC_EA0_ATOMIC[56],TCC_ATOMIC[57],TCC_BUBBLE[57],TCC_CYCLE[57],TCC_EA0_ATOMIC[57],TCC_ATOMIC[58],TCC_BUBBLE[58],TCC_CYCLE[58],TCC_EA0_ATOMIC[58],TCC_ATOMIC[59],TCC_BUBBLE[59],TCC_CYCLE[59],TCC_EA0_ATOMIC[59],TCC_ATOMIC[60],TCC_BUBBLE[60],TCC_CYCLE[60],TCC_EA0_ATOMIC[60],TCC_ATOMIC[61],TCC_BUBBLE[61],TCC_CYCLE[61],TCC_EA0_ATOMIC[61],TCC_ATOMIC[62],TCC_BUBBLE[62],TCC_CYCLE[62],TCC_EA0_ATOMIC[62],TCC_ATOMIC[63],TCC_BUBBLE[63],TCC_CYCLE[63],TCC_EA0_ATOMIC[63],TCC_ATOMIC[64],TCC_BUBBLE[64],TCC_CYCLE[64],TCC_EA0_ATOMIC[64],TCC_ATOMIC[65],TCC_BUBBLE[65],TCC_CYCLE[65],TCC_EA0_ATOMIC[65],TCC_ATOMIC[66],TCC_BUBBLE[66],TCC_CYCLE[66],TCC_EA0_ATOMIC[66],TCC_ATOMIC[67],TCC_BUBBLE[67],TCC_CYCLE[67],TCC_EA0_ATOMIC[67],TCC_ATOMIC[68],TCC_BUBBLE[68],TCC_CYCLE[68],TCC_EA0_ATOMIC[68],TCC_ATOMIC[69],TCC_BUBBLE[69],TCC_CYCLE[69],TCC_EA0_ATOMIC[69],TCC_ATOMIC[70],TCC_BUBBLE[70],TCC_CYCLE[70],TCC_EA0_ATOMIC[70],TCC_ATOMIC[71],TCC_BUBBLE[71],TCC_CYCLE[71],TCC_EA0_ATOMIC[71],TCC_ATOMIC[72],TCC_BUBBLE[72],TCC_CYCLE[72],TCC_EA0_ATOMIC[72],TCC_ATOMIC[73],TCC_BUBBLE[73],TCC_CYCLE[73],TCC_EA0_ATOMIC[73],TCC_ATOMIC[74],TCC_BUBBLE[74],TCC_CYCLE[74],TCC_EA0_ATOMIC[74],TCC_ATOMIC[75],TCC_BUBBLE[75],TCC_CYCLE[75],TCC_EA0_ATOMIC[75],TCC_ATOMIC[76],TCC_BUBBLE[76],TCC_CYCLE[76],TCC_EA0_ATOMIC[76],TCC_ATOMIC[77],TCC_BUBBLE[77],TCC_CYCLE[77],TCC_EA0_ATOMIC[77],TCC_ATOMIC[78],TCC_BUBBLE[78],TCC_CYCLE[78],TCC_EA0_ATOMIC[78],TCC_ATOMIC[79],TCC_BUBBLE[79],TCC_CYCLE[79],TCC_EA0_ATOMIC[79],TCC_ATOMIC[80],TCC_BUBBLE[80],TCC_CYCLE[80],TCC_EA0_ATOMIC[80],TCC_ATOMIC[81],TCC_BUBBLE[81],TCC_CYCLE[81],TCC_EA0_ATOMIC[81],TCC_ATOMIC[82],TCC_BUBBLE[82],TCC_CYCLE[82],TCC_EA0_ATOMIC[82],TCC_ATOMIC[83],TCC_BUBBLE[83],TCC_CYCLE[83],TCC_EA0_ATOMIC[83],TCC_ATOMIC[84],TCC_BUBBLE[84],TCC_CYCLE[84],TCC_EA0_ATOMIC[84],TCC_ATOMIC[85],TCC_BUBBLE[85],TCC_CYCLE[85],TCC_EA0_ATOMIC[85],TCC_ATOMIC[86],TCC_BUBBLE[86],TCC_CYCLE[86],TCC_EA0_ATOMIC[86],TCC_ATOMIC[87],TCC_BUBBLE[87],TCC_CYCLE[87],TCC_EA0_ATOMIC[87],TCC_ATOMIC[88],TCC_BUBBLE[88],TCC_CYCLE[88],TCC_EA0_ATOMIC[88],TCC_ATOMIC[89],TCC_BUBBLE[89],TCC_CYCLE[89],TCC_EA0_ATOMIC[89],TCC_ATOMIC[90],TCC_BUBBLE[90],TCC_CYCLE[90],TCC_EA0_ATOMIC[90],TCC_ATOMIC[91],TCC_BUBBLE[91],TCC_CYCLE[91],TCC_EA0_ATOMIC[91],TCC_ATOMIC[92],TCC_BUBBLE[92],TCC_CYCLE[92],TCC_EA0_ATOMIC[92],TCC_ATOMIC[93],TCC_BUBBLE[93],TCC_CYCLE[93],TCC_EA0_ATOMIC[93],TCC_ATOMIC[94],TCC_BUBBLE[94],TCC_CYCLE[94],TCC_EA0_ATOMIC[94],TCC_ATOMIC[95],TCC_BUBBLE[95],TCC_CYCLE[95],TCC_EA0_ATOMIC[95],Wave_Size_9,Correlation_ID_9,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,Wave_Size_10,Correlation_ID_10,SQC_TC_DATA_ATOMIC_REQ,SQC_TC_STALL,SQC_TC_REQ,SQC_DCACHE_REQ_READ_16,SQC_ICACHE_REQ,SQC_ICACHE_HITS,SQC_ICACHE_MISSES,SQC_ICACHE_MISSES_DUPLICATE,Wave_Size_11,Correlation_ID_11,SQ_INSTS_VALU_MFMA_MOPS_I8,SQ_INSTS_VALU_MFMA_MOPS_F16,SQ_INSTS_VALU_MFMA_MOPS_BF16,SQ_INSTS_VALU_MFMA_MOPS_F32,SQ_INSTS_VALU_MFMA_MOPS_F64,SQC_TC_INST_REQ,SQC_TC_DATA_READ_REQ,SQC_TC_DATA_WRITE_REQ,TCP_PENDING_STALL_CYCLES_sum,Wave_Size_12,Correlation_ID_12,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_EA0_ATOMIC_LEVEL_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_EA0_WRREQ_STALL_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,Wave_Size_13,Correlation_ID_13,SQC_DCACHE_REQ_READ_2,SQC_DCACHE_REQ_READ_4,Wave_Size_14,Correlation_ID_14,SQ_ACTIVE_INST_SCA,SQ_ACTIVE_INST_EXP_GDS,SQ_ACTIVE_INST_MISC,SQ_ACTIVE_INST_FLAT,SQ_INST_CYCLES_VMEM_WR,SQ_INST_CYCLES_VMEM_RD,SQ_INST_CYCLES_SMEM,SQ_INST_CYCLES_SALU,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_BUBBLE_sum,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,Wave_Size_15,Correlation_ID_15,XCC_Index_15,TCC_EA0_ATOMIC_LEVEL[0],TCC_EA0_RDREQ[0],TCC_EA0_RDREQ_32B[0],TCC_EA0_RDREQ_LEVEL[0],TCC_EA0_ATOMIC_LEVEL[1],TCC_EA0_RDREQ[1],TCC_EA0_RDREQ_32B[1],TCC_EA0_RDREQ_LEVEL[1],TCC_EA0_ATOMIC_LEVEL[2],TCC_EA0_RDREQ[2],TCC_EA0_RDREQ_32B[2],TCC_EA0_RDREQ_LEVEL[2],TCC_EA0_ATOMIC_LEVEL[3],TCC_EA0_RDREQ[3],TCC_EA0_RDREQ_32B[3],TCC_EA0_RDREQ_LEVEL[3],TCC_EA0_ATOMIC_LEVEL[4],TCC_EA0_RDREQ[4],TCC_EA0_RDREQ_32B[4],TCC_EA0_RDREQ_LEVEL[4],TCC_EA0_ATOMIC_LEVEL[5],TCC_EA0_RDREQ[5],TCC_EA0_RDREQ_32B[5],TCC_EA0_RDREQ_LEVEL[5],TCC_EA0_ATOMIC_LEVEL[6],TCC_EA0_RDREQ[6],TCC_EA0_RDREQ_32B[6],TCC_EA0_RDREQ_LEVEL[6],TCC_EA0_ATOMIC_LEVEL[7],TCC_EA0_RDREQ[7],TCC_EA0_RDREQ_32B[7],TCC_EA0_RDREQ_LEVEL[7],TCC_EA0_ATOMIC_LEVEL[8],TCC_EA0_RDREQ[8],TCC_EA0_RDREQ_32B[8],TCC_EA0_RDREQ_LEVEL[8],TCC_EA0_ATOMIC_LEVEL[9],TCC_EA0_RDREQ[9],TCC_EA0_RDREQ_32B[9],TCC_EA0_RDREQ_LEVEL[9],TCC_EA0_ATOMIC_LEVEL[10],TCC_EA0_RDREQ[10],TCC_EA0_RDREQ_32B[10],TCC_EA0_RDREQ_LEVEL[10],TCC_EA0_ATOMIC_LEVEL[11],TCC_EA0_RDREQ[11],TCC_EA0_RDREQ_32B[11],TCC_EA0_RDREQ_LEVEL[11],TCC_EA0_ATOMIC_LEVEL[12],TCC_EA0_RDREQ[12],TCC_EA0_RDREQ_32B[12],TCC_EA0_RDREQ_LEVEL[12],TCC_EA0_ATOMIC_LEVEL[13],TCC_EA0_RDREQ[13],TCC_EA0_RDREQ_32B[13],TCC_EA0_RDREQ_LEVEL[13],TCC_EA0_ATOMIC_LEVEL[14],TCC_EA0_RDREQ[14],TCC_EA0_RDREQ_32B[14],TCC_EA0_RDREQ_LEVEL[14],TCC_EA0_ATOMIC_LEVEL[15],TCC_EA0_RDREQ[15],TCC_EA0_RDREQ_32B[15],TCC_EA0_RDREQ_LEVEL[15],TCC_EA0_ATOMIC_LEVEL[16],TCC_EA0_RDREQ[16],TCC_EA0_RDREQ_32B[16],TCC_EA0_RDREQ_LEVEL[16],TCC_EA0_ATOMIC_LEVEL[17],TCC_EA0_RDREQ[17],TCC_EA0_RDREQ_32B[17],TCC_EA0_RDREQ_LEVEL[17],TCC_EA0_ATOMIC_LEVEL[18],TCC_EA0_RDREQ[18],TCC_EA0_RDREQ_32B[18],TCC_EA0_RDREQ_LEVEL[18],TCC_EA0_ATOMIC_LEVEL[19],TCC_EA0_RDREQ[19],TCC_EA0_RDREQ_32B[19],TCC_EA0_RDREQ_LEVEL[19],TCC_EA0_ATOMIC_LEVEL[20],TCC_EA0_RDREQ[20],TCC_EA0_RDREQ_32B[20],TCC_EA0_RDREQ_LEVEL[20],TCC_EA0_ATOMIC_LEVEL[21],TCC_EA0_RDREQ[21],TCC_EA0_RDREQ_32B[21],TCC_EA0_RDREQ_LEVEL[21],TCC_EA0_ATOMIC_LEVEL[22],TCC_EA0_RDREQ[22],TCC_EA0_RDREQ_32B[22],TCC_EA0_RDREQ_LEVEL[22],TCC_EA0_ATOMIC_LEVEL[23],TCC_EA0_RDREQ[23],TCC_EA0_RDREQ_32B[23],TCC_EA0_RDREQ_LEVEL[23],TCC_EA0_ATOMIC_LEVEL[24],TCC_EA0_RDREQ[24],TCC_EA0_RDREQ_32B[24],TCC_EA0_RDREQ_LEVEL[24],TCC_EA0_ATOMIC_LEVEL[25],TCC_EA0_RDREQ[25],TCC_EA0_RDREQ_32B[25],TCC_EA0_RDREQ_LEVEL[25],TCC_EA0_ATOMIC_LEVEL[26],TCC_EA0_RDREQ[26],TCC_EA0_RDREQ_32B[26],TCC_EA0_RDREQ_LEVEL[26],TCC_EA0_ATOMIC_LEVEL[27],TCC_EA0_RDREQ[27],TCC_EA0_RDREQ_32B[27],TCC_EA0_RDREQ_LEVEL[27],TCC_EA0_ATOMIC_LEVEL[28],TCC_EA0_RDREQ[28],TCC_EA0_RDREQ_32B[28],TCC_EA0_RDREQ_LEVEL[28],TCC_EA0_ATOMIC_LEVEL[29],TCC_EA0_RDREQ[29],TCC_EA0_RDREQ_32B[29],TCC_EA0_RDREQ_LEVEL[29],TCC_EA0_ATOMIC_LEVEL[30],TCC_EA0_RDREQ[30],TCC_EA0_RDREQ_32B[30],TCC_EA0_RDREQ_LEVEL[30],TCC_EA0_ATOMIC_LEVEL[31],TCC_EA0_RDREQ[31],TCC_EA0_RDREQ_32B[31],TCC_EA0_RDREQ_LEVEL[31],TCC_EA0_ATOMIC_LEVEL[32],TCC_EA0_RDREQ[32],TCC_EA0_RDREQ_32B[32],TCC_EA0_RDREQ_LEVEL[32],TCC_EA0_ATOMIC_LEVEL[33],TCC_EA0_RDREQ[33],TCC_EA0_RDREQ_32B[33],TCC_EA0_RDREQ_LEVEL[33],TCC_EA0_ATOMIC_LEVEL[34],TCC_EA0_RDREQ[34],TCC_EA0_RDREQ_32B[34],TCC_EA0_RDREQ_LEVEL[34],TCC_EA0_ATOMIC_LEVEL[35],TCC_EA0_RDREQ[35],TCC_EA0_RDREQ_32B[35],TCC_EA0_RDREQ_LEVEL[35],TCC_EA0_ATOMIC_LEVEL[36],TCC_EA0_RDREQ[36],TCC_EA0_RDREQ_32B[36],TCC_EA0_RDREQ_LEVEL[36],TCC_EA0_ATOMIC_LEVEL[37],TCC_EA0_RDREQ[37],TCC_EA0_RDREQ_32B[37],TCC_EA0_RDREQ_LEVEL[37],TCC_EA0_ATOMIC_LEVEL[38],TCC_EA0_RDREQ[38],TCC_EA0_RDREQ_32B[38],TCC_EA0_RDREQ_LEVEL[38],TCC_EA0_ATOMIC_LEVEL[39],TCC_EA0_RDREQ[39],TCC_EA0_RDREQ_32B[39],TCC_EA0_RDREQ_LEVEL[39],TCC_EA0_ATOMIC_LEVEL[40],TCC_EA0_RDREQ[40],TCC_EA0_RDREQ_32B[40],TCC_EA0_RDREQ_LEVEL[40],TCC_EA0_ATOMIC_LEVEL[41],TCC_EA0_RDREQ[41],TCC_EA0_RDREQ_32B[41],TCC_EA0_RDREQ_LEVEL[41],TCC_EA0_ATOMIC_LEVEL[42],TCC_EA0_RDREQ[42],TCC_EA0_RDREQ_32B[42],TCC_EA0_RDREQ_LEVEL[42],TCC_EA0_ATOMIC_LEVEL[43],TCC_EA0_RDREQ[43],TCC_EA0_RDREQ_32B[43],TCC_EA0_RDREQ_LEVEL[43],TCC_EA0_ATOMIC_LEVEL[44],TCC_EA0_RDREQ[44],TCC_EA0_RDREQ_32B[44],TCC_EA0_RDREQ_LEVEL[44],TCC_EA0_ATOMIC_LEVEL[45],TCC_EA0_RDREQ[45],TCC_EA0_RDREQ_32B[45],TCC_EA0_RDREQ_LEVEL[45],TCC_EA0_ATOMIC_LEVEL[46],TCC_EA0_RDREQ[46],TCC_EA0_RDREQ_32B[46],TCC_EA0_RDREQ_LEVEL[46],TCC_EA0_ATOMIC_LEVEL[47],TCC_EA0_RDREQ[47],TCC_EA0_RDREQ_32B[47],TCC_EA0_RDREQ_LEVEL[47],TCC_EA0_ATOMIC_LEVEL[48],TCC_EA0_RDREQ[48],TCC_EA0_RDREQ_32B[48],TCC_EA0_RDREQ_LEVEL[48],TCC_EA0_ATOMIC_LEVEL[49],TCC_EA0_RDREQ[49],TCC_EA0_RDREQ_32B[49],TCC_EA0_RDREQ_LEVEL[49],TCC_EA0_ATOMIC_LEVEL[50],TCC_EA0_RDREQ[50],TCC_EA0_RDREQ_32B[50],TCC_EA0_RDREQ_LEVEL[50],TCC_EA0_ATOMIC_LEVEL[51],TCC_EA0_RDREQ[51],TCC_EA0_RDREQ_32B[51],TCC_EA0_RDREQ_LEVEL[51],TCC_EA0_ATOMIC_LEVEL[52],TCC_EA0_RDREQ[52],TCC_EA0_RDREQ_32B[52],TCC_EA0_RDREQ_LEVEL[52],TCC_EA0_ATOMIC_LEVEL[53],TCC_EA0_RDREQ[53],TCC_EA0_RDREQ_32B[53],TCC_EA0_RDREQ_LEVEL[53],TCC_EA0_ATOMIC_LEVEL[54],TCC_EA0_RDREQ[54],TCC_EA0_RDREQ_32B[54],TCC_EA0_RDREQ_LEVEL[54],TCC_EA0_ATOMIC_LEVEL[55],TCC_EA0_RDREQ[55],TCC_EA0_RDREQ_32B[55],TCC_EA0_RDREQ_LEVEL[55],TCC_EA0_ATOMIC_LEVEL[56],TCC_EA0_RDREQ[56],TCC_EA0_RDREQ_32B[56],TCC_EA0_RDREQ_LEVEL[56],TCC_EA0_ATOMIC_LEVEL[57],TCC_EA0_RDREQ[57],TCC_EA0_RDREQ_32B[57],TCC_EA0_RDREQ_LEVEL[57],TCC_EA0_ATOMIC_LEVEL[58],TCC_EA0_RDREQ[58],TCC_EA0_RDREQ_32B[58],TCC_EA0_RDREQ_LEVEL[58],TCC_EA0_ATOMIC_LEVEL[59],TCC_EA0_RDREQ[59],TCC_EA0_RDREQ_32B[59],TCC_EA0_RDREQ_LEVEL[59],TCC_EA0_ATOMIC_LEVEL[60],TCC_EA0_RDREQ[60],TCC_EA0_RDREQ_32B[60],TCC_EA0_RDREQ_LEVEL[60],TCC_EA0_ATOMIC_LEVEL[61],TCC_EA0_RDREQ[61],TCC_EA0_RDREQ_32B[61],TCC_EA0_RDREQ_LEVEL[61],TCC_EA0_ATOMIC_LEVEL[62],TCC_EA0_RDREQ[62],TCC_EA0_RDREQ_32B[62],TCC_EA0_RDREQ_LEVEL[62],TCC_EA0_ATOMIC_LEVEL[63],TCC_EA0_RDREQ[63],TCC_EA0_RDREQ_32B[63],TCC_EA0_RDREQ_LEVEL[63],TCC_EA0_ATOMIC_LEVEL[64],TCC_EA0_RDREQ[64],TCC_EA0_RDREQ_32B[64],TCC_EA0_RDREQ_LEVEL[64],TCC_EA0_ATOMIC_LEVEL[65],TCC_EA0_RDREQ[65],TCC_EA0_RDREQ_32B[65],TCC_EA0_RDREQ_LEVEL[65],TCC_EA0_ATOMIC_LEVEL[66],TCC_EA0_RDREQ[66],TCC_EA0_RDREQ_32B[66],TCC_EA0_RDREQ_LEVEL[66],TCC_EA0_ATOMIC_LEVEL[67],TCC_EA0_RDREQ[67],TCC_EA0_RDREQ_32B[67],TCC_EA0_RDREQ_LEVEL[67],TCC_EA0_ATOMIC_LEVEL[68],TCC_EA0_RDREQ[68],TCC_EA0_RDREQ_32B[68],TCC_EA0_RDREQ_LEVEL[68],TCC_EA0_ATOMIC_LEVEL[69],TCC_EA0_RDREQ[69],TCC_EA0_RDREQ_32B[69],TCC_EA0_RDREQ_LEVEL[69],TCC_EA0_ATOMIC_LEVEL[70],TCC_EA0_RDREQ[70],TCC_EA0_RDREQ_32B[70],TCC_EA0_RDREQ_LEVEL[70],TCC_EA0_ATOMIC_LEVEL[71],TCC_EA0_RDREQ[71],TCC_EA0_RDREQ_32B[71],TCC_EA0_RDREQ_LEVEL[71],TCC_EA0_ATOMIC_LEVEL[72],TCC_EA0_RDREQ[72],TCC_EA0_RDREQ_32B[72],TCC_EA0_RDREQ_LEVEL[72],TCC_EA0_ATOMIC_LEVEL[73],TCC_EA0_RDREQ[73],TCC_EA0_RDREQ_32B[73],TCC_EA0_RDREQ_LEVEL[73],TCC_EA0_ATOMIC_LEVEL[74],TCC_EA0_RDREQ[74],TCC_EA0_RDREQ_32B[74],TCC_EA0_RDREQ_LEVEL[74],TCC_EA0_ATOMIC_LEVEL[75],TCC_EA0_RDREQ[75],TCC_EA0_RDREQ_32B[75],TCC_EA0_RDREQ_LEVEL[75],TCC_EA0_ATOMIC_LEVEL[76],TCC_EA0_RDREQ[76],TCC_EA0_RDREQ_32B[76],TCC_EA0_RDREQ_LEVEL[76],TCC_EA0_ATOMIC_LEVEL[77],TCC_EA0_RDREQ[77],TCC_EA0_RDREQ_32B[77],TCC_EA0_RDREQ_LEVEL[77],TCC_EA0_ATOMIC_LEVEL[78],TCC_EA0_RDREQ[78],TCC_EA0_RDREQ_32B[78],TCC_EA0_RDREQ_LEVEL[78],TCC_EA0_ATOMIC_LEVEL[79],TCC_EA0_RDREQ[79],TCC_EA0_RDREQ_32B[79],TCC_EA0_RDREQ_LEVEL[79],TCC_EA0_ATOMIC_LEVEL[80],TCC_EA0_RDREQ[80],TCC_EA0_RDREQ_32B[80],TCC_EA0_RDREQ_LEVEL[80],TCC_EA0_ATOMIC_LEVEL[81],TCC_EA0_RDREQ[81],TCC_EA0_RDREQ_32B[81],TCC_EA0_RDREQ_LEVEL[81],TCC_EA0_ATOMIC_LEVEL[82],TCC_EA0_RDREQ[82],TCC_EA0_RDREQ_32B[82],TCC_EA0_RDREQ_LEVEL[82],TCC_EA0_ATOMIC_LEVEL[83],TCC_EA0_RDREQ[83],TCC_EA0_RDREQ_32B[83],TCC_EA0_RDREQ_LEVEL[83],TCC_EA0_ATOMIC_LEVEL[84],TCC_EA0_RDREQ[84],TCC_EA0_RDREQ_32B[84],TCC_EA0_RDREQ_LEVEL[84],TCC_EA0_ATOMIC_LEVEL[85],TCC_EA0_RDREQ[85],TCC_EA0_RDREQ_32B[85],TCC_EA0_RDREQ_LEVEL[85],TCC_EA0_ATOMIC_LEVEL[86],TCC_EA0_RDREQ[86],TCC_EA0_RDREQ_32B[86],TCC_EA0_RDREQ_LEVEL[86],TCC_EA0_ATOMIC_LEVEL[87],TCC_EA0_RDREQ[87],TCC_EA0_RDREQ_32B[87],TCC_EA0_RDREQ_LEVEL[87],TCC_EA0_ATOMIC_LEVEL[88],TCC_EA0_RDREQ[88],TCC_EA0_RDREQ_32B[88],TCC_EA0_RDREQ_LEVEL[88],TCC_EA0_ATOMIC_LEVEL[89],TCC_EA0_RDREQ[89],TCC_EA0_RDREQ_32B[89],TCC_EA0_RDREQ_LEVEL[89],TCC_EA0_ATOMIC_LEVEL[90],TCC_EA0_RDREQ[90],TCC_EA0_RDREQ_32B[90],TCC_EA0_RDREQ_LEVEL[90],TCC_EA0_ATOMIC_LEVEL[91],TCC_EA0_RDREQ[91],TCC_EA0_RDREQ_32B[91],TCC_EA0_RDREQ_LEVEL[91],TCC_EA0_ATOMIC_LEVEL[92],TCC_EA0_RDREQ[92],TCC_EA0_RDREQ_32B[92],TCC_EA0_RDREQ_LEVEL[92],TCC_EA0_ATOMIC_LEVEL[93],TCC_EA0_RDREQ[93],TCC_EA0_RDREQ_32B[93],TCC_EA0_RDREQ_LEVEL[93],TCC_EA0_ATOMIC_LEVEL[94],TCC_EA0_RDREQ[94],TCC_EA0_RDREQ_32B[94],TCC_EA0_RDREQ_LEVEL[94],TCC_EA0_ATOMIC_LEVEL[95],TCC_EA0_RDREQ[95],TCC_EA0_RDREQ_32B[95],TCC_EA0_RDREQ_LEVEL[95],Wave_Size_16,Correlation_ID_16,SQ_INSTS_VMEM,SQ_INSTS_SALU,SQ_INSTS_VSKIPPED,SQ_INSTS,SQ_INSTS_VALU,SQ_INSTS_VALU_ADD_F16,SQ_INSTS_VALU_MUL_F16,SQ_INSTS_VALU_FMA_F16,GRBM_SPI_BUSY,SPI_CSN_NUM_THREADGROUPS,SPI_CSN_WAVE,CPC_CPC_TCIU_BUSY,CPC_CPC_TCIU_IDLE,CPF_CPF_TCIU_BUSY,CPF_CPF_TCIU_STALL,TA_BUFFER_READ_WAVEFRONTS_sum,TA_BUFFER_WRITE_WAVEFRONTS_sum,TCC_CC_REQ_sum,TCC_NC_REQ_sum,TCC_RW_REQ_sum,TCC_UC_REQ_sum,TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum,TCP_READ_TAGCONFLICT_STALL_CYCLES_sum,TCP_TA_TCP_STATE_READ_sum,TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum,TD_LOAD_WAVEFRONT_sum,TD_SPI_STALL_sum,Wave_Size_17,Correlation_ID_17,SQ_CYCLES,SQ_BUSY_CYCLES,SQ_BUSY_CU_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_INSTS_VALU_CVT,SQ_INSTS_VMEM_WR,SQ_INSTS_VMEM_RD,GRBM_COUNT,GRBM_GUI_ACTIVE,SPI_CSN_WINDOW_VALID,SPI_CSN_BUSY,CPC_CPC_STAT_BUSY,CPC_CPC_STAT_IDLE,CPF_CPF_STAT_BUSY,CPF_CPF_STAT_STALL,TA_BUFFER_WAVEFRONTS_sum,TA_TA_BUSY_sum,TCC_BUSY_sum,TCC_CYCLE_sum,TCC_PROBE_ALL_sum,TCC_PROBE_sum,TCP_GATE_EN1_sum,TCP_GATE_EN2_sum,TCP_TCR_TCP_STALL_CYCLES_sum,TCP_TD_TCP_STALL_CYCLES_sum,TD_TC_STALL_sum,TD_TD_BUSY_sum,Start_Timestamp,End_Timestamp
0,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) 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