Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_ATOMIC[0],TCC_BUBBLE[0],TCC_CYCLE[0],TCC_EA0_ATOMIC[0],TCC_ATOMIC[1],TCC_BUBBLE[1],TCC_CYCLE[1],TCC_EA0_ATOMIC[1],TCC_ATOMIC[2],TCC_BUBBLE[2],TCC_CYCLE[2],TCC_EA0_ATOMIC[2],TCC_ATOMIC[3],TCC_BUBBLE[3],TCC_CYCLE[3],TCC_EA0_ATOMIC[3],TCC_ATOMIC[4],TCC_BUBBLE[4],TCC_CYCLE[4],TCC_EA0_ATOMIC[4],TCC_ATOMIC[5],TCC_BUBBLE[5],TCC_CYCLE[5],TCC_EA0_ATOMIC[5],TCC_ATOMIC[6],TCC_BUBBLE[6],TCC_CYCLE[6],TCC_EA0_ATOMIC[6],TCC_ATOMIC[7],TCC_BUBBLE[7],TCC_CYCLE[7],TCC_EA0_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[8],TCC_CYCLE[8],TCC_EA0_ATOMIC[8],TCC_ATOMIC[9],TCC_BUBBLE[9],TCC_CYCLE[9],TCC_EA0_ATOMIC[9],TCC_ATOMIC[10],TCC_BUBBLE[10],TCC_CYCLE[10],TCC_EA0_ATOMIC[10],TCC_ATOMIC[11],TCC_BUBBLE[11],TCC_CYCLE[11],TCC_EA0_ATOMIC[11],TCC_ATOMIC[12],TCC_BUBBLE[12],TCC_CYCLE[12],TCC_EA0_ATOMIC[12],TCC_ATOMIC[13],TCC_BUBBLE[13],TCC_CYCLE[13],TCC_EA0_ATOMIC[13],TCC_ATOMIC[14],TCC_BUBBLE[14],TCC_CYCLE[14],TCC_EA0_ATOMIC[14],TCC_ATOMIC[15],TCC_BUBBLE[15],TCC_CYCLE[15],TCC_EA0_ATOMIC[15],TCC_ATOMIC[16],TCC_BUBBLE[16],TCC_CYCLE[16],TCC_EA0_ATOMIC[16],TCC_ATOMIC[17],TCC_BUBBLE[17],TCC_CYCLE[17],TCC_EA0_ATOMIC[17],TCC_ATOMIC[18],TCC_BUBBLE[18],TCC_CYCLE[18],TCC_EA0_ATOMIC[18],TCC_ATOMIC[19],TCC_BUBBLE[19],TCC_CYCLE[19],TCC_EA0_ATOMIC[19],TCC_ATOMIC[20],TCC_BUBBLE[20],TCC_CYCLE[20],TCC_EA0_ATOMIC[20],TCC_ATOMIC[21],TCC_BUBBLE[21],TCC_CYCLE[21],TCC_EA0_ATOMIC[21],TCC_ATOMIC[22],TCC_BUBBLE[22],TCC_CYCLE[22],TCC_EA0_ATOMIC[22],TCC_ATOMIC[23],TCC_BUBBLE[23],TCC_CYCLE[23],TCC_EA0_ATOMIC[23],TCC_ATOMIC[24],TCC_BUBBLE[24],TCC_CYCLE[24],TCC_EA0_ATOMIC[24],TCC_ATOMIC[25],TCC_BUBBLE[25],TCC_CYCLE[25],TCC_EA0_ATOMIC[25],TCC_ATOMIC[26],TCC_BUBBLE[26],TCC_CYCLE[26],TCC_EA0_ATOMIC[26],TCC_ATOMIC[27],TCC_BUBBLE[27],TCC_CYCLE[27],TCC_EA0_ATOMIC[27],TCC_ATOMIC[28],TCC_BUBBLE[28],TCC_CYCLE[28],TCC_EA0_ATOMIC[28],TCC_ATOMIC[29],TCC_BUBBLE[29],TCC_CYCLE[29],TCC_EA0_ATOMIC[29],TCC_ATOMIC[30],TCC_BUBBLE[30],TCC_CYCLE[30],TCC_EA0_ATOMIC[30],TCC_ATOMIC[31],TCC_BUBBLE[31],TCC_CYCLE[31],TCC_EA0_ATOMIC[31],TCC_ATOMIC[32],TCC_BUBBLE[32],TCC_CYCLE[32],TCC_EA0_ATOMIC[32],TCC_ATOMIC[33],TCC_BUBBLE[33],TCC_CYCLE[33],TCC_EA0_ATOMIC[33],TCC_ATOMIC[34],TCC_BUBBLE[34],TCC_CYCLE[34],TCC_EA0_ATOMIC[34],TCC_ATOMIC[35],TCC_BUBBLE[35],TCC_CYCLE[35],TCC_EA0_ATOMIC[35],TCC_ATOMIC[36],TCC_BUBBLE[36],TCC_CYCLE[36],TCC_EA0_ATOMIC[36],TCC_ATOMIC[37],TCC_BUBBLE[37],TCC_CYCLE[37],TCC_EA0_ATOMIC[37],TCC_ATOMIC[38],TCC_BUBBLE[38],TCC_CYCLE[38],TCC_EA0_ATOMIC[38],TCC_ATOMIC[39],TCC_BUBBLE[39],TCC_CYCLE[39],TCC_EA0_ATOMIC[39],TCC_ATOMIC[40],TCC_BUBBLE[40],TCC_CYCLE[40],TCC_EA0_ATOMIC[40],TCC_ATOMIC[41],TCC_BUBBLE[41],TCC_CYCLE[41],TCC_EA0_ATOMIC[41],TCC_ATOMIC[42],TCC_BUBBLE[42],TCC_CYCLE[42],TCC_EA0_ATOMIC[42],TCC_ATOMIC[43],TCC_BUBBLE[43],TCC_CYCLE[43],TCC_EA0_ATOMIC[43],TCC_ATOMIC[44],TCC_BUBBLE[44],TCC_CYCLE[44],TCC_EA0_ATOMIC[44],TCC_ATOMIC[45],TCC_BUBBLE[45],TCC_CYCLE[45],TCC_EA0_ATOMIC[45],TCC_ATOMIC[46],TCC_BUBBLE[46],TCC_CYCLE[46],TCC_EA0_ATOMIC[46],TCC_ATOMIC[47],TCC_BUBBLE[47],TCC_CYCLE[47],TCC_EA0_ATOMIC[47],TCC_ATOMIC[48],TCC_BUBBLE[48],TCC_CYCLE[48],TCC_EA0_ATOMIC[48],TCC_ATOMIC[49],TCC_BUBBLE[49],TCC_CYCLE[49],TCC_EA0_ATOMIC[49],TCC_ATOMIC[50],TCC_BUBBLE[50],TCC_CYCLE[50],TCC_EA0_ATOMIC[50],TCC_ATOMIC[51],TCC_BUBBLE[51],TCC_CYCLE[51],TCC_EA0_ATOMIC[51],TCC_ATOMIC[52],TCC_BUBBLE[52],TCC_CYCLE[52],TCC_EA0_ATOMIC[52],TCC_ATOMIC[53],TCC_BUBBLE[53],TCC_CYCLE[53],TCC_EA0_ATOMIC[53],TCC_ATOMIC[54],TCC_BUBBLE[54],TCC_CYCLE[54],TCC_EA0_ATOMIC[54],TCC_ATOMIC[55],TCC_BUBBLE[55],TCC_CYCLE[55],TCC_EA0_ATOMIC[55],TCC_ATOMIC[56],TCC_BUBBLE[56],TCC_CYCLE[56],TCC_EA0_ATOMIC[56],TCC_ATOMIC[57],TCC_BUBBLE[57],TCC_CYCLE[57],TCC_EA0_ATOMIC[57],TCC_ATOMIC[58],TCC_BUBBLE[58],TCC_CYCLE[58],TCC_EA0_ATOMIC[58],TCC_ATOMIC[59],TCC_BUBBLE[59],TCC_CYCLE[59],TCC_EA0_ATOMIC[59],TCC_ATOMIC[60],TCC_BUBBLE[60],TCC_CYCLE[60],TCC_EA0_ATOMIC[60],TCC_ATOMIC[61],TCC_BUBBLE[61],TCC_CYCLE[61],TCC_EA0_ATOMIC[61],TCC_ATOMIC[62],TCC_BUBBLE[62],TCC_CYCLE[62],TCC_EA0_ATOMIC[62],TCC_ATOMIC[63],TCC_BUBBLE[63],TCC_CYCLE[63],TCC_EA0_ATOMIC[63],TCC_ATOMIC[64],TCC_BUBBLE[64],TCC_CYCLE[64],TCC_EA0_ATOMIC[64],TCC_ATOMIC[65],TCC_BUBBLE[65],TCC_CYCLE[65],TCC_EA0_ATOMIC[65],TCC_ATOMIC[66],TCC_BUBBLE[66],TCC_CYCLE[66],TCC_EA0_ATOMIC[66],TCC_ATOMIC[67],TCC_BUBBLE[67],TCC_CYCLE[67],TCC_EA0_ATOMIC[67],TCC_ATOMIC[68],TCC_BUBBLE[68],TCC_CYCLE[68],TCC_EA0_ATOMIC[68],TCC_ATOMIC[69],TCC_BUBBLE[69],TCC_CYCLE[69],TCC_EA0_ATOMIC[69],TCC_ATOMIC[70],TCC_BUBBLE[70],TCC_CYCLE[70],TCC_EA0_ATOMIC[70],TCC_ATOMIC[71],TCC_BUBBLE[71],TCC_CYCLE[71],TCC_EA0_ATOMIC[71],TCC_ATOMIC[72],TCC_BUBBLE[72],TCC_CYCLE[72],TCC_EA0_ATOMIC[72],TCC_ATOMIC[73],TCC_BUBBLE[73],TCC_CYCLE[73],TCC_EA0_ATOMIC[73],TCC_ATOMIC[74],TCC_BUBBLE[74],TCC_CYCLE[74],TCC_EA0_ATOMIC[74],TCC_ATOMIC[75],TCC_BUBBLE[75],TCC_CYCLE[75],TCC_EA0_ATOMIC[75],TCC_ATOMIC[76],TCC_BUBBLE[76],TCC_CYCLE[76],TCC_EA0_ATOMIC[76],TCC_ATOMIC[77],TCC_BUBBLE[77],TCC_CYCLE[77],TCC_EA0_ATOMIC[77],TCC_ATOMIC[78],TCC_BUBBLE[78],TCC_CYCLE[78],TCC_EA0_ATOMIC[78],TCC_ATOMIC[79],TCC_BUBBLE[79],TCC_CYCLE[79],TCC_EA0_ATOMIC[79],TCC_ATOMIC[80],TCC_BUBBLE[80],TCC_CYCLE[80],TCC_EA0_ATOMIC[80],TCC_ATOMIC[81],TCC_BUBBLE[81],TCC_CYCLE[81],TCC_EA0_ATOMIC[81],TCC_ATOMIC[82],TCC_BUBBLE[82],TCC_CYCLE[82],TCC_EA0_ATOMIC[82],TCC_ATOMIC[83],TCC_BUBBLE[83],TCC_CYCLE[83],TCC_EA0_ATOMIC[83],TCC_ATOMIC[84],TCC_BUBBLE[84],TCC_CYCLE[84],TCC_EA0_ATOMIC[84],TCC_ATOMIC[85],TCC_BUBBLE[85],TCC_CYCLE[85],TCC_EA0_ATOMIC[85],TCC_ATOMIC[86],TCC_BUBBLE[86],TCC_CYCLE[86],TCC_EA0_ATOMIC[86],TCC_ATOMIC[87],TCC_BUBBLE[87],TCC_CYCLE[87],TCC_EA0_ATOMIC[87],TCC_ATOMIC[88],TCC_BUBBLE[88],TCC_CYCLE[88],TCC_EA0_ATOMIC[88],TCC_ATOMIC[89],TCC_BUBBLE[89],TCC_CYCLE[89],TCC_EA0_ATOMIC[89],TCC_ATOMIC[90],TCC_BUBBLE[90],TCC_CYCLE[90],TCC_EA0_ATOMIC[90],TCC_ATOMIC[91],TCC_BUBBLE[91],TCC_CYCLE[91],TCC_EA0_ATOMIC[91],TCC_ATOMIC[92],TCC_BUBBLE[92],TCC_CYCLE[92],TCC_EA0_ATOMIC[92],TCC_ATOMIC[93],TCC_BUBBLE[93],TCC_CYCLE[93],TCC_EA0_ATOMIC[93],TCC_ATOMIC[94],TCC_BUBBLE[94],TCC_CYCLE[94],TCC_EA0_ATOMIC[94],TCC_ATOMIC[95],TCC_BUBBLE[95],TCC_CYCLE[95],TCC_EA0_ATOMIC[95],TCC_ATOMIC[96],TCC_BUBBLE[96],TCC_CYCLE[96],TCC_EA0_ATOMIC[96],TCC_ATOMIC[97],TCC_BUBBLE[97],TCC_CYCLE[97],TCC_EA0_ATOMIC[97],TCC_ATOMIC[98],TCC_BUBBLE[98],TCC_CYCLE[98],TCC_EA0_ATOMIC[98],TCC_ATOMIC[99],TCC_BUBBLE[99],TCC_CYCLE[99],TCC_EA0_ATOMIC[99],TCC_ATOMIC[100],TCC_BUBBLE[100],TCC_CYCLE[100],TCC_EA0_ATOMIC[100],TCC_ATOMIC[101],TCC_BUBBLE[101],TCC_CYCLE[101],TCC_EA0_ATOMIC[101],TCC_ATOMIC[102],TCC_BUBBLE[102],TCC_CYCLE[102],TCC_EA0_ATOMIC[102],TCC_ATOMIC[103],TCC_BUBBLE[103],TCC_CYCLE[103],TCC_EA0_ATOMIC[103],TCC_ATOMIC[104],TCC_BUBBLE[104],TCC_CYCLE[104],TCC_EA0_ATOMIC[104],TCC_ATOMIC[105],TCC_BUBBLE[105],TCC_CYCLE[105],TCC_EA0_ATOMIC[105],TCC_ATOMIC[106],TCC_BUBBLE[106],TCC_CYCLE[106],TCC_EA0_ATOMIC[106],TCC_ATOMIC[107],TCC_BUBBLE[107],TCC_CYCLE[107],TCC_EA0_ATOMIC[107],TCC_ATOMIC[108],TCC_BUBBLE[108],TCC_CYCLE[108],TCC_EA0_ATOMIC[108],TCC_ATOMIC[109],TCC_BUBBLE[109],TCC_CYCLE[109],TCC_EA0_ATOMIC[109],TCC_ATOMIC[110],TCC_BUBBLE[110],TCC_CYCLE[110],TCC_EA0_ATOMIC[110],TCC_ATOMIC[111],TCC_BUBBLE[111],TCC_CYCLE[111],TCC_EA0_ATOMIC[111],TCC_ATOMIC[112],TCC_BUBBLE[112],TCC_CYCLE[112],TCC_EA0_ATOMIC[112],TCC_ATOMIC[113],TCC_BUBBLE[113],TCC_CYCLE[113],TCC_EA0_ATOMIC[113],TCC_ATOMIC[114],TCC_BUBBLE[114],TCC_CYCLE[114],TCC_EA0_ATOMIC[114],TCC_ATOMIC[115],TCC_BUBBLE[115],TCC_CYCLE[115],TCC_EA0_ATOMIC[115],TCC_ATOMIC[116],TCC_BUBBLE[116],TCC_CYCLE[116],TCC_EA0_ATOMIC[116],TCC_ATOMIC[117],TCC_BUBBLE[117],TCC_CYCLE[117],TCC_EA0_ATOMIC[117],TCC_ATOMIC[118],TCC_BUBBLE[118],TCC_CYCLE[118],TCC_EA0_ATOMIC[118],TCC_ATOMIC[119],TCC_BUBBLE[119],TCC_CYCLE[119],TCC_EA0_ATOMIC[119],TCC_ATOMIC[120],TCC_BUBBLE[120],TCC_CYCLE[120],TCC_EA0_ATOMIC[120],TCC_ATOMIC[121],TCC_BUBBLE[121],TCC_CYCLE[121],TCC_EA0_ATOMIC[121],TCC_ATOMIC[122],TCC_BUBBLE[122],TCC_CYCLE[122],TCC_EA0_ATOMIC[122],TCC_ATOMIC[123],TCC_BUBBLE[123],TCC_CYCLE[123],TCC_EA0_ATOMIC[123],TCC_ATOMIC[124],TCC_BUBBLE[124],TCC_CYCLE[124],TCC_EA0_ATOMIC[124],TCC_ATOMIC[125],TCC_BUBBLE[125],TCC_CYCLE[125],TCC_EA0_ATOMIC[125],TCC_ATOMIC[126],TCC_BUBBLE[126],TCC_CYCLE[126],TCC_EA0_ATOMIC[126],TCC_ATOMIC[127],TCC_BUBBLE[127],TCC_CYCLE[127],TCC_EA0_ATOMIC[127],Wave_Size_2,Correlation_ID_2,SQ_WAVES_LT_32,SQ_WAVES_LT_16,SQ_ITEMS,SQ_LDS_MEM_VIOLATIONS,SQ_LDS_ATOMIC_RETURN,SQ_LDS_IDX_ACTIVE,SQ_WAVES_RESTORED,SQ_WAVES_SAVED,SPI_RA_WVLIM_STALL_CSN,SPI_SWC_CSC_WR,TA_FLAT_ATOMIC_WAVEFRONTS_sum,TA_FLAT_WRITE_WAVEFRONTS_sum,TCC_ALL_TC_OP_INV_EVICT_sum,TCC_EA0_ATOMIC_sum,TCC_NORMAL_EVICT_sum,TCC_TOO_MANY_EA_WRREQS_STALL_sum,TCP_TCC_CC_READ_REQ_sum,TCP_TCC_CC_WRITE_REQ_sum,TCP_TCC_UC_ATOMIC_REQ_sum,TCP_TCC_UC_WRITE_REQ_sum,Wave_Size_3,Correlation_ID_3,SQ_INSTS_SMEM_NORM,SQ_INSTS_MFMA,SQ_INSTS_VALU_MFMA_I8,SQ_INSTS_VALU_MFMA_F16,SQ_INSTS_VALU_MFMA_BF16,SQ_INSTS_VALU_MFMA_F32,SQ_INSTS_VALU_MFMA_F64,SQ_VALU_MFMA_BUSY_CYCLES,SPI_VWC_CSC_WR,SPI_RA_BULKY_CU_FULL_CSN,TCC_EA0_ATOMIC_LEVEL_sum,TCC_EA0_RDREQ_LEVEL_sum,TCC_EA0_WRREQ_LEVEL_sum,TCC_EA0_WRREQ_STALL_sum,TCP_TCC_CC_ATOMIC_REQ_sum,TCP_TCC_RW_ATOMIC_REQ_sum,TCP_TCC_RW_READ_REQ_sum,TCP_TCC_RW_WRITE_REQ_sum,Wave_Size_4,Correlation_ID_4,SQ_INSTS_VALU_TRANS_F16,SQ_INSTS_VALU_ADD_F32,SQ_INSTS_VALU_MUL_F32,SQ_INSTS_VALU_FMA_F32,SQ_INSTS_VALU_TRANS_F32,SQ_INSTS_VALU_ADD_F64,SQ_INSTS_VALU_MUL_F64,SQ_INSTS_VALU_FMA_F64,SPI_RA_REQ_NO_ALLOC,SPI_RA_REQ_NO_ALLOC_CSN,CPC_CPC_STAT_STALL,CPC_UTCL1_STALL_ON_TRANSLATION,CPF_CPF_STAT_IDLE,CPF_CPF_TCIU_IDLE,TA_BUFFER_ATOMIC_WAVEFRONTS_sum,TA_BUFFER_TOTAL_CYCLES_sum,TCC_HIT_sum,TCC_MISS_sum,TCC_REQ_sum,TCC_STREAMING_REQ_sum,TCP_TOTAL_ACCESSES_sum,TCP_TOTAL_READ_sum,TCP_TOTAL_WRITE_sum,TCP_VOLATILE_sum,TD_ATOMIC_WAVEFRONT_sum,TD_STORE_WAVEFRONT_sum,Wave_Size_5,Correlation_ID_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Q_INST_CYCLES_SALU,SPI_RA_SGPR_SIMD_FULL_CSN,SPI_RA_LDS_CU_FULL_CSN,CPC_ME1_DC0_SPI_BUSY,TA_ADDR_STALLED_BY_TD_CYCLES_sum,TA_DATA_STALLED_BY_TC_CYCLES_sum,TCC_BUBBLE_sum,TCC_EA0_RDREQ_32B_sum,TCC_EA0_RDREQ_sum,TCC_EA0_RD_UNCACHED_32B_sum,TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum,TCP_TCC_ATOMIC_WITH_RET_REQ_sum,TCP_TCC_READ_REQ_sum,TCP_TCC_WRITE_REQ_sum,Start_Timestamp,End_Timestamp
0,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) 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