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Evgeny 7c4369bde4 Initial Commit
Contributors:
Ammar ELWazir <aelwazir@amd.com>
AravindanC <aravindan.cheruvally@amd.com>
Benjamin Welton <bewelton@amd.com>
Ma, Bing <Bing.Ma@amd.com>
Chun Yang <chun.yang@amd.com>
Cole Nelson <cole.nelson@amd.com>
Ethan Stewart <ethan.stewart@amd.com>
Evgeny <evgeny.shcherbakov@amd.com>
Freddy Paul <Freddy.paul@amd.com>
Giovanni Baraldi <gbaraldi@amd.com>
Gopesh Bhardwaj <Gopesh.Bhardwaj@amd.com>
Icarus Sparry <icarus.sparry@amd.com>
itrowbri <Ian.Trowbridge@amd.com>
James Edwards <JamesAdrian.Edwards@amd.com>
jatang <jatang@amd.com>
Jeremy Newton <Jeremy.Newton@amd.com>
Jonathan Kim <jonathan.kim@amd.com>
Kent Russell <kent.russell@amd.com>
Kiumars Sabeti <kiumars.sabeti@amd.com>
Lang Yu <lang.yu@amd.com>
Laurent Morichetti <laurent.morichetti@amd.com>
Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>
Manjunath Jakaraddi <manjunath.jakaraddi@amd.com>
Mark Laws <markdavid.laws@amd.com>
Mohan Kumar Mithur <Mohan.KumarMithur@amd.com>
Nicholas Curtis <nicurtis@amd.com>
Nirmal Unnikrishnan <Nirmal.Unnikrishnan@amd.com>
Parag Bhandari <parag.bhandari@amd.com>
Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>
Robert Gregory <Robert.Gregory@amd.com>
Saravanan Solaiyappan <saravanan.solaiyappan@amd.com>
Saurabh Verma <saurabh.verma@amd.com>
Srihari Uttanur <srihari.u@amd.com>
Srinivasan Subramanian <srinivasan.subramanian@amd.com>
Sriraksha Nagaraj <Sriraksha.Nagaraj@amd.com>
Sushma Vaddireddy <svaddire@amd.com>
Xianwei Zhang <Xianwei.Zhang@amd.com>


[ROCm/aqlprofile commit: 1ed169e30c]
2025-05-28 10:10:47 -05:00

50 строки
3.2 KiB
Plaintext

// Start counters PM4 packets sequence
// GRBM_GFX_INDEX broadcast
'SET_UCONFIG_REG' size(3) : c0017900 00000200 e0000000
// Disable RLC Perfmon Clock Gating, RLC_PERFMON_CLK_CNTL = 1
'SET_UCONFIG_REG' size(3) : c0017900 00001cbf 00000001
// CP_PERFMON_CNTL reset
'SET_UCONFIG_REG' size(3) : c0017900 00001808 00000000
// GRBM_GFX_INDEX to block instance (0)
'SET_UCONFIG_REG' size(3) : c0017900 00000200 a0000000
// Reset counter, PERFCOUNTER_RSLT_CNTL.CLEAR_ALL = 1
'COPY_DATA dst_sel=4' size(6) : c0044000 00000405 02000000 00000000 00002afb 00000000
// Setup counter, PERFCOUNTER*_CFG{PERF_SEL = event, PERF_MODE = ACCUM, ENABLE = 1}
'COPY_DATA dst_sel=4' size(6) : c0044000 00000405 10000000 00000000 00002af9 00000000
// Config counter, PERFCOUNTER_RSLT_CNTL = slot
'COPY_DATA dst_sel=4' size(6) : c0044000 00000405 00000000 00000000 00002afb 00000000
// Start counter, PERFCOUNTER_RSLT_CNTL.ENABLE_ANY = 1
'COPY_DATA dst_sel=4' size(6) : c0044000 00000405 01000000 00000000 00002afb 00000000
// GRBM_GFX_INDEX broadcast
'SET_UCONFIG_REG' size(3) : c0017900 00000200 e0000000
// Set COMPUTE_PERFCOUNT_ENABLE
'SET_SH_REG' size(3) : c0017600 0000020b 00000001
// CP_PERFMON_CNTL reset
'SET_UCONFIG_REG' size(3) : c0017900 00001808 00000000
// CP_PERFMON_CNTL start
'SET_UCONFIG_REG' size(3) : c0017900 00001808 00000001
// Issue barrier command to apply the commands to configure perfcounters
'BarrierCommand' size(2) : c0004600 00000407
'CacheFlushPacket' size(7) : c0055800 28c40000 ffffffff 00ffffff 00000000 00000000 00000004
// Stop/Sample counters PM4 packets sequence
// Issue barrier command to wait for dispatch to complete
'BarrierCommand' size(2) : c0004600 00000407
'CacheFlushPacket' size(7) : c0055800 28c40000 ffffffff 00ffffff 00000000 00000000 00000004
// CP_PERFMON_CNTL stop/sample
'SET_UCONFIG_REG' size(3) : c0017900 00001808 00000402
// GRBM_GFX_INDEX broadcast
'SET_UCONFIG_REG' size(3) : c0017900 00000200 e0000000
// GRBM_GFX_INDEX to block instance (0)
'SET_UCONFIG_REG' size(3) : c0017900 00000200 a0000000
// Config counter, PERFCOUNTER_RSLT_CNTL = slot
'COPY_DATA dst_sel=4' size(6) : c0044000 00000405 00000000 00000000 00002afb 00000000
// Read Perfcounter LO word
'COPY_DATA src_sel=4' size(6) : c0044000 02002504 00002af7 00000000 04d32000 00000000
// Read Perfcounter HI word
'COPY_DATA src_sel=4' size(6) : c0044000 02002504 00002af8 00000000 04d32004 00000000
// GRBM_GFX_INDEX broadcast
'SET_UCONFIG_REG' size(3) : c0017900 00000200 e0000000
// Enable RLC Perfmon Clock Gating, RLC_PERFMON_CLK_CNTL = 0
'SET_UCONFIG_REG' size(3) : c0017900 00001cbf 00000000