Evgeny
7c4369bde4
Contributors:
Ammar ELWazir <aelwazir@amd.com>
AravindanC <aravindan.cheruvally@amd.com>
Benjamin Welton <bewelton@amd.com>
Ma, Bing <Bing.Ma@amd.com>
Chun Yang <chun.yang@amd.com>
Cole Nelson <cole.nelson@amd.com>
Ethan Stewart <ethan.stewart@amd.com>
Evgeny <evgeny.shcherbakov@amd.com>
Freddy Paul <Freddy.paul@amd.com>
Giovanni Baraldi <gbaraldi@amd.com>
Gopesh Bhardwaj <Gopesh.Bhardwaj@amd.com>
Icarus Sparry <icarus.sparry@amd.com>
itrowbri <Ian.Trowbridge@amd.com>
James Edwards <JamesAdrian.Edwards@amd.com>
jatang <jatang@amd.com>
Jeremy Newton <Jeremy.Newton@amd.com>
Jonathan Kim <jonathan.kim@amd.com>
Kent Russell <kent.russell@amd.com>
Kiumars Sabeti <kiumars.sabeti@amd.com>
Lang Yu <lang.yu@amd.com>
Laurent Morichetti <laurent.morichetti@amd.com>
Mallya, Ameya Keshava <AmeyaKeshava.Mallya@amd.com>
Manjunath Jakaraddi <manjunath.jakaraddi@amd.com>
Mark Laws <markdavid.laws@amd.com>
Mohan Kumar Mithur <Mohan.KumarMithur@amd.com>
Nicholas Curtis <nicurtis@amd.com>
Nirmal Unnikrishnan <Nirmal.Unnikrishnan@amd.com>
Parag Bhandari <parag.bhandari@amd.com>
Ranjith Ramakrishnan <Ranjith.Ramakrishnan@amd.com>
Robert Gregory <Robert.Gregory@amd.com>
Saravanan Solaiyappan <saravanan.solaiyappan@amd.com>
Saurabh Verma <saurabh.verma@amd.com>
Srihari Uttanur <srihari.u@amd.com>
Srinivasan Subramanian <srinivasan.subramanian@amd.com>
Sriraksha Nagaraj <Sriraksha.Nagaraj@amd.com>
Sushma Vaddireddy <svaddire@amd.com>
Xianwei Zhang <Xianwei.Zhang@amd.com>
[ROCm/aqlprofile commit: 1ed169e30c]
46 baris
2.9 KiB
Plaintext
46 baris
2.9 KiB
Plaintext
// Start counters PM4 packets sequence
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// GRBM_GFX_INDEX broadcast
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 e0000000
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// CP_PERFMON_CNTL reset
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'SET_UCONFIG_REG' size(3) : c0017902 00001808 00000000
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// GRBM_GFX_INDEX to block instance (0)
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 a0000000
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// Reset counter, PERFCOUNTER_RSLT_CNTL.CLEAR_ALL = 1
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'COPY_DATA dst_sel=4' size(6) : c0044002 00000405 02000000 00000000 000007d4 00000000
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// Setup counter, PERFCOUNTER*_CFG{PERF_SEL = event, PERF_MODE = ACCUM, ENABLE = 1}
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'COPY_DATA dst_sel=4' size(6) : c0044002 00000405 10000000 00000000 000007bc 00000000
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// Config counter, PERFCOUNTER_RSLT_CNTL = slot
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'COPY_DATA dst_sel=4' size(6) : c0044002 00000405 000000ff 00000000 000007d4 00000000
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// Start counter, PERFCOUNTER_RSLT_CNTL.ENABLE_ANY = 1
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'COPY_DATA dst_sel=4' size(6) : c0044002 00000405 01000000 00000000 000007d4 00000000
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// GRBM_GFX_INDEX broadcast
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 e0000000
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// Set COMPUTE_PERFCOUNT_ENABLE
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'SET_SH_REG' size(3) : c0017602 0000020b 00000001
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// CP_PERFMON_CNTL reset
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'SET_UCONFIG_REG' size(3) : c0017902 00001808 00000000
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// CP_PERFMON_CNTL start
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'SET_UCONFIG_REG' size(3) : c0017902 00001808 00000001
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// Issue barrier command to apply the commands to configure perfcounters
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'BarrierCommand' size(2) : c0004602 00000407
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'CacheFlushPacket' size(7) : c0055802 28c40000 ffffffff 000000ff 00000000 00000000 00000004
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// Stop/Sample counters PM4 packets sequence
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// Issue barrier command to wait for dispatch to complete
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'BarrierCommand' size(2) : c0004602 00000407
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'CacheFlushPacket' size(7) : c0055802 28c40000 ffffffff 000000ff 00000000 00000000 00000004
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// CP_PERFMON_CNTL stop/sample
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'SET_UCONFIG_REG' size(3) : c0017902 00001808 00000402
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// GRBM_GFX_INDEX broadcast
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 e0000000
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// GRBM_GFX_INDEX to block instance (0)
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 a0000000
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// Config counter, PERFCOUNTER_RSLT_CNTL = slot
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'COPY_DATA dst_sel=4' size(6) : c0044002 00000405 000000ff 00000000 000007d4 00000000
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// Read Perfcounter LO word
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'COPY_DATA src_sel=4' size(6) : c0044002 04004504 000007a6 00000000 03adf000 00000000
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// Read Perfcounter HI word
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'COPY_DATA src_sel=4' size(6) : c0044002 04004504 000007ae 00000000 03adf004 00000000
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// GRBM_GFX_INDEX broadcast
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'SET_UCONFIG_REG' size(3) : c0017902 00000200 e0000000
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