Danylo Lytovchenko
609 строки
23 KiB
C++
609 строки
23 KiB
C++
/* Copyright (c) 2010 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#include "OCLBlitKernel.h"
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#include <Timer.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include "CL/cl.h"
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const static cl_uint Stages = 4;
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const static cl_uint ThreadsForCheck = 1 << Stages;
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#define KERNEL_CODE(...) #__VA_ARGS__
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const static char* strKernel =
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KERNEL_CODE(
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\n
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\x23 if OCL20
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\n
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extern void __amd_scheduler(__global void *, __global void *, uint);
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\n
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\x23 endif
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\n
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extern void __amd_copyBufferToImage(
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__global uint*, __write_only image2d_array_t, ulong4,
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int4, int4, uint4, ulong4);
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extern void __amd_copyImageToBuffer(
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__read_only image2d_array_t, __global uint*, __global ushort*,
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__global uchar*, int4, ulong4, int4, uint4, ulong4);
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extern void __amd_copyImage(
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__read_only image2d_array_t, __write_only image2d_array_t,
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int4, int4, int4);
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extern void __amd_copyImage1DA(
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__read_only image2d_array_t, __write_only image2d_array_t,
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int4, int4, int4);
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extern void __amd_copyBufferRect(
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__global uchar*, __global uchar*,
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ulong4, ulong4, ulong4);
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extern void __amd_copyBufferRectAligned(
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__global uint*, __global uint*,
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ulong4, ulong4, ulong4);
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extern void __amd_copyBuffer(
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__global uchar*, __global uchar*,
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ulong, ulong, ulong, uint);
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extern void __amd_copyBufferAligned(
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__global uint*, __global uint*,
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ulong, ulong, ulong, uint);
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extern void __amd_fillBuffer(
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__global uchar*, __global uint*, __constant uchar*,
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uint, ulong, ulong);
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extern void __amd_fillImage(
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__write_only image2d_array_t,
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float4, int4, uint4, int4, int4, uint);
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__kernel void copyBufferToImage(
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__global uint* src,
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__write_only image2d_array_t dst,
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ulong4 srcOrigin,
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int4 dstOrigin,
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int4 size,
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uint4 format,
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ulong4 pitch)
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{
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__amd_copyBufferToImage(src, dst, srcOrigin, dstOrigin, size, format, pitch);
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}
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__kernel void copyImageToBuffer(
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__read_only image2d_array_t src,
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__global uint* dstUInt,
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__global ushort* dstUShort,
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__global uchar* dstUChar,
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int4 srcOrigin,
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ulong4 dstOrigin,
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int4 size,
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uint4 format,
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ulong4 pitch)
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{
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__amd_copyImageToBuffer(src, dstUInt, dstUShort, dstUChar,
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srcOrigin, dstOrigin, size, format, pitch);
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}
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__kernel void copyImage(
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__read_only image2d_array_t src,
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__write_only image2d_array_t dst,
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int4 srcOrigin,
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int4 dstOrigin,
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int4 size)
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{
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__amd_copyImage(src, dst, srcOrigin, dstOrigin, size);
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}
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__kernel void copyImage1DA(
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__read_only image2d_array_t src,
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__write_only image2d_array_t dst,
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int4 srcOrigin,
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int4 dstOrigin,
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int4 size)
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{
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__amd_copyImage1DA(src, dst, srcOrigin, dstOrigin, size);
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}
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__kernel void copyBufferRect(
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__global uchar* src,
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__global uchar* dst,
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ulong4 srcRect,
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ulong4 dstRect,
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ulong4 size)
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{
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__amd_copyBufferRect(src, dst, srcRect, dstRect, size);
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}
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__kernel void copyBufferRectAligned(
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__global uint* src,
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__global uint* dst,
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ulong4 srcRect,
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ulong4 dstRect,
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ulong4 size)
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{
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__amd_copyBufferRectAligned(src, dst, srcRect, dstRect, size);
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}
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__kernel void copyBuffer(
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__global uchar* srcI,
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__global uchar* dstI,
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ulong srcOrigin,
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ulong dstOrigin,
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ulong size,
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uint remain)
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{
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__amd_copyBuffer(srcI, dstI, srcOrigin, dstOrigin, size, remain);
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}
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__kernel void copyBufferAligned(
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__global uint* src,
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__global uint* dst,
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ulong srcOrigin,
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ulong dstOrigin,
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ulong size,
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uint alignment)
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{
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__amd_copyBufferAligned(src, dst, srcOrigin, dstOrigin, size, alignment);
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}
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__kernel void fillBuffer(
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__global uchar* bufUChar,
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__global uint* bufUInt,
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__constant uchar* pattern,
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uint patternSize,
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ulong offset,
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ulong size)
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{
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__amd_fillBuffer(bufUChar, bufUInt, pattern, patternSize, offset, size);
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}
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__kernel void fillImage(
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__write_only image2d_array_t image,
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float4 patternFLOAT4,
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int4 patternINT4,
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uint4 patternUINT4,
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int4 origin,
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int4 size,
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uint type)
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{
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__amd_fillImage(image, patternFLOAT4, patternINT4, patternUINT4,
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origin, size, type);
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}
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\n
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\x23 if OCL20
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\n
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typedef struct _HsaAqlDispatchPacket {
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uint mix;
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ushort workgroup_size[3];
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ushort reserved2;
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uint grid_size[3];
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uint private_segment_size_bytes;
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uint group_segment_size_bytes;
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ulong kernel_object_address;
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ulong kernel_arg_address;
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ulong reserved3;
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ulong completion_signal;
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} HsaAqlDispatchPacket;
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\n
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// This is an OpenCLized hsa_control_directives_t
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typedef struct _AmdControlDirectives {
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ulong enabled_control_directives;
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ushort enable_break_exceptions;
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ushort enable_detect_exceptions;
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uint max_dynamic_group_size;
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ulong max_flat_grid_size;
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uint max_flat_workgroup_size;
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uchar required_dim;
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uchar reserved1[3];
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ulong required_grid_size[3];
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uint required_workgroup_size[3];
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uchar reserved2[60];
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} AmdControlDirectives;
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\n
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// This is an OpenCLized amd_kernel_code_t
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typedef struct _AmdKernelCode {
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uint amd_kernel_code_version_major;
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uint amd_kernel_code_version_minor;
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ushort amd_machine_kind;
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ushort amd_machine_version_major;
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ushort amd_machine_version_minor;
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ushort amd_machine_version_stepping;
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long kernel_code_entry_byte_offset;
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long kernel_code_prefetch_byte_offset;
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ulong kernel_code_prefetch_byte_size;
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ulong max_scratch_backing_memory_byte_size;
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uint compute_pgm_rsrc1;
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uint compute_pgm_rsrc2;
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uint kernel_code_properties;
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uint workitem_private_segment_byte_size;
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uint workgroup_group_segment_byte_size;
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uint gds_segment_byte_size;
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ulong kernarg_segment_byte_size;
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uint workgroup_fbarrier_count;
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ushort wavefront_sgpr_count;
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ushort workitem_vgpr_count;
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ushort reserved_vgpr_first;
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ushort reserved_vgpr_count;
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ushort reserved_sgpr_first;
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ushort reserved_sgpr_count;
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ushort debug_wavefront_private_segment_offset_sgpr;
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ushort debug_private_segment_buffer_sgpr;
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uchar kernarg_segment_alignment;
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uchar group_segment_alignment;
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uchar private_segment_alignment;
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uchar wavefront_size;
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int call_convention;
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uchar reserved1[12];
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ulong runtime_loader_kernel_symbol;
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AmdControlDirectives control_directives;
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} AmdKernelCode;
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\n
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typedef struct _HwDispatchHeader {
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uint writeData0; // CP WRITE_DATA write to rewind for memory
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uint writeData1;
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uint writeData2;
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uint writeData3;
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uint rewind; // REWIND execution
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uint startExe; // valid bit
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uint condExe0; // 0xC0032200 -- TYPE 3, COND_EXEC
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uint condExe1; // 0x00000204 ----
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uint condExe2; // 0x00000000 ----
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uint condExe3; // 0x00000000 ----
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uint condExe4; // 0x00000000 ----
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} HwDispatchHeader;
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\n
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typedef struct _HwDispatch {
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uint packet0; // 0xC0067602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (6 values)
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uint offset0; // 0x00000204 ---- OFFSET
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uint startX; // 0x00000000 ---- COMPUTE_START_X: START = 0x0
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uint startY; // 0x00000000 ---- COMPUTE_START_Y: START = 0x0
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uint startZ; // 0x00000000 ---- COMPUTE_START_Z: START = 0x0
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uint wrkGrpSizeX; // 0x00000000 ---- COMPUTE_NUM_THREAD_X: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint wrkGrpSizeY; // 0x00000000 ---- COMPUTE_NUM_THREAD_Y: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint wrkGrpSizeZ; // 0x00000000 ---- COMPUTE_NUM_THREAD_Z: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint packet1; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offset1; // 0x0000020C ---- OFFSET
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uint isaLo; // 0x00000000 ---- COMPUTE_PGM_LO: DATA = 0x0
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uint isaHi; // 0x00000000 ---- COMPUTE_PGM_HI: DATA = 0x0, INST_ATC__CI__VI = 0x0
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uint packet2; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offset2; // 0x00000212 ---- OFFSET
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uint resource1; // 0x00000000 ---- COMPUTE_PGM_RSRC1
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uint resource2; // 0x00000000 ---- COMPUTE_PGM_RSRC2
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uint packet3; // 0xc0017602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (1 value)
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uint offset3; // 0x00000215 ---- OFFSET
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uint pad31; // 0x000003ff ---- COMPUTE_RESOURCE_LIMITS
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uint packet31; // 0xC0067602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (1 value)
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uint offset31; // 0x00000218 ---- OFFSET
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uint ringSize; // 0x00000000 ---- COMPUTE_TMPRING_SIZE: WAVES = 0x0, WAVESIZE = 0x0
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uint user0; // 0xC0047602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (4 values)
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uint offsUser0; // 0x00000240 ---- OFFSET
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uint scratchLo; // 0x00000000 ---- COMPUTE_USER_DATA_0: DATA = 0x0
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uint scratchHi; // 0x80000000 ---- COMPUTE_USER_DATA_1: DATA = 0x80000000
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uint scratchSize; // 0x00000000 ---- COMPUTE_USER_DATA_2: DATA = 0x0
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uint padUser; // 0x00EA7FAC ---- COMPUTE_USER_DATA_3: DATA = 0xEA7FAC
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uint user1; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser1; // 0x00000244 ---- OFFSET
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uint aqlPtrLo; // 0x00000000 ---- COMPUTE_USER_DATA_4: DATA = 0x0
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uint aqlPtrHi; // 0x00000000 ---- COMPUTE_USER_DATA_5: DATA = 0x0
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uint user2; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser2; // 0x00000246 ---- OFFSET
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uint hsaQueueLo; // 0x00000000 ---- COMPUTE_USER_DATA_6: DATA = 0x0
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uint hsaQueueHi; // 0x00000000 ---- COMPUTE_USER_DATA_7: DATA = 0x0
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uint user3; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser3; // 0x00000246 ---- OFFSET
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uint argsLo; // 0x00000000 ---- COMPUTE_USER_DATA_8: DATA = 0x0
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uint argsHi; // 0x00000000 ---- COMPUTE_USER_DATA_9: DATA = 0x0
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uint copyData; // 0xC0044000 -- TYPE 3, COPY_DATA
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uint copyDataFlags; // 0x00000405 ---- srcSel 0x5, destSel 0x4, countSel 0x0, wrConfirm 0x0, engineSel 0x0
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uint scratchAddrLo; // 0x000201C4 ---- srcAddressLo
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uint scratchAddrHi; // 0x00000000 ---- srcAddressHi
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uint shPrivateLo; // 0x00002580 ---- dstAddressLo
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uint shPrivateHi; // 0x00000000 ---- dstAddressHi
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uint user4; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser4; // 0x00000248 ---- OFFSET
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uint scratchOffs; // 0x00000000 ---- COMPUTE_USER_DATA_10: DATA = 0x0
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uint privSize; // 0x00000030 ---- COMPUTE_USER_DATA_11: DATA = 0x30
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uint packet4; // 0xC0031502 -- TYPE 3, DISPATCH_DIRECT, TYPE:COMPUTE
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uint glbSizeX; // 0x00000000
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uint glbSizeY; // 0x00000000
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uint glbSizeZ; // 0x00000000
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uint padd41; // 0x00000021
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} HwDispatch;
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\n
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static const uint WavefrontSize = 64;
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static const uint MaxWaveSize = 0x400;
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static const uint UsrRegOffset = 0x240;
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static const uint Pm4Nop = 0xC0001002;
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static const uint Pm4UserRegs = 0xC0007602;
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static const uint Pm4CopyReg = 0xC0044000;
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static const uint PrivateSegEna = 0x1;
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static const uint DispatchEna = 0x2;
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static const uint QueuePtrEna = 0x4;
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static const uint KernelArgEna = 0x8;
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static const uint FlatScratchEna = 0x20;
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\n
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uint GetCmdTemplateHeaderSize() { return sizeof(HwDispatchHeader); }
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\n
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uint GetCmdTemplateDispatchSize() { return sizeof(HwDispatch); }
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\n
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void EmptyCmdTemplateDispatch(ulong cmdBuf)
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{
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volatile __global HwDispatch* dispatch = (volatile __global HwDispatch*)cmdBuf;
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dispatch->glbSizeX = 0;
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dispatch->glbSizeY = 0;
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dispatch->glbSizeZ = 0;
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}
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\n
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void RunCmdTemplateDispatch(
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ulong cmdBuf,
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__global HsaAqlDispatchPacket* aqlPkt,
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ulong scratch,
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ulong hsaQueue,
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uint scratchSize,
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uint scratchOffset,
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uint numMaxWaves,
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uint useATC)
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\n
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{
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volatile __global HwDispatch* dispatch = (volatile __global HwDispatch*)cmdBuf;
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uint usrRegCnt = 0;
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// Program workgroup size
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dispatch->wrkGrpSizeX = aqlPkt->workgroup_size[0];
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dispatch->wrkGrpSizeY = aqlPkt->workgroup_size[1];
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dispatch->wrkGrpSizeZ = aqlPkt->workgroup_size[2];
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// ISA address
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__global AmdKernelCode* kernelObj = (__global AmdKernelCode*)aqlPkt->kernel_object_address;
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ulong isa = aqlPkt->kernel_object_address + kernelObj->kernel_code_entry_byte_offset;
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dispatch->isaLo = (uint)(isa >> 8);
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dispatch->isaHi = (uint)(isa >> 40) | (useATC ? 0x100 : 0);
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// Program PGM resource registers
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dispatch->resource1 = kernelObj->compute_pgm_rsrc1;
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dispatch->resource2 = kernelObj->compute_pgm_rsrc2;
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uint flags = kernelObj->kernel_code_properties;
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uint privateSize = kernelObj->workitem_private_segment_byte_size;
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uint ldsSize = aqlPkt->group_segment_size_bytes +
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kernelObj->workgroup_group_segment_byte_size;
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// Align up the LDS blocks 128 * 4(in DWORDs)
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uint ldsBlocks = (ldsSize + 511) >> 9;
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dispatch->resource2 |= (ldsBlocks << 15);
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// Private/scratch segment was enabled
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if (flags & PrivateSegEna) {
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uint waveSize = privateSize * WavefrontSize;
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// 256 DWRODs is the minimum for SQ
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waveSize = max(MaxWaveSize, waveSize);
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uint numWaves = scratchSize / waveSize;
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numWaves = min(numWaves, numMaxWaves);
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dispatch->ringSize = numWaves;
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dispatch->ringSize |= (waveSize >> 10) << 12;
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dispatch->user0 = Pm4UserRegs | (4 << 16);
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dispatch->scratchLo = (uint)scratch;
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dispatch->scratchHi = ((uint)(scratch >> 32)) | 0x80000000; // Enables swizzle
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dispatch->scratchSize = scratchSize;
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usrRegCnt += 4;
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}
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else {
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dispatch->ringSize = 0;
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dispatch->user0 = Pm4Nop | (4 << 16);
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}
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// Pointer to the AQL dispatch packet
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dispatch->user1 = (flags & DispatchEna) ? (Pm4UserRegs | (2 << 16)) : (Pm4Nop | (2 << 16));
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dispatch->offsUser1 = UsrRegOffset + usrRegCnt;
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usrRegCnt += (flags & DispatchEna) ? 2 : 0;
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ulong gpuAqlPtr = (ulong)aqlPkt;
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dispatch->aqlPtrLo = (uint)gpuAqlPtr;
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dispatch->aqlPtrHi = (uint)(gpuAqlPtr >> 32);
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// Pointer to the AQL queue header
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if (flags & QueuePtrEna) {
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dispatch->user2 = Pm4UserRegs | (2 << 16);
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dispatch->offsUser2 = UsrRegOffset + usrRegCnt;
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usrRegCnt += 2;
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dispatch->hsaQueueLo = (uint)hsaQueue;
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dispatch->hsaQueueHi = (uint)(hsaQueue >> 32);
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}
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else {
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dispatch->user2 = Pm4Nop | (2 << 16);
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}
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// Pointer to the AQL kernel arguments
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dispatch->user3 = (flags & KernelArgEna) ? (Pm4UserRegs | (2 << 16)) : (Pm4Nop | (2 << 16));
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dispatch->offsUser3 = UsrRegOffset + usrRegCnt;
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usrRegCnt += (flags & KernelArgEna) ? 2 : 0;
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dispatch->argsLo = (uint)aqlPkt->kernel_arg_address;
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dispatch->argsHi = (uint)(aqlPkt->kernel_arg_address >> 32);
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// Provide pointer to the private/scratch buffer for the flat address
|
|
if (flags & FlatScratchEna) {
|
|
dispatch->copyData = Pm4CopyReg;
|
|
dispatch->scratchAddrLo = (uint)((scratch - scratchOffset) >> 16);
|
|
dispatch->offsUser4 = UsrRegOffset + usrRegCnt;
|
|
dispatch->scratchOffs = scratchOffset;
|
|
dispatch->privSize = privateSize;
|
|
}
|
|
else {
|
|
dispatch->copyData = Pm4Nop | (8 << 16);
|
|
}
|
|
|
|
// Update the global launch grid
|
|
dispatch->glbSizeX = aqlPkt->grid_size[0];
|
|
dispatch->glbSizeY = aqlPkt->grid_size[1];
|
|
dispatch->glbSizeZ = aqlPkt->grid_size[2];
|
|
}
|
|
\n
|
|
__kernel void scheduler(
|
|
__global void * queue,
|
|
__global void * params,
|
|
uint paramIdx)
|
|
{
|
|
__amd_scheduler(queue, params, paramIdx);
|
|
}
|
|
\n
|
|
\x23 endif
|
|
\n
|
|
);
|
|
|
|
enum {
|
|
BlitCopyImage = 0,
|
|
BlitCopyImage1DA,
|
|
BlitCopyImageToBuffer,
|
|
BlitCopyBufferToImage,
|
|
BlitCopyBufferRect,
|
|
BlitCopyBufferRectAligned,
|
|
BlitCopyBuffer,
|
|
BlitCopyBufferAligned,
|
|
FillBuffer,
|
|
FillImage,
|
|
Scheduler,
|
|
BlitTotal
|
|
};
|
|
|
|
static const char* BlitName[BlitTotal] = {
|
|
"copyImage", "copyImage1DA", "copyImageToBuffer",
|
|
"copyBufferToImage", "copyBufferRect", "copyBufferRectAligned",
|
|
"copyBuffer", "copyBufferAligned", "fillBuffer",
|
|
"fillImage", "scheduler",
|
|
};
|
|
|
|
OCLBlitKernel::OCLBlitKernel() { _numSubTests = 1; }
|
|
|
|
OCLBlitKernel::~OCLBlitKernel() {}
|
|
|
|
void OCLBlitKernel::open(unsigned int test, char* units, double& conversion,
|
|
unsigned int deviceId) {
|
|
OCLTestImp::open(test, units, conversion, deviceId);
|
|
CHECK_RESULT((error_ != CL_SUCCESS), "Error opening test");
|
|
char dbuffer[1024] = {0};
|
|
CPerfCounter timer;
|
|
int sub = 0;
|
|
std::string options = "-cl-std=CL2.0 -DOCL20=1";
|
|
|
|
cl_device_type deviceType;
|
|
error_ = _wrapper->clGetDeviceInfo(devices_[deviceId], CL_DEVICE_TYPE, sizeof(deviceType),
|
|
&deviceType, NULL);
|
|
CHECK_RESULT((error_ != CL_SUCCESS), "CL_DEVICE_TYPE failed");
|
|
|
|
if (!(deviceType & CL_DEVICE_TYPE_GPU)) {
|
|
testDescString = "GPU device is required for this test!\n";
|
|
return;
|
|
}
|
|
|
|
size_t param_size = 0;
|
|
char* strVersion = 0;
|
|
error_ = _wrapper->clGetDeviceInfo(devices_[_deviceId], CL_DEVICE_VERSION, 0, 0, ¶m_size);
|
|
CHECK_RESULT(error_ != CL_SUCCESS, "clGetDeviceInfo failed");
|
|
strVersion = new char[param_size];
|
|
error_ =
|
|
_wrapper->clGetDeviceInfo(devices_[_deviceId], CL_DEVICE_VERSION, param_size, strVersion, 0);
|
|
CHECK_RESULT(error_ != CL_SUCCESS, "clGetDeviceInfo failed");
|
|
if (strVersion[7] < '2') {
|
|
options = "-DOCL20=0";
|
|
sub = 1;
|
|
delete strVersion;
|
|
testDescString = "Currently it works for OCL20 devices only!\n";
|
|
return;
|
|
}
|
|
delete strVersion;
|
|
|
|
error_ = _wrapper->clGetDeviceInfo(devices_[_deviceId], CL_DRIVER_VERSION, 0, 0, ¶m_size);
|
|
CHECK_RESULT(error_ != CL_SUCCESS, "clGetDeviceInfo failed");
|
|
strVersion = new char[param_size];
|
|
error_ =
|
|
_wrapper->clGetDeviceInfo(devices_[_deviceId], CL_DRIVER_VERSION, param_size, strVersion, 0);
|
|
CHECK_RESULT(error_ != CL_SUCCESS, "clGetDeviceInfo failed");
|
|
|
|
std::string sch = strKernel;
|
|
static const char AmdScheduler[] = "amd_scheduler";
|
|
static const char AmdSchedulerPal[] = "amd_scheduler_pal";
|
|
static const char AmdSchedulerROCm[] = "amd_scheduler_rocm";
|
|
const char* AmdSchedulerPatch = NULL;
|
|
size_t loc = 0;
|
|
|
|
if (NULL != strstr(strVersion, "LC")) {
|
|
if (NULL != strstr(strVersion, "PAL")) {
|
|
AmdSchedulerPatch = AmdSchedulerPal;
|
|
} else if (NULL != strstr(strVersion, "HSA")) {
|
|
AmdSchedulerPatch = AmdSchedulerROCm;
|
|
}
|
|
}
|
|
delete strVersion;
|
|
|
|
if (NULL != AmdSchedulerPatch) {
|
|
loc = sch.find(AmdScheduler);
|
|
sch.replace(loc, strlen(AmdScheduler), AmdSchedulerPatch);
|
|
loc = sch.find(AmdScheduler, (loc + strlen(AmdSchedulerPatch)));
|
|
sch.replace(loc, strlen(AmdScheduler), AmdSchedulerPatch);
|
|
}
|
|
|
|
timer.Reset();
|
|
timer.Start();
|
|
|
|
const char* strProgram = sch.c_str();
|
|
program_ = _wrapper->clCreateProgramWithSource(context_, 1, &strProgram, NULL, &error_);
|
|
CHECK_RESULT((error_ != CL_SUCCESS), "clCreateProgramWithSource() failed");
|
|
error_ = _wrapper->clBuildProgram(program_, 1, &devices_[deviceId], options.c_str(), NULL, NULL);
|
|
if (error_ != CL_SUCCESS) {
|
|
char programLog[1024];
|
|
_wrapper->clGetProgramBuildInfo(program_, devices_[deviceId], CL_PROGRAM_BUILD_LOG, 1024,
|
|
programLog, 0);
|
|
printf("\n%s\n", programLog);
|
|
fflush(stdout);
|
|
}
|
|
CHECK_RESULT((error_ != CL_SUCCESS), "clBuildProgram() failed");
|
|
|
|
cl_kernel kernels[BlitTotal];
|
|
for (int i = 0; i < BlitTotal - sub; ++i) {
|
|
kernels[i] = _wrapper->clCreateKernel(program_, BlitName[i], &error_);
|
|
CHECK_RESULT((error_ != CL_SUCCESS), "clCreateKernel() failed");
|
|
}
|
|
timer.Stop();
|
|
double sec = timer.GetElapsedTime();
|
|
|
|
time_ = (float)sec * 1000.f;
|
|
testDescString = "Blit kernel compilaiton time (ms):";
|
|
|
|
for (int i = 0; i < BlitTotal - sub; ++i) {
|
|
_wrapper->clReleaseKernel(kernels[i]);
|
|
}
|
|
}
|
|
|
|
void OCLBlitKernel::run(void) { _perfInfo = time_; }
|
|
|
|
unsigned int OCLBlitKernel::close(void) { return OCLTestImp::close(); }
|