Danylo Lytovchenko
220 righe
9.1 KiB
C++
220 righe
9.1 KiB
C++
/*
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Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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#include "atomicExch_common.hh"
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#include "atomicExch_negative_kernels_rtc.hh"
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/**
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* @addtogroup atomicExch atomicExch
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* @{
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* @ingroup AtomicsTest
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*/
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/**
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* Test Description
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* ------------------------
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* - Executes a kernel wherein all threads will perform an atomic exchange in the same(compile
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* time deducible) memory location. Each thread will exchange its own grid wide linear index + 1
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* into the memory location, storing the return value into a separate output array slot
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* corresponding to it. Once complete, the union of output array and exchange memory is validated to
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* contain all values in the range [0, number_of_threads].
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*
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* - The test is run for:
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* - All overloads of atomicExch
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated exchange memory
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* - Exchange memory located in shared memory
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* - Several grid and block dimension combinations(only one block is used for shared memory)
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* Test source
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* ------------------------
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* - unit/atomics/atomicExch.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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#if HT_NVIDIA
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive_Same_Address_Compile_Time", "", int, unsigned int,
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unsigned long long, float) {
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#else
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive_Same_Address_Compile_Time", "", int, unsigned int,
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unsigned long, unsigned long long, float, double) {
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#endif // HT_NVIDIA
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for (auto current = 0; current < cmd_options.iterations; ++current) {
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DYNAMIC_SECTION("Positive Same Address" << current) {
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AtomicExchSameAddressTest<TestType, AtomicScopes::device>();
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}
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}
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}
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/**
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* Test Description
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* ------------------------
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* - Executes a single kernel on a single device wherein all threads will perform an atomic
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* exchange into a runtime determined memory location. Each thread will exchange its own grid wide
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* linear index + offset into the memory location, storing the return value into a separate output
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* array slot corresponding to it. Once complete, the union of output array and exchange memory is
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* validated to contain all values in the range [0, number_of_threads +
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* number_of_exchange_memory_slots). Several memory access patterns are tested:
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* -# All threads exchange to a single memory location
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* -# Each thread exchanges into an array containing warp_size elements, using tid % warp_size
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* for indexing
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* -# Same as the above, but the exchange elements are spread out by L1 cache line size bytes.
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*
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* - The test is run for:
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* - All overloads of atomicExch
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated exchange memory
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* - Exchange memory located in shared memory
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* - Several grid and block dimension combinations(only one block is used for shared memory)
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* Test source
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* ------------------------
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* - unit/atomics/atomicExch.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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#if HT_NVIDIA
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive", "", int, unsigned int, unsigned long long, float) {
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#else
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive", "", int, unsigned int, unsigned long,
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unsigned long long, float, double) {
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#endif // HT_NVIDIA
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int warp_size = 0;
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HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
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const auto cache_line_size = 128u;
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for (auto current = 0; current < cmd_options.iterations; ++current) {
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DYNAMIC_SECTION("Same address " << current) {
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AtomicExchSingleDeviceSingleKernelTest<TestType, AtomicScopes::device>(1, sizeof(TestType));
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}
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DYNAMIC_SECTION("Adjacent addresses " << current) {
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AtomicExchSingleDeviceSingleKernelTest<TestType, AtomicScopes::device>(warp_size,
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sizeof(TestType));
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}
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DYNAMIC_SECTION("Scattered addresses " << current) {
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AtomicExchSingleDeviceSingleKernelTest<TestType, AtomicScopes::device>(warp_size,
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cache_line_size);
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}
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}
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}
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/**
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* Test Description
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* ------------------------
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* - Executes a kernel two times concurrently on a single device wherein all threads will perform
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* an atomic exchange into a runtime determined memory location. Each thread will exchange its own
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* grid wide linear index + offset into the memory location, storing the return value into a
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* separate output array slot corresponding to it. Once complete, the union of output array and
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* exchange memory is validated to contain all values in the range [0, number_of_threads +
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* number_of_exchange_memory_slots). Several memory access patterns are tested:
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* -# All threads exchange to a single memory location
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* -# Each thread exchanges into an array containing warp_size elements, using tid % warp_size
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* for indexing
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* -# Same as the above, but the exchange elements are spread out by L1 cache line size bytes.
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*
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* - The test is run for:
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* - All overloads of atomicExch
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* - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated exchange memory
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* - Several grid and block dimension combinations
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* Test source
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* ------------------------
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* - unit/atomics/atomicExch.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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#if HT_NVIDIA
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive_Multi_Kernel", "", int, unsigned int,
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unsigned long long, float) {
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#else
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TEMPLATE_TEST_CASE("Unit_atomicExch_Positive_Multi_Kernel", "", int, unsigned int, unsigned long,
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unsigned long long, float, double) {
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#endif // HT_NVIDIA
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int warp_size = 0;
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HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0));
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const auto cache_line_size = 128u;
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for (auto current = 0; current < cmd_options.iterations; ++current) {
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DYNAMIC_SECTION("Same address " << current) {
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AtomicExchSingleDeviceMultipleKernelTest<TestType, AtomicScopes::device>(2, 1,
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sizeof(TestType));
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}
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DYNAMIC_SECTION("Adjacent addresses " << current) {
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AtomicExchSingleDeviceMultipleKernelTest<TestType, AtomicScopes::device>(2, warp_size,
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sizeof(TestType));
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}
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DYNAMIC_SECTION("Scattered addresses " << current) {
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AtomicExchSingleDeviceMultipleKernelTest<TestType, AtomicScopes::device>(2, warp_size,
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cache_line_size);
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}
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}
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}
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/**
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* Test Description
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* ------------------------
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* - RTCs kernels that pass combinations of arguments of invalid types for all overloads of
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* atomicExch
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* Test source
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* ------------------------
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* - unit/atomics/atomicExch.cc
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* Test requirements
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* ------------------------
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* - HIP_VERSION >= 5.2
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*/
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TEST_CASE("Unit_atomicExch_Negative_Parameters_RTC") {
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hiprtcProgram program{};
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const auto program_source = GENERATE(kAtomicExchInt, kAtomicExchUnsignedInt, kAtomicExchULL,
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kAtomicExchFloat, kAtomicExchDouble);
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HIPRTC_CHECK(
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hiprtcCreateProgram(&program, program_source, "atomicExch_negative.cc", 0, nullptr, nullptr));
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hiprtcResult result{hiprtcCompileProgram(program, 0, nullptr)};
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// Get the compile log and count compiler error messages
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size_t log_size{};
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HIPRTC_CHECK(hiprtcGetProgramLogSize(program, &log_size));
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std::string log(log_size, ' ');
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HIPRTC_CHECK(hiprtcGetProgramLog(program, log.data()));
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int error_count{0};
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int expected_error_count{8};
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std::string error_message{"error:"};
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size_t n_pos = log.find(error_message, 0);
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while (n_pos != std::string::npos) {
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++error_count;
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n_pos = log.find(error_message, n_pos + 1);
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}
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HIPRTC_CHECK(hiprtcDestroyProgram(&program));
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HIPRTC_CHECK_ERROR(result, HIPRTC_ERROR_COMPILATION);
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REQUIRE(error_count == expected_error_count);
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}
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/**
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* End doxygen group AtomicsTest.
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* @}
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*/
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