JoseSantosAMD
e664f7abf4
* Updated links in documentation. (#328)
Updated to reflect new GitHub organization.
Fixed broken links to GitHub pages.
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
* update branch for 2.x documentation builds
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* update checkout action and use concurrency instead of cancel-workflow-action
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* test addition of user option for container launch
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* remove --user option for container, try chown instead
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* fixing yaml syntax
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* reorder job step - start with checkout
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* restore missing run directive
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
* Update workloads to include log.txt
Add missing MI200 workloads
Signed-off-by: Jose Santos <josantos@amd.com>
* Signed-off-by: Jose Santos <josantos@amd.com>
Add vcopy workload for tests
* Change exit codes for caught failures
Signed-off-by: Jose Santos <josantos@amd.com>
* reformat
Signed-off-by: Jose Santos <josantos@amd.com>
* Add pytest-xdist for pytest -n
Signed-off-by: Jose Santos <josantos@amd.com>
---------
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Signed-off-by: Karl W. Schulz <karl.schulz@amd.com>
Signed-off-by: Jose Santos <josantos@amd.com>
Co-authored-by: David Galiffi <David.Galiffi@amd.com>
Co-authored-by: Karl W. Schulz <karl.schulz@amd.com>
[ROCm/rocprofiler-compute commit: da506ad9b5]
35 KiB
35 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_1 | obj_1 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_2 | obj_2 | SQ_INSTS_VALU_INT64 | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TD_COALESCABLE_WAVEFRONT_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_3 | obj_3 | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | wave_size_4 | obj_4 | SQ_INSTS_SMEM_NORM | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F32 | SQ_INSTS_VALU_MFMA_F64 | SQ_VALU_MFMA_BUSY_CYCLES | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | TCC_EA_ATOMIC_LEVEL_sum | wave_size_5 | obj_5 | SQ_INSTS_FLAT_LDS_ONLY | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_6 | obj_6 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_7 | obj_7 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_8 | obj_8 | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | wave_size_9 | obj_9 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_10 | obj_10 | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_DRAM_sum | TCC_TAG_STALL_sum | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | wave_size_11 | obj_11 | SQ_INSTS_VALU_MUL_F32 | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_TRANS_F32 | SQ_INSTS_VALU_ADD_F64 | SQ_INSTS_VALU_MUL_F64 | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VALU_INT32 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_12 | obj_12 | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | wave_size_13 | obj_13 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_14 | obj_14 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | wave_size_15 | obj_15 | SQ_INSTS_VSKIPPED | SQ_INSTS | SQ_INSTS_VALU | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_MUL_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_INSTS_VALU_TRANS_F16 | SQ_INSTS_VALU_ADD_F32 | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_SPI_STALL_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_16 | obj_16 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VALU_CVT | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_17 | obj_17 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_18 | obj_18 | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f719d074ec0 | 0 | 1280294 | 4096 | 4096 | 0 | 1016298 | 4096 | 4096 | 0 | 1173736 | 4096 | 4096 | 0 | 1331612 | 4096 | 4096 | 0 | 1104334 | 4096 | 4096 | 0 | 1203531 | 4096 | 4096 | 0 | 1008753 | 4096 | 4096 | 0 | 1292385 | 4096 | 4096 | 0 | 1190225 | 4096 | 4096 | 0 | 1227828 | 4096 | 4096 | 0 | 1131202 | 4096 | 4096 | 0 | 1203672 | 4096 | 4096 | 0 | 1138456 | 4096 | 4096 | 0 | 1183327 | 4096 | 4096 | 0 | 1394894 | 4096 | 4096 | 0 | 1277117 | 4096 | 4096 | 0 | 1253645 | 4096 | 4096 | 0 | 1265595 | 4096 | 4096 | 0 | 1071387 | 4096 | 4096 | 0 | 1761815 | 4096 | 4096 | 0 | 1356100 | 4096 | 4096 | 0 | 1511464 | 4096 | 4096 | 0 | 1122717 | 4096 | 4096 | 0 | 1268678 | 4096 | 4096 | 0 | 1126448 | 4096 | 4096 | 0 | 1062773 | 4096 | 4096 | 0 | 1041707 | 4096 | 4096 | 0 | 1233636 | 4096 | 4096 | 0 | 1492365 | 4096 | 4096 | 0 | 1237295 | 4096 | 4096 | 0 | 1420029 | 4096 | 4096 | 0 | 1217238 | 4096 | 4096 | 64 | 0x7f5871864ec0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 0 | 27506 | 0 | 0 | 64 | 0x7f842c814ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 10074 | 0 | 816 | 27715 | 0 | 73251.0 | 131072.0 | 0.0 | 65568.0 | 64 | 0x7f64e75d8ec0 | 1276 | 114416 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f01f2d00ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 39527436.0 | 35354785.0 | 0.0 | 64 | 0x7f6ecb88cec0 | 0 | 0 | 0 | 0 | 0 | 0 | 168 | 56 | 131072.0 | 131072.0 | 0.0 | 946191.0 | 64 | 0x7fc1d67f8ec0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 129 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 147 | 0 | 4098 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 355 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 207 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7feb1c338ec0 | 2253 | 4099 | 2256 | 6352 | 2274 | 4096 | 2274 | 6370 | 2292 | 4096 | 2292 | 6388 | 2317 | 4096 | 2317 | 6413 | 2232 | 4096 | 2232 | 6328 | 2266 | 4096 | 2266 | 6362 | 2275 | 4096 | 2275 | 6371 | 2286 | 4096 | 2286 | 6382 | 2287 | 4096 | 2287 | 6383 | 2249 | 4096 | 2249 | 6345 | 2279 | 4096 | 2279 | 6375 | 2295 | 4096 | 2295 | 6391 | 2315 | 4096 | 2315 | 6411 | 2238 | 4096 | 2238 | 6334 | 2270 | 4096 | 2270 | 6366 | 2277 | 4096 | 2277 | 6373 | 2263 | 4096 | 2263 | 6359 | 2285 | 4096 | 2285 | 6381 | 2196 | 4098 | 2198 | 6294 | 2265 | 4096 | 2265 | 6361 | 2327 | 4097 | 2328 | 6424 | 2304 | 4096 | 2304 | 6400 | 2280 | 4096 | 2280 | 6376 | 2435 | 4098 | 2437 | 6533 | 2270 | 4096 | 2270 | 6366 | 2262 | 4096 | 2262 | 6358 | 2286 | 4096 | 2286 | 6382 | 2204 | 4096 | 2204 | 6300 | 2266 | 4096 | 2266 | 6362 | 2270 | 4096 | 2270 | 6366 | 2308 | 4096 | 2308 | 6404 | 2280 | 4096 | 2280 | 6376 | 64 | 0x7f0c851d0ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 27530242.0 | 84637584.0 | 37276646.0 | 131072.0 | 0.0 | 221242.0 | 0 | 0 | 15056 | 687.0 | 131086.0 | 0.0 | 20.0 | 64 | 0x7f2a26314ec0 | 0 | 0 | 0 | 1027825 | 74 | 0 | 0 | 1131751 | 0 | 0 | 0 | 1057543 | 0 | 0 | 0 | 1097462 | 0 | 0 | 0 | 1120029 | 55 | 0 | 0 | 1246251 | 0 | 0 | 0 | 1072885 | 0 | 0 | 0 | 1216521 | 0 | 0 | 0 | 1086561 | 0 | 0 | 0 | 1064423 | 0 | 0 | 0 | 1004711 | 0 | 0 | 0 | 1108645 | 0 | 0 | 0 | 1024831 | 0 | 0 | 0 | 1142102 | 0 | 0 | 0 | 1177389 | 22 | 0 | 0 | 1214656 | 0 | 0 | 0 | 1014701 | 0 | 0 | 0 | 1107805 | 0 | 0 | 0 | 1131637 | 0 | 0 | 0 | 1218413 | 0 | 0 | 0 | 1074604 | 0 | 0 | 0 | 1079222 | 60 | 0 | 0 | 1246159 | 0 | 0 | 0 | 1124479 | 0 | 0 | 0 | 1077444 | 0 | 0 | 0 | 1099417 | 145 | 0 | 0 | 1205829 | 41 | 0 | 0 | 1224358 | 0 | 0 | 0 | 1128386 | 0 | 0 | 0 | 1121967 | 0 | 0 | 0 | 1026123 | 69 | 0 | 0 | 1279568 | 64 | 0x7f980b700ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131079.0 | 33891.0 | 46047.0 | 19489.0 | 64 | 0x7f9e9e168ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13604 | 19334 | 8300 | 545 | 0 | 27266 | 204016.0 | 0.0 | 72935.0 | 131081.0 | 64 | 0x7f80e4520ec0 | 0 | 0 | 0 | 224 | 0 | 65536 | 64132 | 56 | 64 | 0x7fbd96bb4ec0 | 10620646 | 9564806 | 711776 | 344064 | 1594430 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 277686.0 | 32768.0 | 458925 | 0 | 0 | 10761 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7fa1d1cb0ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65551.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f9a5f924ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 18078 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 416.0 | 32768.0 | 4096 | 16384 | 352 | 28633 | 2150 | 0 | 56.0 | 6.0 | 0.0 | 204556.0 | 64 | 0x7ff854d0cec0 | 235728 | 131018 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 29465 | 29465 | 1980828.0 | 1398275.0 | 3488.0 | 200607.0 | 1093079.0 | 0.0 | 1390463.0 | 1092398.0 | 234017 | 139150 | 29465 | 0 | 29465 | 0 | 942880.0 | 503329.0 | 0.0 | 0.0 | 64 | 0x7f6ca7ed0ec0 | 6374 | 0 | 4096 | 6393 | 0 | 4096 | 6379 | 0 | 4096 | 6357 | 0 | 4096 | 6399 | 0 | 4096 | 6418 | 0 | 4096 | 6391 | 0 | 4096 | 6360 | 0 | 4096 | 6365 | 0 | 4096 | 6370 | 0 | 4096 | 6395 | 0 | 4096 | 6379 | 0 | 4096 | 6353 | 0 | 4096 | 6399 | 0 | 4096 | 6420 | 0 | 4096 | 6395 | 0 | 4096 | 6363 | 0 | 4096 | 6356 | 0 | 4096 | 6403 | 0 | 4096 | 6401 | 0 | 4096 | 6386 | 0 | 4096 | 6350 | 0 | 4096 | 6397 | 0 | 4096 | 6587 | 0 | 4096 | 6419 | 0 | 4096 | 6365 | 0 | 4096 | 6360 | 0 | 4096 | 6400 | 0 | 4096 | 6404 | 0 | 4096 | 6387 | 0 | 4096 | 6353 | 0 | 4096 | 6401 | 0 | 4096 | 64 | 0x7f52604a0ec0 | 32768 | 32768 | 0 | 1411551767635712 | 1411551767656192 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f719d074ec0 | 0 | 3635368 | 2844 | 2844 | 0 | 3358869 | 2868 | 2868 | 0 | 4507800 | 2836 | 2836 | 0 | 4427655 | 2872 | 2872 | 0 | 3528702 | 2908 | 2908 | 0 | 4042385 | 2856 | 2856 | 0 | 3222489 | 2848 | 2848 | 0 | 4461160 | 2804 | 2804 | 0 | 3796362 | 2800 | 2800 | 0 | 3636483 | 2848 | 2848 | 0 | 4079095 | 2868 | 2868 | 0 | 4022898 | 2832 | 2832 | 0 | 3688662 | 2872 | 2872 | 0 | 3878807 | 2908 | 2908 | 0 | 3509431 | 2856 | 2856 | 0 | 3142952 | 2850 | 2850 | 0 | 3168535 | 2804 | 2804 | 0 | 3760235 | 2832 | 2832 | 0 | 3390587 | 2860 | 2860 | 0 | 4033999 | 2860 | 2860 | 0 | 3370259 | 2830 | 2830 | 0 | 3976984 | 2878 | 2878 | 0 | 3924020 | 2834 | 2834 | 0 | 4706973 | 2840 | 2840 | 0 | 4308399 | 2840 | 2840 | 0 | 3268498 | 2808 | 2808 | 0 | 3235184 | 2836 | 2836 | 0 | 3606911 | 2860 | 2860 | 0 | 4164092 | 2860 | 2860 | 0 | 3140833 | 2828 | 2828 | 0 | 3982134 | 2872 | 2872 | 0 | 4308084 | 2828 | 2828 | 64 | 0x7f5871864ec0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 0 | 40844 | 0 | 0 | 64 | 0x7f842c814ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 21863 | 0 | 2857 | 39450 | 0 | 70312.0 | 131072.0 | 0.0 | 45621.0 | 64 | 0x7f64e75d8ec0 | 0 | 184431 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f01f2d00ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 116463987.0 | 59127715.0 | 0.0 | 64 | 0x7f6ecb88cec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 1983462.0 | 64 | 0x7fc1d67f8ec0 | 4096 | 0 | 456 | 0 | 4096 | 0 | 291 | 0 | 4096 | 0 | 2176 | 0 | 4096 | 0 | 727 | 0 | 4098 | 0 | 725 | 0 | 4097 | 0 | 1024 | 0 | 4096 | 0 | 71 | 0 | 4096 | 0 | 925 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 332 | 0 | 4096 | 0 | 729 | 0 | 4098 | 0 | 911 | 0 | 4096 | 0 | 185 | 0 | 4096 | 0 | 548 | 0 | 4096 | 0 | 1181 | 0 | 4096 | 0 | 155 | 0 | 4096 | 0 | 771 | 0 | 4096 | 0 | 828 | 0 | 4097 | 0 | 87 | 0 | 4098 | 0 | 541 | 0 | 4096 | 0 | 259 | 0 | 4096 | 0 | 295 | 0 | 4096 | 0 | 1833 | 0 | 4096 | 0 | 1038 | 0 | 4096 | 0 | 1152 | 0 | 4096 | 0 | 752 | 0 | 4097 | 0 | 372 | 0 | 4096 | 0 | 515 | 0 | 4096 | 0 | 66 | 0 | 4096 | 0 | 55 | 0 | 4096 | 0 | 21 | 0 | 4096 | 0 | 932 | 0 | 64 | 0x7feb1c338ec0 | 2167 | 4099 | 2170 | 6266 | 2163 | 4098 | 2165 | 6261 | 2166 | 4096 | 2166 | 6262 | 2131 | 4096 | 2131 | 6227 | 2155 | 4096 | 2155 | 6251 | 2126 | 4096 | 2126 | 6222 | 2198 | 4096 | 2198 | 6294 | 2205 | 4096 | 2205 | 6301 | 2205 | 4096 | 2205 | 6301 | 2167 | 4096 | 2167 | 6263 | 2167 | 4096 | 2167 | 6263 | 2170 | 4096 | 2170 | 6266 | 2131 | 4096 | 2131 | 6227 | 2157 | 4096 | 2157 | 6253 | 2128 | 4096 | 2128 | 6224 | 2200 | 4096 | 2200 | 6296 | 2197 | 4096 | 2197 | 6293 | 2192 | 4096 | 2192 | 6288 | 2191 | 4098 | 2193 | 6289 | 2165 | 4096 | 2165 | 6261 | 2224 | 4098 | 2226 | 6322 | 2159 | 4096 | 2159 | 6255 | 2142 | 4096 | 2142 | 6238 | 2143 | 4096 | 2143 | 6239 | 2141 | 4096 | 2141 | 6237 | 2196 | 4096 | 2196 | 6292 | 2191 | 4096 | 2191 | 6287 | 2194 | 4096 | 2194 | 6290 | 2163 | 4097 | 2164 | 6260 | 2166 | 4096 | 2166 | 6262 | 2156 | 4096 | 2156 | 6252 | 2148 | 4096 | 2148 | 6244 | 64 | 0x7f0c851d0ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 57344038.0 | 201189675.0 | 49212604.0 | 131072.0 | 0.0 | 469527.0 | 0 | 0 | 24792 | 3406.0 | 131086.0 | 0.0 | 26.0 | 64 | 0x7f2a26314ec0 | 0 | 0 | 0 | 1951688 | 0 | 0 | 0 | 2040120 | 1375 | 0 | 0 | 2515290 | 388 | 0 | 0 | 1924121 | 0 | 0 | 0 | 1959773 | 0 | 0 | 0 | 2144087 | 0 | 0 | 0 | 1601755 | 0 | 0 | 0 | 2227649 | 0 | 0 | 0 | 1515823 | 0 | 0 | 0 | 1712370 | 747 | 0 | 0 | 2281309 | 0 | 0 | 0 | 1754410 | 0 | 0 | 0 | 1631638 | 0 | 0 | 0 | 1959634 | 0 | 0 | 0 | 1945745 | 0 | 0 | 0 | 2101434 | 0 | 0 | 0 | 1485087 | 0 | 0 | 0 | 1663642 | 0 | 0 | 0 | 1597442 | 361 | 0 | 0 | 2320340 | 0 | 0 | 0 | 1479920 | 0 | 0 | 0 | 1769753 | 0 | 0 | 0 | 1643637 | 0 | 0 | 0 | 2016612 | 0 | 0 | 0 | 1590062 | 0 | 0 | 0 | 1353961 | 0 | 0 | 0 | 1457530 | 0 | 0 | 0 | 1782668 | 1 | 0 | 0 | 1962887 | 0 | 0 | 0 | 1575942 | 0 | 0 | 0 | 1874338 | 0 | 0 | 0 | 2035352 | 64 | 0x7f980b700ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131072.0 | 92644.0 | 45484.0 | 0.0 | 64 | 0x7f9e9e168ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 32251 | 27914 | 9640 | 2417 | 0 | 39435 | 200735.0 | 0.0 | 69652.0 | 131083.0 | 64 | 0x7f80e4520ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fbd96bb4ec0 | 19460332 | 18326981 | 789287 | 344064 | 2808219 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 662213.0 | 32768.0 | 1020891 | 0 | 0 | 13732 | 91072.0 | 91072.0 | 0.0 | 91072.0 | 64 | 0x7fa1d1cb0ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65550.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f9a5f924ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29953 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 211.0 | 32768.0 | 4096 | 16384 | 302 | 41182 | 2074 | 0 | 56.0 | 11.0 | 0.0 | 200382.0 | 64 | 0x7ff854d0cec0 | 332936 | 217335 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 41616 | 41616 | 3122366.0 | 2426905.0 | 4865.0 | 361077.0 | 1765505.0 | 0.0 | 2413768.0 | 2104530.0 | 332928 | 227334 | 41616 | 0 | 41616 | 0 | 1331712.0 | 770089.0 | 0.0 | 0.0 | 64 | 0x7f6ca7ed0ec0 | 6275 | 0 | 4096 | 6265 | 0 | 4096 | 6270 | 0 | 4096 | 6315 | 0 | 4096 | 6256 | 0 | 4096 | 6282 | 0 | 4096 | 6280 | 0 | 4096 | 6295 | 0 | 4096 | 6297 | 0 | 4096 | 6284 | 0 | 4096 | 6266 | 0 | 4096 | 6267 | 0 | 4096 | 6316 | 0 | 4096 | 6258 | 0 | 4096 | 6284 | 0 | 4096 | 6278 | 0 | 4096 | 6276 | 0 | 4096 | 6303 | 0 | 4096 | 6319 | 0 | 4096 | 6272 | 0 | 4096 | 6287 | 0 | 4096 | 6292 | 0 | 4096 | 6259 | 0 | 4096 | 6244 | 0 | 4096 | 6247 | 0 | 4096 | 6279 | 0 | 4096 | 6308 | 0 | 4096 | 6325 | 0 | 4096 | 6270 | 0 | 4096 | 6288 | 0 | 4096 | 6301 | 0 | 4096 | 6264 | 0 | 4096 | 64 | 0x7f52604a0ec0 | 32768 | 32768 | 0 | 1411551767749472 | 1411551767765792 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7f719d074ec0 | 0 | 4893434 | 2842 | 2842 | 0 | 3008209 | 2884 | 2884 | 0 | 3693531 | 2840 | 2840 | 0 | 4755946 | 2844 | 2844 | 0 | 3066626 | 2916 | 2916 | 0 | 3804873 | 2868 | 2868 | 0 | 3252142 | 2864 | 2864 | 0 | 4476300 | 2820 | 2820 | 0 | 2954350 | 2820 | 2820 | 0 | 4062496 | 2840 | 2840 | 0 | 3474505 | 2880 | 2880 | 0 | 3357615 | 2840 | 2840 | 0 | 4920610 | 2840 | 2840 | 0 | 3165935 | 2920 | 2920 | 0 | 3358292 | 2868 | 2868 | 0 | 3102609 | 2864 | 2864 | 0 | 3416702 | 2784 | 2784 | 0 | 3889266 | 2832 | 2832 | 0 | 3431023 | 2872 | 2872 | 0 | 3536202 | 2872 | 2872 | 0 | 3319281 | 2848 | 2848 | 0 | 3611600 | 2872 | 2872 | 0 | 4564855 | 2852 | 2852 | 0 | 3948416 | 2848 | 2848 | 0 | 4021456 | 2846 | 2846 | 0 | 3292413 | 2784 | 2784 | 0 | 2882639 | 2832 | 2832 | 0 | 3946100 | 2860 | 2860 | 0 | 3749723 | 2872 | 2872 | 0 | 2710590 | 2848 | 2848 | 0 | 3573893 | 2872 | 2872 | 0 | 4205309 | 2860 | 2860 | 64 | 0x7f5871864ec0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 0 | 40789 | 0 | 0 | 64 | 0x7f842c814ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 20454 | 0 | 2734 | 38217 | 0 | 70013.0 | 131072.0 | 0.0 | 45741.0 | 64 | 0x7f64e75d8ec0 | 0 | 182947 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7f01f2d00ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 119691070.0 | 60044646.0 | 0.0 | 64 | 0x7f6ecb88cec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2007495.0 | 64 | 0x7fc1d67f8ec0 | 4096 | 0 | 1430 | 0 | 4096 | 0 | 786 | 0 | 4096 | 0 | 706 | 0 | 4096 | 0 | 110 | 0 | 4098 | 0 | 877 | 0 | 4097 | 0 | 422 | 0 | 4096 | 0 | 723 | 0 | 4096 | 0 | 701 | 0 | 4096 | 0 | 605 | 0 | 4096 | 0 | 935 | 0 | 4096 | 0 | 516 | 0 | 4098 | 0 | 596 | 0 | 4096 | 0 | 203 | 0 | 4096 | 0 | 464 | 0 | 4096 | 0 | 1484 | 0 | 4096 | 0 | 281 | 0 | 4096 | 0 | 593 | 0 | 4096 | 0 | 646 | 0 | 4097 | 0 | 208 | 0 | 4098 | 0 | 1107 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 460 | 0 | 4096 | 0 | 440 | 0 | 4096 | 0 | 744 | 0 | 4096 | 0 | 2052 | 0 | 4096 | 0 | 322 | 0 | 4097 | 0 | 568 | 0 | 4096 | 0 | 659 | 0 | 4096 | 0 | 431 | 0 | 4096 | 0 | 719 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 767 | 0 | 64 | 0x7feb1c338ec0 | 2191 | 4099 | 2194 | 6290 | 2198 | 4098 | 2200 | 6296 | 2227 | 4096 | 2227 | 6323 | 2207 | 4096 | 2207 | 6303 | 2195 | 4096 | 2195 | 6291 | 2175 | 4096 | 2175 | 6271 | 2169 | 4096 | 2169 | 6265 | 2181 | 4096 | 2181 | 6277 | 2183 | 4096 | 2183 | 6279 | 2196 | 4096 | 2196 | 6292 | 2203 | 4096 | 2203 | 6299 | 2229 | 4096 | 2229 | 6325 | 2209 | 4096 | 2209 | 6305 | 2198 | 4096 | 2198 | 6294 | 2174 | 4096 | 2174 | 6270 | 2168 | 4096 | 2168 | 6264 | 2192 | 4096 | 2192 | 6288 | 2193 | 4096 | 2193 | 6289 | 2166 | 4098 | 2168 | 6264 | 2187 | 4096 | 2187 | 6283 | 2250 | 4098 | 2252 | 6348 | 2209 | 4096 | 2209 | 6305 | 2185 | 4096 | 2185 | 6281 | 2197 | 4096 | 2197 | 6293 | 2195 | 4096 | 2195 | 6291 | 2192 | 4096 | 2192 | 6288 | 2191 | 4096 | 2191 | 6287 | 2169 | 4096 | 2169 | 6265 | 2189 | 4097 | 2190 | 6286 | 2201 | 4096 | 2201 | 6297 | 2210 | 4096 | 2210 | 6306 | 2187 | 4096 | 2187 | 6283 | 64 | 0x7f0c851d0ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 57372751.0 | 203209514.0 | 46896816.0 | 131072.0 | 0.0 | 520441.0 | 0 | 0 | 24918 | 6541.0 | 131087.0 | 0.0 | 28.0 | 64 | 0x7f2a26314ec0 | 0 | 0 | 0 | 1925466 | 4 | 0 | 0 | 1901532 | 0 | 0 | 0 | 1769391 | 78 | 0 | 0 | 2063862 | 49 | 0 | 0 | 1996144 | 1302 | 0 | 0 | 2244795 | 0 | 0 | 0 | 1567085 | 69 | 0 | 0 | 1956879 | 1 | 0 | 0 | 1666303 | 0 | 0 | 0 | 1671082 | 0 | 0 | 0 | 1509605 | 0 | 0 | 0 | 1696856 | 1076 | 0 | 0 | 2560896 | 0 | 0 | 0 | 1888969 | 724 | 0 | 0 | 2078267 | 0 | 0 | 0 | 1859150 | 0 | 0 | 0 | 1746326 | 0 | 0 | 0 | 1616154 | 0 | 0 | 0 | 1541765 | 0 | 0 | 0 | 1842461 | 0 | 0 | 0 | 1516028 | 108 | 0 | 0 | 2160627 | 7 | 0 | 0 | 1691966 | 0 | 0 | 0 | 1716188 | 0 | 0 | 0 | 1637841 | 0 | 0 | 0 | 1746015 | 0 | 0 | 0 | 1918312 | 0 | 0 | 0 | 1645271 | 0 | 0 | 0 | 1677917 | 0 | 0 | 0 | 1485077 | 0 | 0 | 0 | 1510985 | 0 | 0 | 0 | 1731264 | 64 | 0x7f980b700ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131081.0 | 99736.0 | 45511.0 | 0.0 | 64 | 0x7f9e9e168ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 32796 | 28321 | 9652 | 2427 | 0 | 39845 | 201111.0 | 0.0 | 70029.0 | 131082.0 | 64 | 0x7f80e4520ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7fbd96bb4ec0 | 18674882 | 17567758 | 763060 | 344064 | 2706223 | 0 | 0 | 163840 | 832.0 | 515148.0 | 0.0 | 524288.0 | 630567.0 | 32768.0 | 915443 | 0 | 0 | 13879 | 91113.0 | 91113.0 | 0.0 | 91113.0 | 64 | 0x7fa1d1cb0ec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65552.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7f9a5f924ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 30614 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 207.0 | 32768.0 | 4096 | 16384 | 302 | 41805 | 1941 | 0 | 56.0 | 11.0 | 0.0 | 200333.0 | 64 | 0x7ff854d0cec0 | 332832 | 226984 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 41603 | 41603 | 3227887.0 | 2522631.0 | 4209.0 | 383730.0 | 1781211.0 | 0.0 | 2511870.0 | 2205061.0 | 332824 | 236399 | 41603 | 0 | 41603 | 0 | 1331296.0 | 778074.0 | 0.0 | 0.0 | 64 | 0x7f6ca7ed0ec0 | 6283 | 0 | 4096 | 6303 | 0 | 4096 | 6273 | 0 | 4096 | 6293 | 0 | 4096 | 6279 | 0 | 4096 | 6274 | 0 | 4096 | 6280 | 0 | 4096 | 6297 | 0 | 4096 | 6295 | 0 | 4096 | 6287 | 0 | 4096 | 6307 | 0 | 4096 | 6278 | 0 | 4096 | 6299 | 0 | 4096 | 6280 | 0 | 4096 | 6279 | 0 | 4096 | 6277 | 0 | 4096 | 6285 | 0 | 4096 | 6283 | 0 | 4096 | 6281 | 0 | 4096 | 6284 | 0 | 4096 | 6295 | 0 | 4096 | 6306 | 0 | 4096 | 6263 | 0 | 4096 | 6303 | 0 | 4096 | 6306 | 0 | 4096 | 6283 | 0 | 4096 | 6280 | 0 | 4096 | 6277 | 0 | 4096 | 6283 | 0 | 4096 | 6298 | 0 | 4096 | 6311 | 0 | 4096 | 6267 | 0 | 4096 | 64 | 0x7f52604a0ec0 | 32768 | 32768 | 0 | 1411551767786592 | 1411551767802112 |