vedithal-amd
27585a8a2b
* Add MI 350 hardware information
* Refactor MI GPU YAML file and corresponding interface
* Add SoC file for gfx950 architecture
* Add analysis report configs for MI 350 containing existing metrics
* Add placeholder None valued metrics for previous architectures to make
baseline comparison work
* Enable testing on MI 350
* Analysis config metric changes
- SPI changes
- Update metric formula for default SPI pipe counter
- Use efficiently collected pipe wise SPI counters
- Add SPI Wave Occupancy
- Add Scheduler-Pipe Wave Utilization
- Update formula for VGPR Writes
- Add Scheduler-Pipe FIFO Full Rate
- CPC changes
- Add CPC SYNC FIFO Full Rate
- Add CPC CANE Stall Rate
- Add CPC ADC Utilization
- SQ changes
- Add VALU co-issue efficiency
- Add F6F4 datatype metrics
- Update formula for total FLOPs by adding F6F4 counters
- Add LDS STORE / LOAD / ATOMIC metrics
- Add LDS STORE / LOAD / ATOMIC bandwidth
- Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates
* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)
* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily
* Do not hardcode memory and shader clock speeds
* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling
* Move generate sysinfo.csv to pre processing step of profiling
* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase
* Update CHANGELOG
* Analysis phase warning to use --specs-correction when needed
[ROCm/rocprofiler-compute commit: f9aa7be97c]
38 KiB
38 KiB
| 1 | Dispatch_ID | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | Wave_Size | Kernel_Name | Correlation_ID | Kernel_ID | CPC_CANE_BUSY | CPC_GD_BUSY | SPI_RA_REQ_NO_ALLOC | SPI_SWC_CSC_WR | SQC_DCACHE_REQ_READ_4 | SQC_TC_DATA_READ_REQ | SQ_INSTS_VALU_INT64 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_F6F4 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VMEM | SQ_VALU_MFMA_BUSY_CYCLES | TA_BUFFER_READ_WAVEFRONTS_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TCC_CC_REQ_sum | TCC_EA0_RDREQ_LEVEL_sum | TCC_EA0_RD_UNCACHED_32B_sum | TCC_RW_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCP_TCC_NC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TCP_UTCL1_PERMISSION_MISS_sum | Kernel_ID_1 | CPC_CPC_UTCL2IU_BUSY | CPC_SYNC_FIFO_FULL | SPI_CS0_NUM_THREADGROUPS | SPI_CS1_NUM_THREADGROUPS | SPI_CS2_NUM_THREADGROUPS | SPI_CS3_NUM_THREADGROUPS | SQC_DCACHE_REQ_READ_8 | SQC_TC_DATA_ATOMIC_REQ | SQ_ACTIVE_INST_VALU | SQ_BUSY_CYCLES | SQ_INSTS_SENDMSG | SQ_INSTS_VALU_ADD_F64 | SQ_LDS_BANK_CONFLICT | SQ_VMEM_TA_CMD_FIFO_FULL | TA_BUFFER_WAVEFRONTS_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_EA0_WRREQ_LEVEL_sum | TCC_UC_REQ_sum | TCP_TCC_READ_REQ_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | Kernel_ID_2 | SPI_RA_LDS_CU_FULL_CSN | SPI_RA_TMP_STALL_CSN | SQC_DCACHE_REQ_READ_1 | SQC_ICACHE_HITS | SQ_INSTS_LDS_ATOMIC_BANDWIDTH | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_F6F4 | SQ_INSTS_VALU_MUL_F32 | SQ_LDS_ADDR_CONFLICT | SQ_WAIT_INST_ANY | TCC_EA0_RDREQ_32B_sum | TCC_EA0_RDREQ_sum | TCC_STREAMING_REQ_sum | TCC_WRITE_sum | Kernel_ID_3 | SQC_DCACHE_REQ | SQ_ACTIVE_INST_FLAT | SQ_ACTIVE_INST_SCA | SQ_IFETCH | SQ_INSTS | SQ_INSTS_SALU | SQ_INSTS_VALU_ADD_F32 | SQ_INSTS_VALU_MFMA_F32 | Kernel_ID_4 | SPI_RA_VGPR_SIMD_FULL_CSN | SPI_VWC1_VDATA_VALID_WR | SQC_DCACHE_REQ_READ_2 | SQ_ACTIVE_INST_ANY | SQ_ACTIVE_INST_MISC | SQ_INSTS_BRANCH | SQ_INSTS_LDS_STORE_BANDWIDTH | SQ_INSTS_VALU_CVT | SQ_LDS_ATOMIC_RETURN | SQ_LDS_MEM_VIOLATIONS | TCC_MISS_sum | TCC_PROBE_sum | TCC_REQ_sum | TCC_WRITEBACK_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_READ_sum | Kernel_ID_5 | CPC_CPC_UTCL2IU_IDLE | CPC_UTCL1_STALL_ON_TRANSLATION | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_RES_STALL_CSN | SQC_DCACHE_MISSES_DUPLICATE | SQ_INSTS_SMEM | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_INT32 | SQ_INSTS_VALU_MFMA_F8 | SQ_INSTS_VALU_MFMA_MOPS_F8 | SQ_INSTS_VALU_TRANS_F32 | SQ_THREAD_CYCLES_VALU | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | TCC_BUSY_sum | TCC_HIT_sum | TCC_NORMAL_WRITEBACK_sum | TCC_READ_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TCC_CC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_WRITE_REQ_sum | Kernel_ID_6 | SPI_RA_TGLIM_CU_FULL_CSN | SPI_RA_WVLIM_STALL_CSN | SQC_TC_INST_REQ | SQ_INSTS_VALU | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQ_INSTS_VALU_TRANS_F16 | SQ_LDS_UNALIGNED_STALL | SQ_WAIT_ANY | TCC_EA0_WR_UNCACHED_32B_sum | TCC_NORMAL_EVICT_sum | Kernel_ID_7 | SPI_CSC_WAVE_CNT_BUSY | SPI_RA_WAVE_SIMD_FULL_CSN | SQC_TC_DATA_WRITE_REQ | SQ_ACTIVE_INST_LDS | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F64 | SQ_LDS_DATA_FIFO_FULL | SQ_VMEM_TA_ADDR_FIFO_FULL | SQ_WAVES | SQ_WAVES_RESTORED | TCC_EA0_ATOMIC_sum | TCC_EA0_RDREQ_DRAM_sum | TCC_EA0_WRREQ_64B_sum | TCC_EA0_WRREQ_DRAM_sum | Kernel_ID_8 | CPC_CPC_TCIU_BUSY | CPC_ME1_DC0_SPI_BUSY | SPI_RA_REQ_NO_ALLOC_CSN | SPI_VWC0_VDATA_VALID_WR | SQC_DCACHE_ATOMIC | SQC_DCACHE_MISSES | SQC_ICACHE_REQ | SQC_TC_STALL | SQ_INSTS_VALU_MUL_F16 | SQ_INST_LEVEL_LDS | SQ_WAVES_SAVED | TA_BUFFER_WRITE_WAVEFRONTS_sum | TA_TA_BUSY_sum | TCC_ATOMIC_sum | TCC_EA0_ATOMIC_LEVEL_sum | TCC_EA0_WRREQ_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_UTCL1_REQUEST_sum | Kernel_ID_9 | CPC_CPC_TCIU_IDLE | CPC_TG_SEND | CPF_CPF_TCIU_IDLE | SPI_CS0_BUSY | SPI_CS1_BUSY | SPI_CS2_BUSY | SPI_CS3_BUSY | SQ_INSTS_LDS | SQ_INSTS_LDS_LOAD_BANDWIDTH | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_LDS_IDX_ACTIVE | SQ_LEVEL_WAVES | SQ_WAVE_CYCLES | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | TCC_BUBBLE_sum | TCC_EA0_ATOMIC_LEVEL[0] | TCC_EA0_ATOMIC_LEVEL[11] | TCC_EA0_ATOMIC_LEVEL[12] | TCC_EA0_ATOMIC_LEVEL[13] | TCC_EA0_ATOMIC_LEVEL[14] | TCC_EA0_ATOMIC_LEVEL[16] | TCC_EA0_ATOMIC_LEVEL[17] | TCC_EA0_ATOMIC_LEVEL[18] | TCC_EA0_ATOMIC_LEVEL[19] | TCC_EA0_ATOMIC_LEVEL[1] | TCC_EA0_ATOMIC_LEVEL[22] | TCC_EA0_ATOMIC_LEVEL[23] | TCC_EA0_ATOMIC_LEVEL[24] | TCC_EA0_ATOMIC_LEVEL[25] | TCC_EA0_ATOMIC_LEVEL[27] | TCC_EA0_ATOMIC_LEVEL[28] | TCC_EA0_ATOMIC_LEVEL[29] | TCC_EA0_ATOMIC_LEVEL[2] | TCC_EA0_ATOMIC_LEVEL[30] | TCC_EA0_ATOMIC_LEVEL[32] | TCC_EA0_ATOMIC_LEVEL[33] | TCC_EA0_ATOMIC_LEVEL[34] | TCC_EA0_ATOMIC_LEVEL[35] | TCC_EA0_ATOMIC_LEVEL[37] | TCC_EA0_ATOMIC_LEVEL[38] | TCC_EA0_ATOMIC_LEVEL[39] | TCC_EA0_ATOMIC_LEVEL[3] | TCC_EA0_ATOMIC_LEVEL[40] | TCC_EA0_ATOMIC_LEVEL[43] | TCC_EA0_ATOMIC_LEVEL[44] | TCC_EA0_ATOMIC_LEVEL[45] | TCC_EA0_ATOMIC_LEVEL[46] | TCC_EA0_ATOMIC_LEVEL[48] | TCC_EA0_ATOMIC_LEVEL[49] | TCC_EA0_ATOMIC_LEVEL[4] | TCC_EA0_ATOMIC_LEVEL[50] | TCC_EA0_ATOMIC_LEVEL[51] | TCC_EA0_ATOMIC_LEVEL[53] | TCC_EA0_ATOMIC_LEVEL[54] | TCC_EA0_ATOMIC_LEVEL[55] | TCC_EA0_ATOMIC_LEVEL[56] | TCC_EA0_ATOMIC_LEVEL[58] | TCC_EA0_ATOMIC_LEVEL[59] | TCC_EA0_ATOMIC_LEVEL[60] | TCC_EA0_ATOMIC_LEVEL[61] | TCC_EA0_ATOMIC_LEVEL[6] | TCC_EA0_ATOMIC_LEVEL[7] | TCC_EA0_ATOMIC_LEVEL[8] | TCC_EA0_ATOMIC_LEVEL[9] | TCC_EA0_RDREQ_LEVEL[0] | TCC_EA0_RDREQ_LEVEL[11] | TCC_EA0_RDREQ_LEVEL[12] | TCC_EA0_RDREQ_LEVEL[13] | TCC_EA0_RDREQ_LEVEL[14] | TCC_EA0_RDREQ_LEVEL[16] | TCC_EA0_RDREQ_LEVEL[17] | TCC_EA0_RDREQ_LEVEL[18] | TCC_EA0_RDREQ_LEVEL[19] | TCC_EA0_RDREQ_LEVEL[1] | TCC_EA0_RDREQ_LEVEL[22] | TCC_EA0_RDREQ_LEVEL[23] | TCC_EA0_RDREQ_LEVEL[24] | TCC_EA0_RDREQ_LEVEL[25] | TCC_EA0_RDREQ_LEVEL[27] | TCC_EA0_RDREQ_LEVEL[28] | TCC_EA0_RDREQ_LEVEL[29] | TCC_EA0_RDREQ_LEVEL[2] | TCC_EA0_RDREQ_LEVEL[30] | TCC_EA0_RDREQ_LEVEL[32] | TCC_EA0_RDREQ_LEVEL[33] | TCC_EA0_RDREQ_LEVEL[34] | TCC_EA0_RDREQ_LEVEL[35] | TCC_EA0_RDREQ_LEVEL[37] | TCC_EA0_RDREQ_LEVEL[38] | TCC_EA0_RDREQ_LEVEL[39] | TCC_EA0_RDREQ_LEVEL[3] | TCC_EA0_RDREQ_LEVEL[40] | TCC_EA0_RDREQ_LEVEL[43] | TCC_EA0_RDREQ_LEVEL[44] | TCC_EA0_RDREQ_LEVEL[45] | TCC_EA0_RDREQ_LEVEL[46] | TCC_EA0_RDREQ_LEVEL[48] | TCC_EA0_RDREQ_LEVEL[49] | TCC_EA0_RDREQ_LEVEL[4] | TCC_EA0_RDREQ_LEVEL[50] | TCC_EA0_RDREQ_LEVEL[51] | TCC_EA0_RDREQ_LEVEL[53] | TCC_EA0_RDREQ_LEVEL[54] | TCC_EA0_RDREQ_LEVEL[55] | TCC_EA0_RDREQ_LEVEL[56] | TCC_EA0_RDREQ_LEVEL[58] | TCC_EA0_RDREQ_LEVEL[59] | TCC_EA0_RDREQ_LEVEL[60] | TCC_EA0_RDREQ_LEVEL[61] | TCC_EA0_RDREQ_LEVEL[6] | TCC_EA0_RDREQ_LEVEL[7] | TCC_EA0_RDREQ_LEVEL[8] | TCC_EA0_RDREQ_LEVEL[9] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_TOO_MANY_EA_WRREQS_STALL[32] | TCC_TOO_MANY_EA_WRREQS_STALL[33] | TCC_TOO_MANY_EA_WRREQS_STALL[34] | TCC_TOO_MANY_EA_WRREQS_STALL[35] | TCC_TOO_MANY_EA_WRREQS_STALL[37] | TCC_TOO_MANY_EA_WRREQS_STALL[38] | TCC_TOO_MANY_EA_WRREQS_STALL[39] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_TOO_MANY_EA_WRREQS_STALL[40] | TCC_TOO_MANY_EA_WRREQS_STALL[43] | TCC_TOO_MANY_EA_WRREQS_STALL[44] | TCC_TOO_MANY_EA_WRREQS_STALL[45] | TCC_TOO_MANY_EA_WRREQS_STALL[46] | TCC_TOO_MANY_EA_WRREQS_STALL[48] | TCC_TOO_MANY_EA_WRREQS_STALL[49] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_TOO_MANY_EA_WRREQS_STALL[50] | TCC_TOO_MANY_EA_WRREQS_STALL[51] | TCC_TOO_MANY_EA_WRREQS_STALL[53] | TCC_TOO_MANY_EA_WRREQS_STALL[54] | TCC_TOO_MANY_EA_WRREQS_STALL[55] | TCC_TOO_MANY_EA_WRREQS_STALL[56] | TCC_TOO_MANY_EA_WRREQS_STALL[58] | TCC_TOO_MANY_EA_WRREQS_STALL[59] | TCC_TOO_MANY_EA_WRREQS_STALL[60] | TCC_TOO_MANY_EA_WRREQS_STALL[61] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCP_GATE_EN2_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TD_TD_BUSY_sum | Kernel_ID_10 | CPC_ME1_BUSY_FOR_PACKET_DECODE | CPC_SYNC_WRREQ_FIFO_BUSY | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_BUSY | GRBM_GUI_ACTIVE | SPI_CS0_WAVE | SPI_CS1_WAVE | SPI_CS2_WAVE | SPI_CS3_WAVE | SQC_DCACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | SQ_IFETCH_LEVEL | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_VMEM_WR_TA_DATA_FIFO_FULL | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_FLAT_WAVEFRONTS_sum | TCC_EA0_RDREQ[0] | TCC_EA0_RDREQ[10] | TCC_EA0_RDREQ[11] | TCC_EA0_RDREQ[12] | TCC_EA0_RDREQ[13] | TCC_EA0_RDREQ[14] | TCC_EA0_RDREQ[15] | TCC_EA0_RDREQ[16] | TCC_EA0_RDREQ[17] | TCC_EA0_RDREQ[18] | TCC_EA0_RDREQ[19] | TCC_EA0_RDREQ[1] | TCC_EA0_RDREQ[20] | TCC_EA0_RDREQ[21] | TCC_EA0_RDREQ[22] | TCC_EA0_RDREQ[23] | TCC_EA0_RDREQ[25] | TCC_EA0_RDREQ[26] | TCC_EA0_RDREQ[27] | TCC_EA0_RDREQ[28] | TCC_EA0_RDREQ[29] | TCC_EA0_RDREQ[2] | TCC_EA0_RDREQ[30] | TCC_EA0_RDREQ[31] | TCC_EA0_RDREQ[32] | TCC_EA0_RDREQ[33] | TCC_EA0_RDREQ[34] | TCC_EA0_RDREQ[35] | TCC_EA0_RDREQ[36] | TCC_EA0_RDREQ[37] | TCC_EA0_RDREQ[38] | TCC_EA0_RDREQ[39] | TCC_EA0_RDREQ[3] | TCC_EA0_RDREQ[40] | TCC_EA0_RDREQ[41] | TCC_EA0_RDREQ[42] | TCC_EA0_RDREQ[43] | TCC_EA0_RDREQ[45] | TCC_EA0_RDREQ[46] | TCC_EA0_RDREQ[47] | TCC_EA0_RDREQ[48] | TCC_EA0_RDREQ[49] | TCC_EA0_RDREQ[50] | TCC_EA0_RDREQ[51] | TCC_EA0_RDREQ[52] | TCC_EA0_RDREQ[53] | TCC_EA0_RDREQ[54] | TCC_EA0_RDREQ[55] | TCC_EA0_RDREQ[56] | TCC_EA0_RDREQ[57] | TCC_EA0_RDREQ[58] | TCC_EA0_RDREQ[59] | TCC_EA0_RDREQ[5] | TCC_EA0_RDREQ[60] | TCC_EA0_RDREQ[61] | TCC_EA0_RDREQ[62] | TCC_EA0_RDREQ[63] | TCC_EA0_RDREQ[6] | TCC_EA0_RDREQ[7] | TCC_EA0_RDREQ[8] | TCC_EA0_RDREQ[9] | TCC_EA0_WRREQ_LEVEL[0] | TCC_EA0_WRREQ_LEVEL[10] | TCC_EA0_WRREQ_LEVEL[11] | TCC_EA0_WRREQ_LEVEL[12] | TCC_EA0_WRREQ_LEVEL[13] | TCC_EA0_WRREQ_LEVEL[14] | TCC_EA0_WRREQ_LEVEL[15] | TCC_EA0_WRREQ_LEVEL[16] | TCC_EA0_WRREQ_LEVEL[17] | TCC_EA0_WRREQ_LEVEL[18] | TCC_EA0_WRREQ_LEVEL[19] | TCC_EA0_WRREQ_LEVEL[1] | TCC_EA0_WRREQ_LEVEL[20] | TCC_EA0_WRREQ_LEVEL[21] | TCC_EA0_WRREQ_LEVEL[22] | TCC_EA0_WRREQ_LEVEL[23] | TCC_EA0_WRREQ_LEVEL[25] | TCC_EA0_WRREQ_LEVEL[26] | TCC_EA0_WRREQ_LEVEL[27] | TCC_EA0_WRREQ_LEVEL[28] | TCC_EA0_WRREQ_LEVEL[29] | TCC_EA0_WRREQ_LEVEL[2] | TCC_EA0_WRREQ_LEVEL[30] | TCC_EA0_WRREQ_LEVEL[31] | TCC_EA0_WRREQ_LEVEL[32] | TCC_EA0_WRREQ_LEVEL[33] | TCC_EA0_WRREQ_LEVEL[34] | TCC_EA0_WRREQ_LEVEL[35] | TCC_EA0_WRREQ_LEVEL[36] | TCC_EA0_WRREQ_LEVEL[37] | TCC_EA0_WRREQ_LEVEL[38] | TCC_EA0_WRREQ_LEVEL[39] | TCC_EA0_WRREQ_LEVEL[3] | TCC_EA0_WRREQ_LEVEL[40] | TCC_EA0_WRREQ_LEVEL[41] | TCC_EA0_WRREQ_LEVEL[42] | TCC_EA0_WRREQ_LEVEL[43] | TCC_EA0_WRREQ_LEVEL[45] | TCC_EA0_WRREQ_LEVEL[46] | TCC_EA0_WRREQ_LEVEL[47] | TCC_EA0_WRREQ_LEVEL[48] | TCC_EA0_WRREQ_LEVEL[49] | TCC_EA0_WRREQ_LEVEL[50] | TCC_EA0_WRREQ_LEVEL[51] | TCC_EA0_WRREQ_LEVEL[52] | TCC_EA0_WRREQ_LEVEL[53] | TCC_EA0_WRREQ_LEVEL[54] | TCC_EA0_WRREQ_LEVEL[55] | TCC_EA0_WRREQ_LEVEL[56] | TCC_EA0_WRREQ_LEVEL[57] | TCC_EA0_WRREQ_LEVEL[58] | TCC_EA0_WRREQ_LEVEL[59] | TCC_EA0_WRREQ_LEVEL[5] | TCC_EA0_WRREQ_LEVEL[60] | TCC_EA0_WRREQ_LEVEL[61] | TCC_EA0_WRREQ_LEVEL[62] | TCC_EA0_WRREQ_LEVEL[63] | TCC_EA0_WRREQ_LEVEL[6] | TCC_EA0_WRREQ_LEVEL[7] | TCC_EA0_WRREQ_LEVEL[8] | TCC_EA0_WRREQ_LEVEL[9] | TCC_NC_REQ_sum | TCC_REQ[0] | TCC_REQ[10] | TCC_REQ[11] | TCC_REQ[12] | TCC_REQ[13] | TCC_REQ[14] | TCC_REQ[15] | TCC_REQ[16] | TCC_REQ[17] | TCC_REQ[18] | TCC_REQ[19] | TCC_REQ[1] | TCC_REQ[20] | TCC_REQ[21] | TCC_REQ[22] | TCC_REQ[23] | TCC_REQ[25] | TCC_REQ[26] | TCC_REQ[27] | TCC_REQ[28] | TCC_REQ[29] | TCC_REQ[2] | TCC_REQ[30] | TCC_REQ[31] | TCC_REQ[32] | TCC_REQ[33] | TCC_REQ[34] | TCC_REQ[35] | TCC_REQ[36] | TCC_REQ[37] | TCC_REQ[38] | TCC_REQ[39] | TCC_REQ[3] | TCC_REQ[40] | TCC_REQ[41] | TCC_REQ[42] | TCC_REQ[43] | TCC_REQ[45] | TCC_REQ[46] | TCC_REQ[47] | TCC_REQ[48] | TCC_REQ[49] | TCC_REQ[50] | TCC_REQ[51] | TCC_REQ[52] | TCC_REQ[53] | TCC_REQ[54] | TCC_REQ[55] | TCC_REQ[56] | TCC_REQ[57] | TCC_REQ[58] | TCC_REQ[59] | TCC_REQ[5] | TCC_REQ[60] | TCC_REQ[61] | TCC_REQ[62] | TCC_REQ[63] | TCC_REQ[6] | TCC_REQ[7] | TCC_REQ[8] | TCC_REQ[9] | TCP_GATE_EN1_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_TOTAL_WRITE_sum | TD_ATOMIC_WAVEFRONT_sum | TD_TC_STALL_sum | Kernel_ID_11 | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_IDLE | CPF_CPF_STAT_STALL | SPI_CSQ_P0_OCCUPANCY | SPI_CSQ_P1_OCCUPANCY | SPI_CSQ_P2_OCCUPANCY | SPI_CSQ_P3_OCCUPANCY | SPI_RA_SGPR_SIMD_FULL_CSN | SQC_DCACHE_REQ_READ_16 | SQ_BUSY_CU_CYCLES | SQ_INSTS_LDS_LOAD | SQ_INSTS_LDS_STORE | SQ_INSTS_VALU_MUL_F64 | SQ_INST_LEVEL_SMEM | SQ_LDS_CMD_FIFO_FULL | TA_BUFFER_TOTAL_CYCLES_sum | TA_FLAT_READ_WAVEFRONTS_sum | TCC_ATOMIC[0] | TCC_ATOMIC[10] | TCC_ATOMIC[11] | TCC_ATOMIC[12] | TCC_ATOMIC[13] | TCC_ATOMIC[15] | TCC_ATOMIC[16] | TCC_ATOMIC[17] | TCC_ATOMIC[18] | TCC_ATOMIC[19] | TCC_ATOMIC[1] | TCC_ATOMIC[21] | TCC_ATOMIC[22] | TCC_ATOMIC[23] | TCC_ATOMIC[24] | TCC_ATOMIC[26] | TCC_ATOMIC[27] | TCC_ATOMIC[28] | TCC_ATOMIC[29] | TCC_ATOMIC[2] | TCC_ATOMIC[31] | TCC_ATOMIC[32] | TCC_ATOMIC[33] | TCC_ATOMIC[34] | TCC_ATOMIC[35] | TCC_ATOMIC[37] | TCC_ATOMIC[38] | TCC_ATOMIC[39] | TCC_ATOMIC[3] | TCC_ATOMIC[40] | TCC_ATOMIC[42] | TCC_ATOMIC[43] | TCC_ATOMIC[44] | TCC_ATOMIC[45] | TCC_ATOMIC[47] | TCC_ATOMIC[48] | TCC_ATOMIC[49] | TCC_ATOMIC[50] | TCC_ATOMIC[51] | TCC_ATOMIC[53] | TCC_ATOMIC[54] | TCC_ATOMIC[55] | TCC_ATOMIC[56] | TCC_ATOMIC[58] | TCC_ATOMIC[59] | TCC_ATOMIC[5] | TCC_ATOMIC[60] | TCC_ATOMIC[61] | TCC_ATOMIC[63] | TCC_ATOMIC[6] | TCC_ATOMIC[7] | TCC_ATOMIC[8] | TCC_BUBBLE[0] | TCC_BUBBLE[10] | TCC_BUBBLE[11] | TCC_BUBBLE[12] | TCC_BUBBLE[13] | TCC_BUBBLE[15] | TCC_BUBBLE[16] | TCC_BUBBLE[17] | TCC_BUBBLE[18] | TCC_BUBBLE[19] | TCC_BUBBLE[1] | TCC_BUBBLE[21] | TCC_BUBBLE[22] | TCC_BUBBLE[23] | TCC_BUBBLE[24] | TCC_BUBBLE[26] | TCC_BUBBLE[27] | TCC_BUBBLE[28] | TCC_BUBBLE[29] | TCC_BUBBLE[2] | TCC_BUBBLE[31] | TCC_BUBBLE[32] | TCC_BUBBLE[33] | TCC_BUBBLE[34] | TCC_BUBBLE[35] | TCC_BUBBLE[37] | TCC_BUBBLE[38] | TCC_BUBBLE[39] | TCC_BUBBLE[3] | TCC_BUBBLE[40] | TCC_BUBBLE[42] | TCC_BUBBLE[43] | TCC_BUBBLE[44] | TCC_BUBBLE[45] | TCC_BUBBLE[47] | TCC_BUBBLE[48] | TCC_BUBBLE[49] | TCC_BUBBLE[50] | TCC_BUBBLE[51] | TCC_BUBBLE[53] | TCC_BUBBLE[54] | TCC_BUBBLE[55] | TCC_BUBBLE[56] | TCC_BUBBLE[58] | TCC_BUBBLE[59] | TCC_BUBBLE[5] | TCC_BUBBLE[60] | TCC_BUBBLE[61] | TCC_BUBBLE[63] | TCC_BUBBLE[6] | TCC_BUBBLE[7] | TCC_BUBBLE[8] | TCC_EA0_ATOMIC[0] | TCC_EA0_ATOMIC[10] | TCC_EA0_ATOMIC[11] | TCC_EA0_ATOMIC[12] | TCC_EA0_ATOMIC[13] | TCC_EA0_ATOMIC[15] | TCC_EA0_ATOMIC[16] | TCC_EA0_ATOMIC[17] | TCC_EA0_ATOMIC[18] | TCC_EA0_ATOMIC[19] | TCC_EA0_ATOMIC[1] | TCC_EA0_ATOMIC[21] | TCC_EA0_ATOMIC[22] | TCC_EA0_ATOMIC[23] | TCC_EA0_ATOMIC[24] | TCC_EA0_ATOMIC[26] | TCC_EA0_ATOMIC[27] | TCC_EA0_ATOMIC[28] | TCC_EA0_ATOMIC[29] | TCC_EA0_ATOMIC[2] | TCC_EA0_ATOMIC[31] | TCC_EA0_ATOMIC[32] | TCC_EA0_ATOMIC[33] | TCC_EA0_ATOMIC[34] | TCC_EA0_ATOMIC[35] | TCC_EA0_ATOMIC[37] | TCC_EA0_ATOMIC[38] | TCC_EA0_ATOMIC[39] | TCC_EA0_ATOMIC[3] | TCC_EA0_ATOMIC[40] | TCC_EA0_ATOMIC[42] | TCC_EA0_ATOMIC[43] | TCC_EA0_ATOMIC[44] | TCC_EA0_ATOMIC[45] | TCC_EA0_ATOMIC[47] | TCC_EA0_ATOMIC[48] | TCC_EA0_ATOMIC[49] | TCC_EA0_ATOMIC[50] | TCC_EA0_ATOMIC[51] | TCC_EA0_ATOMIC[53] | TCC_EA0_ATOMIC[54] | TCC_EA0_ATOMIC[55] | TCC_EA0_ATOMIC[56] | TCC_EA0_ATOMIC[58] | TCC_EA0_ATOMIC[59] | TCC_EA0_ATOMIC[5] | TCC_EA0_ATOMIC[60] | TCC_EA0_ATOMIC[61] | TCC_EA0_ATOMIC[63] | TCC_EA0_ATOMIC[6] | TCC_EA0_ATOMIC[7] | TCC_EA0_ATOMIC[8] | TCC_HIT[0] | TCC_HIT[10] | TCC_HIT[11] | TCC_HIT[12] | TCC_HIT[13] | TCC_HIT[15] | TCC_HIT[16] | TCC_HIT[17] | TCC_HIT[18] | TCC_HIT[19] | TCC_HIT[1] | TCC_HIT[21] | TCC_HIT[22] | TCC_HIT[23] | TCC_HIT[24] | TCC_HIT[26] | TCC_HIT[27] | TCC_HIT[28] | TCC_HIT[29] | TCC_HIT[2] | TCC_HIT[31] | TCC_HIT[32] | TCC_HIT[33] | TCC_HIT[34] | TCC_HIT[35] | TCC_HIT[37] | TCC_HIT[38] | TCC_HIT[39] | TCC_HIT[3] | TCC_HIT[40] | TCC_HIT[42] | TCC_HIT[43] | TCC_HIT[44] | TCC_HIT[45] | TCC_HIT[47] | TCC_HIT[48] | TCC_HIT[49] | TCC_HIT[50] | TCC_HIT[51] | TCC_HIT[53] | TCC_HIT[54] | TCC_HIT[55] | TCC_HIT[56] | TCC_HIT[58] | TCC_HIT[59] | TCC_HIT[5] | TCC_HIT[60] | TCC_HIT[61] | TCC_HIT[63] | TCC_HIT[6] | TCC_HIT[7] | TCC_HIT[8] | TCP_TA_TCP_STATE_READ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TD_LOAD_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | Kernel_ID_12 | CPC_CANE_STALL | CPC_CPC_STAT_STALL | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | GRBM_COUNT | GRBM_SPI_BUSY | SPI_CS0_CRAWLER_STALL | SPI_CS1_CRAWLER_STALL | SPI_CS2_CRAWLER_STALL | SPI_CS3_CRAWLER_STALL | SQ_ACTIVE_INST_VMEM | SQ_INSTS_GDS | SQ_INSTS_LDS_ATOMIC | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VSKIPPED | SQ_INST_LEVEL_VMEM | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TCC_EA0_WRREQ[0] | TCC_EA0_WRREQ[10] | TCC_EA0_WRREQ[11] | TCC_EA0_WRREQ[12] | TCC_EA0_WRREQ[14] | TCC_EA0_WRREQ[15] | TCC_EA0_WRREQ[16] | TCC_EA0_WRREQ[17] | TCC_EA0_WRREQ[18] | TCC_EA0_WRREQ[19] | TCC_EA0_WRREQ[1] | TCC_EA0_WRREQ[21] | TCC_EA0_WRREQ[22] | TCC_EA0_WRREQ[23] | TCC_EA0_WRREQ[24] | TCC_EA0_WRREQ[25] | TCC_EA0_WRREQ[26] | TCC_EA0_WRREQ[27] | TCC_EA0_WRREQ[28] | TCC_EA0_WRREQ[2] | TCC_EA0_WRREQ[30] | TCC_EA0_WRREQ[31] | TCC_EA0_WRREQ[32] | TCC_EA0_WRREQ[33] | TCC_EA0_WRREQ[34] | TCC_EA0_WRREQ[35] | TCC_EA0_WRREQ[36] | TCC_EA0_WRREQ[37] | TCC_EA0_WRREQ[38] | TCC_EA0_WRREQ[39] | TCC_EA0_WRREQ[3] | TCC_EA0_WRREQ[41] | TCC_EA0_WRREQ[42] | TCC_EA0_WRREQ[43] | TCC_EA0_WRREQ[44] | TCC_EA0_WRREQ[45] | TCC_EA0_WRREQ[46] | TCC_EA0_WRREQ[47] | TCC_EA0_WRREQ[48] | TCC_EA0_WRREQ[49] | TCC_EA0_WRREQ[50] | TCC_EA0_WRREQ[51] | TCC_EA0_WRREQ[52] | TCC_EA0_WRREQ[53] | TCC_EA0_WRREQ[54] | TCC_EA0_WRREQ[55] | TCC_EA0_WRREQ[57] | TCC_EA0_WRREQ[58] | TCC_EA0_WRREQ[59] | TCC_EA0_WRREQ[5] | TCC_EA0_WRREQ[60] | TCC_EA0_WRREQ[61] | TCC_EA0_WRREQ[62] | TCC_EA0_WRREQ[63] | TCC_EA0_WRREQ[6] | TCC_EA0_WRREQ[7] | TCC_EA0_WRREQ[8] | TCC_EA0_WRREQ[9] | TCC_MISS[0] | TCC_MISS[10] | TCC_MISS[11] | TCC_MISS[12] | TCC_MISS[14] | TCC_MISS[15] | TCC_MISS[16] | TCC_MISS[17] | TCC_MISS[18] | TCC_MISS[19] | TCC_MISS[1] | TCC_MISS[21] | TCC_MISS[22] | TCC_MISS[23] | TCC_MISS[24] | TCC_MISS[25] | TCC_MISS[26] | TCC_MISS[27] | TCC_MISS[28] | TCC_MISS[2] | TCC_MISS[30] | TCC_MISS[31] | TCC_MISS[32] | TCC_MISS[33] | TCC_MISS[34] | TCC_MISS[35] | TCC_MISS[36] | TCC_MISS[37] | TCC_MISS[38] | TCC_MISS[39] | TCC_MISS[3] | TCC_MISS[41] | TCC_MISS[42] | TCC_MISS[43] | TCC_MISS[44] | TCC_MISS[45] | TCC_MISS[46] | TCC_MISS[47] | TCC_MISS[48] | TCC_MISS[49] | TCC_MISS[50] | TCC_MISS[51] | TCC_MISS[52] | TCC_MISS[53] | TCC_MISS[54] | TCC_MISS[55] | TCC_MISS[57] | TCC_MISS[58] | TCC_MISS[59] | TCC_MISS[5] | TCC_MISS[60] | TCC_MISS[61] | TCC_MISS[62] | TCC_MISS[63] | TCC_MISS[6] | TCC_MISS[7] | TCC_MISS[8] | TCC_MISS[9] | TCC_READ[0] | TCC_READ[10] | TCC_READ[11] | TCC_READ[12] | TCC_READ[14] | TCC_READ[15] | TCC_READ[16] | TCC_READ[17] | TCC_READ[18] | TCC_READ[19] | TCC_READ[1] | TCC_READ[21] | TCC_READ[22] | TCC_READ[23] | TCC_READ[24] | TCC_READ[25] | TCC_READ[26] | TCC_READ[27] | TCC_READ[28] | TCC_READ[2] | TCC_READ[30] | TCC_READ[31] | TCC_READ[32] | TCC_READ[33] | TCC_READ[34] | TCC_READ[35] | TCC_READ[36] | TCC_READ[37] | TCC_READ[38] | TCC_READ[39] | TCC_READ[3] | TCC_READ[41] | TCC_READ[42] | TCC_READ[43] | TCC_READ[44] | TCC_READ[45] | TCC_READ[46] | TCC_READ[47] | TCC_READ[48] | TCC_READ[49] | TCC_READ[50] | TCC_READ[51] | TCC_READ[52] | TCC_READ[53] | TCC_READ[54] | TCC_READ[55] | TCC_READ[57] | TCC_READ[58] | TCC_READ[59] | TCC_READ[5] | TCC_READ[60] | TCC_READ[61] | TCC_READ[62] | TCC_READ[63] | TCC_READ[6] | TCC_READ[7] | TCC_READ[8] | TCC_READ[9] | TCC_WRITE[0] | TCC_WRITE[10] | TCC_WRITE[11] | TCC_WRITE[12] | TCC_WRITE[14] | TCC_WRITE[15] | TCC_WRITE[16] | TCC_WRITE[17] | TCC_WRITE[18] | TCC_WRITE[19] | TCC_WRITE[1] | TCC_WRITE[21] | TCC_WRITE[22] | TCC_WRITE[23] | TCC_WRITE[24] | TCC_WRITE[25] | TCC_WRITE[26] | TCC_WRITE[27] | TCC_WRITE[28] | TCC_WRITE[2] | TCC_WRITE[30] | TCC_WRITE[31] | TCC_WRITE[32] | TCC_WRITE[33] | TCC_WRITE[34] | TCC_WRITE[35] | TCC_WRITE[36] | TCC_WRITE[37] | TCC_WRITE[38] | TCC_WRITE[39] | TCC_WRITE[3] | TCC_WRITE[41] | TCC_WRITE[42] | TCC_WRITE[43] | TCC_WRITE[44] | TCC_WRITE[45] | TCC_WRITE[46] | TCC_WRITE[47] | TCC_WRITE[48] | TCC_WRITE[49] | TCC_WRITE[50] | TCC_WRITE[51] | TCC_WRITE[52] | TCC_WRITE[53] | TCC_WRITE[54] | TCC_WRITE[55] | TCC_WRITE[57] | TCC_WRITE[58] | TCC_WRITE[59] | TCC_WRITE[5] | TCC_WRITE[60] | TCC_WRITE[61] | TCC_WRITE[62] | TCC_WRITE[63] | TCC_WRITE[6] | TCC_WRITE[7] | TCC_WRITE[8] | TCC_WRITE[9] | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_RW_READ_REQ_sum | TCP_TCP_LATENCY_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_SPI_STALL_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | 0 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 1 | 13 | 630.0 | 30469.0 | 12744.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 22666001.0 | 58.0 | 197976.0 | 406733.0 | 0.0 | 0.0 | 0.0 | 13 | 389.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 126903.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 154249.0 | 0.0 | 36146.0 | 9826410.0 | 26.0 | 65536.0 | 11.0 | 768.0 | 0.0 | 13 | 0.0 | 0.0 | 32768.0 | 64005.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 656853.0 | 0.0 | 65640.0 | 0.0 | 131072.0 | 13 | 65536.0 | 32768.0 | 114688.0 | 65536.0 | 327680.0 | 49152.0 | 0.0 | 0.0 | 13 | 0.0 | 32768.0 | 32768.0 | 278528.0 | 32768.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 131138.0 | 0.0 | 198002.0 | 65596.0 | 0.0 | 2097152.0 | 0.0 | 1048576.0 | 13 | 76981.0 | 399.0 | 0.0 | 9346.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 533130.0 | 66864.0 | 30395.0 | 66936.0 | 0.0 | 0.0 | 0.0 | 131072.0 | 13 | 0.0 | 0.0 | 1296.0 | 98304.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 5300250.0 | 0.0 | 44.0 | 13 | 129716.0 | 279581.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 65622.0 | 131072.0 | 131072.0 | 13 | 628.0 | 28511.0 | 18570.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 730768.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 | 13 | 76230.0 | 4096.0 | 74700.0 | 146248.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 6406528.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 366347.0 | 357772.0 | 356963.0 | 349090.0 | 376766.0 | 737844.0 | 674665.0 | 709219.0 | 678639.0 | 690427.0 | 343990.0 | 324671.0 | 343293.0 | 346854.0 | 381616.0 | 358883.0 | 363344.0 | 703259.0 | 361957.0 | 743500.0 | 699149.0 | 680115.0 | 684746.0 | 338927.0 | 323941.0 | 341659.0 | 662566.0 | 341692.0 | 342216.0 | 362540.0 | 345698.0 | 325196.0 | 670504.0 | 706680.0 | 336552.0 | 689433.0 | 668474.0 | 338628.0 | 351132.0 | 343139.0 | 331632.0 | 367394.0 | 363667.0 | 344667.0 | 324349.0 | 343830.0 | 339430.0 | 345257.0 | 339020.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 823402.0 | 131072.0 | 0.0 | 524288.0 | 816209.0 | 13 | 39762.0 | 8.0 | 3350.0 | 78383.0 | 78383.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 1358.0 | 19849.0 | 0.0 | 0.0 | 0.0 | 73772.0 | 32768.0 | 2048.0 | 1029.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 2048.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1032.0 | 1025.0 | 1029.0 | 1024.0 | 2048.0 | 1024.0 | 1032.0 | 1029.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1029.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1032.0 | 1029.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1029.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1032.0 | 299809.0 | 150330.0 | 152966.0 | 140377.0 | 141618.0 | 143102.0 | 153709.0 | 289555.0 | 136667.0 | 135044.0 | 132763.0 | 136304.0 | 146473.0 | 146928.0 | 141940.0 | 138800.0 | 153648.0 | 153921.0 | 153401.0 | 142275.0 | 158958.0 | 137764.0 | 154480.0 | 160030.0 | 287362.0 | 150932.0 | 153809.0 | 136102.0 | 148758.0 | 146780.0 | 137156.0 | 142600.0 | 132260.0 | 153858.0 | 148372.0 | 158797.0 | 150948.0 | 156084.0 | 155637.0 | 155676.0 | 134811.0 | 154657.0 | 151789.0 | 152058.0 | 156935.0 | 147692.0 | 137836.0 | 152194.0 | 155650.0 | 149350.0 | 159350.0 | 155714.0 | 151894.0 | 143590.0 | 140617.0 | 158498.0 | 151931.0 | 149816.0 | 134354.0 | 152344.0 | 153376.0 | 0.0 | 6144.0 | 3145.0 | 3072.0 | 3072.0 | 3073.0 | 3145.0 | 3072.0 | 6144.0 | 3072.0 | 3073.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3145.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3114.0 | 3090.0 | 3145.0 | 3072.0 | 6144.0 | 3072.0 | 3114.0 | 3145.0 | 3072.0 | 3072.0 | 3073.0 | 3145.0 | 3145.0 | 3090.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3114.0 | 3145.0 | 3073.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3145.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3114.0 | 1418304.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 571910.0 | 13 | 77276.0 | 0.0 | 0.0 | 3438.0 | 26015654.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 1005075.0 | 0.0 | 0.0 | 0.0 | 170074.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 2135.0 | 1024.0 | 1041.0 | 1094.0 | 1024.0 | 1024.0 | 2118.0 | 2118.0 | 2048.0 | 1024.0 | 2118.0 | 1094.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 2048.0 | 1024.0 | 2118.0 | 2118.0 | 2048.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 1041.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 2118.0 | 2153.0 | 2083.0 | 1024.0 | 1094.0 | 1059.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1094.0 | 1059.0 | 1024.0 | 1024.0 | 1024.0 | 1041.0 | 32768.0 | 0.0 | 0.0 | 493416.0 | 32768.0 | 16384.0 | 13 | 0.0 | 16354.0 | 2108.0 | 0.0 | 74761.0 | 37009.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 256862.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4098.0 | 2048.0 | 2048.0 | 2052.0 | 2050.0 | 2049.0 | 4097.0 | 4096.0 | 2050.0 | 2048.0 | 4098.0 | 2048.0 | 2048.0 | 2051.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2052.0 | 2048.0 | 4102.0 | 2048.0 | 2050.0 | 2049.0 | 2048.0 | 2051.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2051.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2052.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2050.0 | 1024.0 | 1024.0 | 1028.0 | 1096.0 | 1060.0 | 2066.0 | 2048.0 | 1096.0 | 1024.0 | 2050.0 | 1024.0 | 1024.0 | 1097.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1098.0 | 1024.0 | 2054.0 | 1024.0 | 1096.0 | 1060.0 | 1024.0 | 1027.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1026.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 2048.0 | 1024.0 | 1097.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1098.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 12901602.0 | 0.0 | 601.0 | 1248227792617386.5 | 1248227792639148.5 |
| 3 | 1 | 0 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 2 | 13 | 631.0 | 22019.0 | 4288.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 11922030.0 | 16.0 | 197976.0 | 289225.0 | 0.0 | 0.0 | 0.0 | 13 | 0.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 96924.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 103050.0 | 0.0 | 36209.0 | 10285296.0 | 8.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 13 | 0.0 | 0.0 | 32768.0 | 64262.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 95857.0 | 0.0 | 65612.0 | 0.0 | 131072.0 | 13 | 65536.0 | 32768.0 | 114688.0 | 65536.0 | 327680.0 | 49152.0 | 0.0 | 0.0 | 13 | 0.0 | 32768.0 | 32768.0 | 278528.0 | 32768.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 131120.0 | 0.0 | 197984.0 | 65596.0 | 0.0 | 2097152.0 | 0.0 | 1048576.0 | 13 | 65633.0 | 0.0 | 0.0 | 3274.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 459164.0 | 66864.0 | 29343.0 | 66912.0 | 0.0 | 0.0 | 0.0 | 131072.0 | 13 | 0.0 | 0.0 | 1296.0 | 98304.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 4063067.0 | 0.0 | 44.0 | 13 | 97526.0 | 104638.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 65612.0 | 131072.0 | 131072.0 | 13 | 628.0 | 21899.0 | 17097.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 587815.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 | 13 | 66030.0 | 4096.0 | 64509.0 | 108920.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 4413902.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 168628.0 | 188771.0 | 180374.0 | 166979.0 | 187051.0 | 341252.0 | 347378.0 | 366453.0 | 358634.0 | 349942.0 | 166901.0 | 185540.0 | 167789.0 | 186890.0 | 195821.0 | 191987.0 | 161167.0 | 349386.0 | 173327.0 | 351353.0 | 362889.0 | 349396.0 | 340194.0 | 166112.0 | 162174.0 | 179731.0 | 326950.0 | 183560.0 | 167731.0 | 191528.0 | 159788.0 | 174031.0 | 333041.0 | 347181.0 | 191522.0 | 361391.0 | 371374.0 | 166146.0 | 185780.0 | 171148.0 | 183365.0 | 196992.0 | 178416.0 | 168290.0 | 169604.0 | 172663.0 | 165574.0 | 182558.0 | 177592.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 647210.0 | 131072.0 | 0.0 | 524288.0 | 639099.0 | 13 | 35094.0 | 8.0 | 3391.0 | 64716.0 | 64716.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 996.0 | 17914.0 | 0.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 2048.0 | 1028.0 | 1024.0 | 1025.0 | 1026.0 | 1028.0 | 1024.0 | 2049.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1025.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1028.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1025.0 | 1026.0 | 1028.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1026.0 | 307368.0 | 162005.0 | 160446.0 | 151060.0 | 153141.0 | 157304.0 | 151470.0 | 305183.0 | 146408.0 | 156888.0 | 152592.0 | 146297.0 | 143934.0 | 145080.0 | 157918.0 | 159116.0 | 146547.0 | 154796.0 | 157202.0 | 148817.0 | 159205.0 | 153646.0 | 161241.0 | 155953.0 | 316781.0 | 151490.0 | 159946.0 | 158706.0 | 146499.0 | 145428.0 | 160731.0 | 157547.0 | 151609.0 | 154421.0 | 158188.0 | 161612.0 | 161330.0 | 158057.0 | 162267.0 | 154697.0 | 156653.0 | 151979.0 | 161987.0 | 154131.0 | 157525.0 | 139803.0 | 153051.0 | 159171.0 | 150842.0 | 160845.0 | 161000.0 | 157519.0 | 152887.0 | 158287.0 | 158280.0 | 149117.0 | 164042.0 | 142572.0 | 153599.0 | 158627.0 | 147290.0 | 0.0 | 6144.0 | 3144.0 | 3072.0 | 3073.0 | 3091.0 | 3144.0 | 3072.0 | 6145.0 | 3072.0 | 3091.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3073.0 | 3108.0 | 3144.0 | 3072.0 | 3072.0 | 3091.0 | 3144.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3073.0 | 3108.0 | 3144.0 | 3091.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3108.0 | 1062800.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 347780.0 | 13 | 66157.0 | 0.0 | 0.0 | 3477.0 | 18725576.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 751413.0 | 0.0 | 0.0 | 0.0 | 109530.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 2118.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 2135.0 | 2118.0 | 2048.0 | 1041.0 | 2118.0 | 1094.0 | 1024.0 | 1024.0 | 1041.0 | 1024.0 | 1041.0 | 1094.0 | 1024.0 | 2048.0 | 1024.0 | 2118.0 | 2118.0 | 2048.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 2118.0 | 2153.0 | 2083.0 | 1024.0 | 1094.0 | 1059.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1094.0 | 1059.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 32768.0 | 0.0 | 0.0 | 524288.0 | 32768.0 | 16384.0 | 13 | 0.0 | 14445.0 | 2112.0 | 0.0 | 66766.0 | 29059.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 186838.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4098.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2049.0 | 4097.0 | 4096.0 | 2050.0 | 2048.0 | 4096.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2050.0 | 2048.0 | 4097.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 4097.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2067.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1060.0 | 2049.0 | 2048.0 | 1096.0 | 1024.0 | 2048.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1096.0 | 1024.0 | 2049.0 | 1024.0 | 1096.0 | 1060.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1042.0 | 2049.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1025.0 | 1025.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 8973198.0 | 0.0 | 897.0 | 1248227793203453.2 | 1248227793220373.0 |
| 4 | 2 | 0 | 1048576 | 256 | 0 | 0 | 4 | 0 | 16 | 64 | vecCopy(double*, double*, double*, int, int) | 3 | 13 | 630.0 | 21586.0 | 3860.0 | 32768.0 | 0.0 | 72.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 11792534.0 | 0.0 | 197976.0 | 286818.0 | 0.0 | 0.0 | 0.0 | 13 | 0.0 | 0.0 | 4096.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 98304.0 | 96768.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 100616.0 | 0.0 | 36239.0 | 10281734.0 | 0.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 13 | 0.0 | 0.0 | 32768.0 | 64364.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 120606.0 | 0.0 | 65612.0 | 0.0 | 131072.0 | 13 | 65536.0 | 32768.0 | 114688.0 | 65536.0 | 327680.0 | 49152.0 | 0.0 | 0.0 | 13 | 0.0 | 32768.0 | 32768.0 | 278528.0 | 32768.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 131112.0 | 0.0 | 197976.0 | 65596.0 | 0.0 | 2097152.0 | 0.0 | 1048576.0 | 13 | 62962.0 | 0.0 | 0.0 | 3253.0 | 2160.0 | 65536.0 | 0.0 | 49152.0 | 0.0 | 0.0 | 0.0 | 6291456.0 | 0.0 | 32768.0 | 460697.0 | 66864.0 | 29330.0 | 66904.0 | 0.0 | 0.0 | 0.0 | 131072.0 | 13 | 0.0 | 0.0 | 1296.0 | 98304.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 4109650.0 | 0.0 | 44.0 | 13 | 97380.0 | 103228.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 65612.0 | 131072.0 | 131072.0 | 13 | 628.0 | 21865.0 | 17000.0 | 32768.0 | 0.0 | 72.0 | 65536.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 587705.0 | 0.0 | 0.0 | 131072.0 | 0.0 | 0.0 | 0.0 | 128.0 | 524288.0 | 13 | 61716.0 | 4096.0 | 60350.0 | 107896.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 4337140.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 192457.0 | 179283.0 | 183607.0 | 168303.0 | 188445.0 | 363907.0 | 353513.0 | 336506.0 | 358454.0 | 357389.0 | 166113.0 | 175264.0 | 165655.0 | 198953.0 | 179626.0 | 182508.0 | 166395.0 | 349820.0 | 187371.0 | 369566.0 | 387313.0 | 340202.0 | 353747.0 | 167292.0 | 163935.0 | 187961.0 | 331568.0 | 189609.0 | 166929.0 | 186667.0 | 164998.0 | 190238.0 | 336870.0 | 380054.0 | 177919.0 | 357408.0 | 351545.0 | 166698.0 | 185523.0 | 186549.0 | 188624.0 | 178890.0 | 183734.0 | 165658.0 | 163188.0 | 167422.0 | 177959.0 | 191058.0 | 197686.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 648321.0 | 131072.0 | 0.0 | 524288.0 | 640253.0 | 13 | 35834.0 | 8.0 | 376.0 | 62877.0 | 62877.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 63304.0 | 72.0 | 1039.0 | 18047.0 | 0.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 2048.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1024.0 | 1028.0 | 1024.0 | 2048.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1024.0 | 1024.0 | 1026.0 | 1028.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1028.0 | 1024.0 | 1024.0 | 1024.0 | 1025.0 | 1028.0 | 1026.0 | 297690.0 | 151572.0 | 166245.0 | 153966.0 | 152335.0 | 145177.0 | 155284.0 | 305526.0 | 157035.0 | 150029.0 | 149885.0 | 155828.0 | 160141.0 | 154195.0 | 151522.0 | 154137.0 | 145865.0 | 151468.0 | 159289.0 | 156374.0 | 151317.0 | 155030.0 | 151653.0 | 156309.0 | 306747.0 | 153464.0 | 147495.0 | 145937.0 | 158635.0 | 156119.0 | 151800.0 | 147953.0 | 147121.0 | 150499.0 | 157270.0 | 159094.0 | 162440.0 | 154810.0 | 149439.0 | 150285.0 | 151413.0 | 156221.0 | 151239.0 | 147915.0 | 162813.0 | 149282.0 | 153992.0 | 156456.0 | 151068.0 | 159130.0 | 163566.0 | 164073.0 | 155062.0 | 156829.0 | 142277.0 | 152961.0 | 146665.0 | 148927.0 | 154406.0 | 155546.0 | 152788.0 | 0.0 | 6144.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3072.0 | 3144.0 | 3072.0 | 6144.0 | 3072.0 | 3108.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3072.0 | 3072.0 | 3108.0 | 3144.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3072.0 | 3144.0 | 3072.0 | 3072.0 | 3072.0 | 3090.0 | 3144.0 | 3108.0 | 1074680.0 | 0.0 | 0.0 | 1048576.0 | 0.0 | 343195.0 | 13 | 62396.0 | 0.0 | 0.0 | 376.0 | 18327092.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 740907.0 | 0.0 | 0.0 | 0.0 | 108626.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 2118.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 2118.0 | 2118.0 | 2048.0 | 1024.0 | 2118.0 | 1094.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 2048.0 | 1024.0 | 2118.0 | 2118.0 | 2048.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 1094.0 | 1024.0 | 1024.0 | 2135.0 | 2153.0 | 2083.0 | 1041.0 | 1094.0 | 1059.0 | 1024.0 | 1041.0 | 1024.0 | 1041.0 | 1094.0 | 1094.0 | 1059.0 | 1024.0 | 1024.0 | 1024.0 | 1024.0 | 32768.0 | 0.0 | 0.0 | 524288.0 | 32768.0 | 16384.0 | 13 | 0.0 | 11292.0 | 2055.0 | 0.0 | 63585.0 | 29133.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 0.0 | 186316.0 | 0.0 | 0.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4097.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 4096.0 | 4096.0 | 2050.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2050.0 | 2048.0 | 4097.0 | 2048.0 | 2050.0 | 2049.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2049.0 | 2048.0 | 2050.0 | 2048.0 | 2048.0 | 2048.0 | 2050.0 | 2049.0 | 2050.0 | 2066.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 2048.0 | 2048.0 | 1096.0 | 1024.0 | 2048.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1096.0 | 1024.0 | 2066.0 | 1024.0 | 1096.0 | 1060.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 2048.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1042.0 | 1024.0 | 1096.0 | 1024.0 | 1024.0 | 1024.0 | 1096.0 | 1060.0 | 1096.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 4096.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 4096.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 2048.0 | 0.0 | 0.0 | 65536.0 | 8951646.0 | 0.0 | 876.0 | 1248227793701339.8 | 1248227793718203.8 |