Mario Limonciello
bc5d48e76c
* Run pre-commit's whitespace related hooks on projects/rocr-runtime In order for pre-commit to be useful, everything needs to meet a common baseline. Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> * Add missing semicolon which would block compilation on big endian CPUs Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> --------- Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
318 linhas
9.8 KiB
C++
318 linhas
9.8 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2022, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "image_lut_gfx11.h"
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#include "resource_gfx11.h"
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namespace rocr {
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namespace image {
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/*
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* The type table has changed for gfx11, so we need a separate instance for
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* the Property LUT
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*/
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const ImageProperty ImageLutGfx11::kPropLutGfx11_[ORDER_COUNT][TYPE_COUNT] = {
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_A
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{RW, 1, FMT_8, TYPE_SNORM},
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{RW, 2, FMT_16, TYPE_SNORM},
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{RW, 1, FMT_8, TYPE_UNORM},
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{RW, 2, FMT_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 1, FMT_8, TYPE_SINT},
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{RW, 2, FMT_16, TYPE_SINT},
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{RW, 4, FMT_32, TYPE_SINT},
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{RW, 1, FMT_8, TYPE_UINT},
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{RW, 2, FMT_16, TYPE_UINT},
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{RW, 4, FMT_32, TYPE_UINT},
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{RW, 2, FMT_16, TYPE_FLOAT},
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{RW, 4, FMT_32, TYPE_FLOAT}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_R
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{RW, 1, FMT_8, TYPE_SNORM},
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{RW, 2, FMT_16, TYPE_SNORM},
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{RW, 1, FMT_8, TYPE_UNORM},
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{RW, 2, FMT_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 1, FMT_8, TYPE_SINT},
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{RW, 2, FMT_16, TYPE_SINT},
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{RW, 4, FMT_32, TYPE_SINT},
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{RW, 1, FMT_8, TYPE_UINT},
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{RW, 2, FMT_16, TYPE_UINT},
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{RW, 4, FMT_32, TYPE_UINT},
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{RW, 2, FMT_16, TYPE_FLOAT},
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{RW, 4, FMT_32, TYPE_FLOAT}},
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_RX
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{ // HSA_EXT_IMAGE_CHANNEL_ORDER_RG
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{RW, 2, FMT_8_8, TYPE_SNORM},
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{RW, 4, FMT_16_16, TYPE_SNORM},
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{RW, 2, FMT_8_8, TYPE_UNORM},
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{RW, 4, FMT_16_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 2, FMT_8_8, TYPE_SINT},
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{RW, 4, FMT_16_16, TYPE_SINT},
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{RW, 8, FMT_32_32, TYPE_SINT},
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{RW, 2, FMT_8_8, TYPE_UINT},
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{RW, 4, FMT_16_16, TYPE_UINT},
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{RW, 8, FMT_32_32, TYPE_UINT},
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{RW, 4, FMT_16_16, TYPE_FLOAT},
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{RW, 8, FMT_32_32, TYPE_FLOAT}},
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_RGX
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{ // HSA_EXT_IMAGE_CHANNEL_ORDER_RA
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{RW, 2, FMT_8_8, TYPE_SNORM},
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{RW, 4, FMT_16_16, TYPE_SNORM},
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{RW, 2, FMT_8_8, TYPE_UNORM},
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{RW, 4, FMT_16_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 2, FMT_8_8, TYPE_SINT},
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{RW, 4, FMT_16_16, TYPE_SINT},
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{RW, 8, FMT_32_32, TYPE_SINT},
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{RW, 2, FMT_8_8, TYPE_UINT},
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{RW, 4, FMT_16_16, TYPE_UINT},
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{RW, 8, FMT_32_32, TYPE_UINT},
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{RW, 4, FMT_16_16, TYPE_FLOAT},
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{RW, 8, FMT_32_32, TYPE_FLOAT}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_RGB
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 2, FMT_1_5_5_5, TYPE_UNORM},
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{RW, 2, FMT_5_6_5, TYPE_UNORM},
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{RW, 4, FMT_2_10_10_10, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0}},
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_RGBX
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{ // HSA_EXT_IMAGE_CHANNEL_ORDER_RGBA
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{RW, 4, FMT_8_8_8_8, TYPE_SNORM},
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{RW, 8, FMT_16_16_16_16, TYPE_SNORM},
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{RW, 4, FMT_8_8_8_8, TYPE_UNORM},
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{RW, 8, FMT_16_16_16_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_SINT},
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{RW, 8, FMT_16_16_16_16, TYPE_SINT},
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{RW, 16, FMT_32_32_32_32, TYPE_SINT},
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{RW, 4, FMT_8_8_8_8, TYPE_UINT},
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{RW, 8, FMT_16_16_16_16, TYPE_UINT},
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{RW, 16, FMT_32_32_32_32, TYPE_UINT},
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{RW, 8, FMT_16_16_16_16, TYPE_FLOAT},
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{RW, 16, FMT_32_32_32_32, TYPE_FLOAT}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_BGRA
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{RW, 4, FMT_8_8_8_8, TYPE_SNORM},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_SINT},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_UINT},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_ARGB
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{RW, 4, FMT_8_8_8_8, TYPE_SNORM},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_SINT},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 4, FMT_8_8_8_8, TYPE_UINT},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0}},
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_ABGR
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX
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{ // HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RO, 4, FMT_8_8_8_8, TYPE_SRGB},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0}},
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{}, // HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA
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{ // HSA_EXT_IMAGE_CHANNEL_ORDER_INTENSITY
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{RW, 1, FMT_8, TYPE_SNORM},
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{RW, 2, FMT_16, TYPE_SNORM},
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{RW, 1, FMT_8, TYPE_UNORM},
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{RW, 2, FMT_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 2, FMT_16, TYPE_FLOAT},
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{RW, 4, FMT_32, TYPE_FLOAT}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_LUMINANCE
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{RW, 1, FMT_8, TYPE_SNORM},
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{RW, 2, FMT_16, TYPE_SNORM},
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{RW, 1, FMT_8, TYPE_UNORM},
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{RW, 2, FMT_16, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{RW, 2, FMT_16, TYPE_FLOAT},
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{RW, 4, FMT_32, TYPE_FLOAT}},
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{// HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{ROWO, 2, FMT_16, TYPE_UNORM},
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// TODO: 24 bit
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{0, 3, FMT_32, TYPE_UNORM},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{0, 0, 0, 0},
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{ROWO, 4, FMT_32, TYPE_FLOAT}},
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{} // HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL
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};
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ImageProperty ImageLutGfx11::MapFormat(const hsa_ext_image_format_t& format,
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hsa_ext_image_geometry_t geometry) const {
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switch (geometry) {
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case HSA_EXT_IMAGE_GEOMETRY_1D:
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case HSA_EXT_IMAGE_GEOMETRY_2D:
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case HSA_EXT_IMAGE_GEOMETRY_3D:
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case HSA_EXT_IMAGE_GEOMETRY_1DA:
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case HSA_EXT_IMAGE_GEOMETRY_2DA:
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return kPropLutGfx11_[format.channel_order][format.channel_type];
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case HSA_EXT_IMAGE_GEOMETRY_1DB:
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switch (format.channel_order) {
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// Hardware does not support buffer access to srgb image.
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case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGB:
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case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBX:
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case HSA_EXT_IMAGE_CHANNEL_ORDER_SRGBA:
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case HSA_EXT_IMAGE_CHANNEL_ORDER_SBGRA:
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break;
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default:
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switch (format.channel_type) {
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// Hardware does not support buffer access to 555/565 packed image.
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case HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_555:
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case HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_565:
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break;
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default:
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return kPropLutGfx11_[format.channel_order][format.channel_type];
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}
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}
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break;
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case HSA_EXT_IMAGE_GEOMETRY_2DDEPTH:
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case HSA_EXT_IMAGE_GEOMETRY_2DADEPTH:
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switch (format.channel_order) {
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case HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH:
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case HSA_EXT_IMAGE_CHANNEL_ORDER_DEPTH_STENCIL:
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return kPropLutGfx11_[format.channel_order][format.channel_type];
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default:
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break;
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}
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break;
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default:
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assert(false && "Should not reach here");
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break;
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}
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ImageProperty prop = {0};
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return prop;
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}
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} // namespace image
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} // namespace rocr
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