taosang2
a5de0f048d
Support different address modes in X, Y, Z directions
Change-Id: If1db5a8af33c92ddc4b48968c3d8eceb97daea6a
[ROCm/ROCR-Runtime commit: df250a49a5]
509 regels
14 KiB
C++
509 regels
14 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#ifndef HSA_RUNTIME_EXT_IMAGE_RESOURCE_KV_H
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#define HSA_RUNTIME_EXT_IMAGE_RESOURCE_KV_H
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#if defined(LITTLEENDIAN_CPU)
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#elif defined(BIGENDIAN_CPU)
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#else
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#error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined"
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#endif
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namespace rocr {
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namespace image {
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union SQ_BUF_RSRC_WORD0 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int base_address : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int base_address : 32;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_BUF_RSRC_WORD1 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int base_address_hi : 16;
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unsigned int stride : 14;
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unsigned int cache_swizzle : 1;
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unsigned int swizzle_enable : 1;
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#elif defined(BIGENDIAN_CPU)
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unsigned int swizzle_enable : 1;
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unsigned int cache_swizzle : 1;
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unsigned int stride : 14;
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unsigned int base_address_hi : 16;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_BUF_RSRC_WORD2 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int num_records : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int num_records : 32;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_BUF_RSRC_WORD3 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int dst_sel_x : 3;
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unsigned int dst_sel_y : 3;
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unsigned int dst_sel_z : 3;
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unsigned int dst_sel_w : 3;
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unsigned int num_format : 3;
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unsigned int data_format : 4;
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unsigned int element_size : 2;
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unsigned int index_stride : 2;
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unsigned int add_tid_enable : 1;
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unsigned int atc : 1;
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unsigned int hash_enable : 1;
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unsigned int heap : 1;
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unsigned int mtype : 3;
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unsigned int type : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int type : 2;
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unsigned int mtype : 3;
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unsigned int heap : 1;
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unsigned int hash_enable : 1;
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unsigned int atc : 1;
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unsigned int add_tid_enable : 1;
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unsigned int index_stride : 2;
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unsigned int element_size : 2;
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unsigned int data_format : 4;
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unsigned int num_format : 3;
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unsigned int dst_sel_w : 3;
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unsigned int dst_sel_z : 3;
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unsigned int dst_sel_y : 3;
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unsigned int dst_sel_x : 3;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD0 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int base_address : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int base_address : 32;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD1 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int base_address_hi : 8;
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unsigned int min_lod : 12;
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unsigned int data_format : 6;
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unsigned int num_format : 4;
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unsigned int mtype : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int mtype : 2;
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unsigned int num_format : 4;
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unsigned int data_format : 6;
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unsigned int min_lod : 12;
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unsigned int base_address_hi : 8;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD2 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int width : 14;
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unsigned int height : 14;
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unsigned int perf_mod : 3;
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unsigned int interlaced : 1;
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#elif defined(BIGENDIAN_CPU)
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unsigned int interlaced : 1;
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unsigned int perf_mod : 3;
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unsigned int height : 14;
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unsigned int width : 14;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD3 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int dst_sel_x : 3;
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unsigned int dst_sel_y : 3;
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unsigned int dst_sel_z : 3;
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unsigned int dst_sel_w : 3;
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unsigned int base_level : 4;
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unsigned int last_level : 4;
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unsigned int tiling_index : 5;
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unsigned int pow2_pad : 1;
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unsigned int mtype : 1;
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unsigned int atc : 1;
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unsigned int type : 4;
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#elif defined(BIGENDIAN_CPU)
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unsigned int type : 4;
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unsigned int atc : 1;
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unsigned int mtype : 1;
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unsigned int pow2_pad : 1;
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unsigned int tiling_index : 5;
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unsigned int last_level : 4;
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unsigned int base_level : 4;
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unsigned int dst_sel_w : 3;
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unsigned int dst_sel_z : 3;
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unsigned int dst_sel_y : 3;
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unsigned int dst_sel_x : 3;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD4 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int depth : 13;
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unsigned int pitch : 14;
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unsigned int : 5;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 5;
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unsigned int pitch : 14;
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unsigned int depth : 13;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD5 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int base_array : 13;
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unsigned int last_array : 13;
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unsigned int : 6;
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#elif defined(BIGENDIAN_CPU)
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unsigned int : 6;
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unsigned int last_array : 13;
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unsigned int base_array : 13;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD6 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int min_lod_warn : 12;
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unsigned int counter_bank_id : 8;
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unsigned int lod_hdw_cnt_en : 1;
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unsigned int compression_en : 1;
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unsigned int alpha_is_on_msb : 1;
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unsigned int color_transform : 1;
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unsigned int lost_alpha_bits : 4;
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unsigned int lost_color_bits : 4;
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#elif defined(BIGENDIAN_CPU)
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unsigned int lost_color_bits : 4;
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unsigned int lost_alpha_bits : 4;
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unsigned int color_transform : 1;
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unsigned int alpha_is_on_msb : 1;
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unsigned int compression_en : 1;
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unsigned int lod_hdw_cnt_en : 1;
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unsigned int counter_bank_id : 8;
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unsigned int min_lod_warn : 12;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_RSRC_WORD7 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int meta_data_address : 32;
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#elif defined(BIGENDIAN_CPU)
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unsigned int meta_data_address : 32;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_SAMP_WORD0 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int CLAMP_X : 3;
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unsigned int CLAMP_Y : 3;
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unsigned int CLAMP_Z : 3;
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unsigned int max_aniso_ratio : 3;
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unsigned int depth_compare_func : 3;
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unsigned int force_unormalized : 1;
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unsigned int aniso_threshold : 3;
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unsigned int mc_coord_trunc : 1;
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unsigned int force_degamma : 1;
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unsigned int aniso_bias : 6;
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unsigned int trunc_coord : 1;
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unsigned int disable_cube_wrap : 1;
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unsigned int filter_mode : 2;
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unsigned int compat_mode : 1;
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#elif defined(BIGENDIAN_CPU)
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unsigned int compat_mode : 1;
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unsigned int filter_mode : 2;
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unsigned int disable_cube_wrap : 1;
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unsigned int trunc_coord : 1;
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unsigned int aniso_bias : 6;
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unsigned int force_degamma : 1;
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unsigned int mc_coord_trunc : 1;
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unsigned int aniso_threshold : 3;
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unsigned int force_unormalized : 1;
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unsigned int depth_compare_func : 3;
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unsigned int max_aniso_ratio : 3;
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unsigned int CLAMP_Z : 3;
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unsigned int CLAMP_Y : 3;
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unsigned int CLAMP_X : 3;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_SAMP_WORD1 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int min_lod : 12;
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unsigned int max_lod : 12;
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unsigned int perf_mip : 4;
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unsigned int perf_z : 4;
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#elif defined(BIGENDIAN_CPU)
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unsigned int perf_z : 4;
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unsigned int perf_mip : 4;
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unsigned int max_lod : 12;
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unsigned int min_lod : 12;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_SAMP_WORD2 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int lod_bias : 14;
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unsigned int lod_bias_sec : 6;
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unsigned int xy_mag_filter : 2;
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unsigned int xy_min_filter : 2;
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unsigned int z_filter : 2;
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unsigned int mip_filter : 2;
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unsigned int mip_point_preclamp : 1;
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unsigned int disable_lsb_ceil : 1;
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unsigned int filter_prec_fix : 1;
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unsigned int aniso_override_vi : 1;
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#elif defined(BIGENDIAN_CPU)
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unsigned int aniso_override_vi : 1;
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unsigned int filter_prec_fix : 1;
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unsigned int disable_lsb_ceil : 1;
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unsigned int mip_point_preclamp : 1;
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unsigned int mip_filter : 2;
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unsigned int z_filter : 2;
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unsigned int xy_min_filter : 2;
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unsigned int xy_mag_filter : 2;
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unsigned int lod_bias_sec : 6;
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unsigned int lod_bias : 14;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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union SQ_IMG_SAMP_WORD3 {
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struct {
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#if defined(LITTLEENDIAN_CPU)
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unsigned int border_color_ptr : 12;
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unsigned int : 18;
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unsigned int border_color_type : 2;
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#elif defined(BIGENDIAN_CPU)
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unsigned int border_color_type : 2;
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unsigned int : 18;
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unsigned int border_color_ptr : 12;
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#endif
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} bitfields, bits;
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unsigned int u32_all;
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signed int i32_all;
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float f32_all;
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};
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typedef enum FMT {
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FMT_INVALID = 0x00000000,
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FMT_8 = 0x00000001,
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FMT_16 = 0x00000002,
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FMT_8_8 = 0x00000003,
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FMT_32 = 0x00000004,
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FMT_16_16 = 0x00000005,
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FMT_10_10_10_2 = 0x00000008,
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FMT_2_10_10_10 = 0x00000009,
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FMT_8_8_8_8 = 0x0000000a,
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FMT_32_32 = 0x0000000b,
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FMT_16_16_16_16 = 0x0000000c,
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FMT_32_32_32 = 0x0000000d,
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FMT_32_32_32_32 = 0x0000000e,
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FMT_5_6_5 = 0x00000010,
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FMT_1_5_5_5 = 0x00000011,
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FMT_5_5_5_1 = 0x00000012,
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FMT_8_24 = 0x00000014,
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FMT_24_8 = 0x00000015,
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FMT_X24_8_32 = 0x00000016,
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FMT_RESERVED_24__SI__CI = 0x00000018
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} FMT;
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typedef enum type {
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TYPE_UNORM = 0x00000000,
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TYPE_SNORM = 0x00000001,
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TYPE_UINT = 0x00000004,
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TYPE_SINT = 0x00000005,
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TYPE_FLOAT = 0x00000007,
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TYPE_SRGB = 0x00000009
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} type;
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typedef enum SEL {
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SEL_0 = 0x00000000,
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SEL_1 = 0x00000001,
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SEL_X = 0x00000004,
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SEL_Y = 0x00000005,
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SEL_Z = 0x00000006,
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SEL_W = 0x00000007,
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} SEL;
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typedef enum SQ_RSRC_IMG_TYPE {
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SQ_RSRC_IMG_1D = 0x00000008,
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SQ_RSRC_IMG_2D = 0x00000009,
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SQ_RSRC_IMG_3D = 0x0000000a,
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SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
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SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
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} SQ_RSRC_IMG_TYPE;
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typedef enum SQ_TEX_XY_FILTER {
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SQ_TEX_XY_FILTER_POINT = 0x00000000,
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SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
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SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
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SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
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} SQ_TEX_XY_FILTER;
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typedef enum SQ_TEX_Z_FILTER {
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SQ_TEX_Z_FILTER_NONE = 0x00000000,
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SQ_TEX_Z_FILTER_POINT = 0x00000001,
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SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
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} SQ_TEX_Z_FILTER;
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typedef enum SQ_TEX_MIP_FILTER {
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SQ_TEX_MIP_FILTER_NONE = 0x00000000,
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SQ_TEX_MIP_FILTER_POINT = 0x00000001,
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SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
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SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ__VI = 0x00000003,
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} SQ_TEX_MIP_FILTER;
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typedef enum SQ_TEX_CLAMP {
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SQ_TEX_WRAP = 0x00000000,
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SQ_TEX_MIRROR = 0x00000001,
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SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
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SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
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SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
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SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
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SQ_TEX_CLAMP_BORDER = 0x00000006,
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SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
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} SQ_TEX_CLAMP;
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typedef enum SQ_TEX_BORDER_COLOR {
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SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
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SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
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SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
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SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
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} SQ_TEX_BORDER_COLOR;
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typedef struct metadata_amd_ci_vi_s {
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uint32_t version; // Must be 1
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uint32_t vendorID; // AMD | CZ
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SQ_IMG_RSRC_WORD0 word0;
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SQ_IMG_RSRC_WORD1 word1;
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SQ_IMG_RSRC_WORD2 word2;
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SQ_IMG_RSRC_WORD3 word3;
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SQ_IMG_RSRC_WORD4 word4;
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SQ_IMG_RSRC_WORD5 word5;
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SQ_IMG_RSRC_WORD6 word6;
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SQ_IMG_RSRC_WORD7 word7;
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uint32_t mip_offsets[0]; //Mip level offset bits [39:8] for each level (if any)
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} metadata_amd_ci_vi_t;
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} // namespace image
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} // namespace rocr
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#endif // HSA_RUNTIME_EXT_IMAGE_RESOURCE_KV_H
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