Scott Todd
fa772be675
## Overview and rationale This reverts https://github.com/ROCm/rocm-systems/pull/1886, which... * Re-applies https://github.com/ROCm/rocm-systems/pull/1866 * Reverts https://github.com/ROCm/rocm-systems/pull/1728 (So it restores the [`amdgpu-windows-interop/`](https://github.com/ROCm/rocm-systems/tree/develop/shared/amdgpu-windows-interop) folder back to the state from a few weeks ago) The rationale for this change is at https://github.com/ROCm/rocm-systems/pull/1866: > Last PAL update broke applications on gfx12 Windows. ## Cross-repository change details That PR failed to build but was merged with this explanation: > TheRock CI Windows build fails as expected with this revert. > > References to these PAL members need to be stripped out in a patch on TheRock. > > ``` > 11.3 C:\home\runner\_work\rocm-systems\rocm-systems\projects\clr\rocclr\device\pal\palubercapturemgr.cpp(152): error C2039: 'RegisterTraceStateChangeCallback': is not a member of 'GpuUtil::TraceSession' > 11.4 C:\home\runner\_work\rocm-systems\rocm-systems\shared\amdgpu-windows-interop\pal\inc\gpuUtil\palTraceSession.h(372): note: see declaration of 'GpuUtil::TraceSession' > 11.4 C:\home\runner\_work\rocm-systems\rocm-systems\projects\clr\rocclr\device\pal\palubercapturemgr.cpp(195): error C2039: 'UnregisterTraceStateChangeCallback': is not a member of 'GpuUtil::TraceSession' > 11.4 C:\home\runner\_work\rocm-systems\rocm-systems\shared\amdgpu-windows-interop\pal\inc\gpuUtil\palTraceSession.h(372): note: see declaration of 'GpuUtil::TraceSession' > ``` The patch in TheRock was updated in https://github.com/ROCm/TheRock/pull/2154. This rolls forward by updating the ref for TheRock. That original PR could have been sequenced differently to avoid a build break - perhaps by * Pointing to a branch in TheRock with the patch rebased * Deleting the patch in the workflows here but holding a local copy of the path to be applied in workflows * Landing the patch as a normal commit instead of carrying it at all ## Test plan 1. Watch TheRock CI here (https://github.com/ROCm/rocm-systems/actions/runs/19447202693/job/55644411119?pr=1893) 2. Build locally: ```bash # In rocm-systems git am --whitespace=nowarn D:\projects\TheRock\patches\amd-mainline\rocm-systems\0001-Revert-SWDEV-543498-Some-compute-Ubertrace-profiles-.patch git am --whitespace=nowarn D:\projects\TheRock\patches\amd-mainline\rocm-systems\0003-Use-is_versioned-true-consistently-in-both-Comgr-Loa.patch git am --whitespace=nowarn D:\projects\TheRock\patches\amd-mainline\rocm-systems\0006-Explicitly-load-libamdhip64.so.7.patch # Note: the build fails with the observed errors if patch 0001 is not applied! # In TheRock cmake -DCMAKE_BUILD_TYPE=Release \ -DCMAKE_C_COMPILER=cl.exe -DCMAKE_CXX_COMPILER=cl.exe \ -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache \ -DPython3_EXECUTABLE=d:/projects/TheRock/.venv/Scripts/python \ -DTHEROCK_ROCM_SYSTEMS_SOURCE_DIR=d:/projects/TheRock/../rocm-systems \ # IMPORTANT -DTHEROCK_AMDGPU_FAMILIES=gfx110X-all \ -DBUILD_TESTING=ON \ -DTHEROCK_ENABLE_ALL=ON \ -Damd-llvm_BUILD_TYPE=RelWithDebInfo \ -S D:/projects/TheRock \ -B D:/projects/TheRock/build \ -G Ninja cmake --build D:/projects/TheRock/build --target hip-clr # [build] Build finished with exit code 0 cmake --build D:/projects/TheRock/build --target ocl-clr+dist # [build] Build finished with exit code 0 ```
627 satır
31 KiB
C++
627 satır
31 KiB
C++
/*
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***********************************************************************************************************************
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*
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* Copyright (c) 2016-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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**********************************************************************************************************************/
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/**
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***********************************************************************************************************************
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* @file palDeveloperHooks.h
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* @brief Common include for PAL developer callbacks. Defines common enums, typedefs, structures, etc.
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***********************************************************************************************************************
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*/
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#pragma once
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#include "pal.h"
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#include "palCmdBuffer.h"
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namespace Pal
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{
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// Forward declarations.
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class ICmdBuffer;
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class IImage;
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class IPipeline;
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namespace Developer
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{
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/// The type of the developer callback so the callback can properly perform whatever actions it needs.
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///
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/// @see Callback
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enum class CallbackType : uint32
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{
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AllocGpuMemory = 0, ///< This callback is to inform that GPU memory has been allocated.
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FreeGpuMemory, ///< This callback is to inform that GPU memory has been freed.
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PresentConcluded, ///< This callback is to inform that a present has concluded.
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ImageBarrier, ///< This callback is to inform that a barrier is being executed.
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CreateImage, ///< This callback is to inform that an image has been created.
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BarrierBegin, ///< This callback is to inform that a barrier is about to be executed.
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BarrierEnd, ///< This callback is to inform that a barrier is done being executed.
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DrawDispatch, ///< This callback is to inform that a draw or dispatch command is being recorded.
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BindPipeline, ///< This callback is to inform that a pipeline (client or internal) has been bound.
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SurfRegData, ///< This callback is to inform tools of the register state of a surface.
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#if PAL_DEVELOPER_BUILD
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DrawDispatchValidation, ///< This callback is to describe the state validation needed by a draw or dispatch.
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BindPipelineValidation, ///< This callback is to describe the state validation needed by a pipeline bind.
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OptimizedRegisters, ///< This callback is to describe the PM4 optimizer's removal of redundant register
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/// sets.
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#endif
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BindGpuMemory, ///< This callback is to inform of a new binding to GPU memory.
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SubAllocGpuMemory, ///< This callback is to inform of suballocation from base GPU memory allocation.
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SubFreeGpuMemory, ///< This callback is to inform that GPU memory suballocation has been freed.
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#if PAL_DEVELOPER_BUILD
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RpmBlt, ///< This callback is to describe the internal RPM blt calls.
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#endif
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Count, ///< The number of info types.
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};
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constexpr uint32 AllCallbackTypesMask = Util::BitfieldGenMask(static_cast<uint32>(CallbackType::Count));
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constexpr uint32 DefaultDisabledCallbackTypes = (1 << static_cast<uint32>(CallbackType::BindGpuMemory)) |
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(1 << static_cast<uint32>(CallbackType::SubAllocGpuMemory)) |
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(1 << static_cast<uint32>(CallbackType::SubFreeGpuMemory));
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constexpr uint32 DefaultEnabledCallbackTypes = AllCallbackTypesMask & ~DefaultDisabledCallbackTypes;
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/// Definition for developer callback.
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///
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/// @param [in] pPrivateData Private data that is installed with the callback for use by the installer.
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/// @param [in] deviceIndex Unique index for the device so that the installer can properly dispatch the event.
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/// @param [in] infoType Information about the callback so the installer can make informed decisions about
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/// what actions to perform.
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/// @param [in] pInfoData Additional data related to the particular callback type.
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typedef void (PAL_STDCALL *Callback)(
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void* pPrivateData,
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const uint32 deviceIndex,
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CallbackType type,
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void* pCbData);
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/// Enumeration describing the different ways GPU memory is allocated.
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enum class GpuMemoryAllocationMethod : uint32
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{
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Unassigned = 0, ///< Unassigned allocation method.
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Normal, ///< Virtual memory allocation (not pinned/peer).
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Pinned, ///< Pinned memory allocation.
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Peer, ///< Peer memory allocation.
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MultiDevice, ///< MultiDevice memory allocation.
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Opened, ///< Shared memory allocation.
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Svm, ///< Shared virtual memory allocation.
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};
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/// Enumeration describing the different Presentation modes an application can take.
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enum class PresentModeType : uint32
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{
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Unknown = 0, ///< When the present mode is not known.
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Flip, ///< when the presentation surface is used directly as the front buffer.
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Composite, ///< When the flipped image is drawn by a window compositor instead
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/// of the application.
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Blit, ///< when the presentation surface is copied to the front buffer.
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};
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/// Information about the presentation mode an application is in.
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struct PresentationModeData
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{
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PresentModeType presentationMode; ///< Information about present mode from above enumeration.
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UniquePresentKey presentKey; ///< Identifies the window/swap chain, etc. used to present.
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};
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/// Information for allocation/deallocation of GPU memory.
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struct GpuMemoryData
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{
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gpusize size; ///< Size, in bytes, of the allocation.
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GpuHeap heap; ///< The first requested heap of the allocation.
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/// Allocation description flags
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struct Flags
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{
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uint32 isClient : 1; ///< This allocation is requested by the client.
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uint32 isFlippable : 1; ///< This allocation is marked as flippable.
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uint32 isUdmaBuffer : 1; ///< This allocation is for a UDMA buffer.
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uint32 isVirtual : 1; ///< This allocation is for virtual memory.
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uint32 isCmdAllocator : 1; ///< This allocation is for a CmdAllocator.
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uint32 isExternal : 1; ///< This allocation is marked as external.
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uint32 buddyAllocated : 1; ///< This allocation is buddy allocated.
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uint32 appRequested : 1; ///< This allocation is Pal internal, but application requested
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uint32 reserved : 24; ///< Reserved for future use.
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} flags; ///< Flags describing the allocation.
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GpuMemoryAllocationMethod allocMethod; ///< Allocation method
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const IGpuMemory* pGpuMemory; ///< Handle to the Pal::IGpuMemory object of this GPU memory allocation
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gpusize offset; ///< Offset, in bytes, of a suballocation within a base allocation. For
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/// base allocations, offset is always zero.
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};
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#if PAL_DEVELOPER_BUILD
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/// PWS acquire point for barrier logger
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#if PAL_CLIENT_INTERFACE_MAJOR_VERSION >= 901
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enum AcquirePoint : uint8
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{
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AcquirePointPfp,
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AcquirePointMe,
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AcquirePointPreShader,
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AcquirePointPreDepth,
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AcquirePointPrePs,
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AcquirePointPreColor,
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AcquirePointEop,
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AcquirePointCount
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};
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#else
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enum class AcquirePoint : uint8
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{
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Pfp = 0,
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Me,
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PreShader,
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PreDepth,
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PrePs,
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PreColor,
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Eop, // Invalid, for internal optimization purpose.
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Count
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};
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#endif
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#endif
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/// Information pertaining to the cache flush/invalidations and stalls performed during barrier execution.
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struct BarrierOperations
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{
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union
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{
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struct
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{
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uint16 eopTsBottomOfPipe : 1; ///< Issue an end-of-pipe event that can be waited on.
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/// When combined with waitOnTs, makes a full pipeline stall.
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uint16 vsPartialFlush : 1; ///< Stall at ME, waiting for all prior VS waves to complete.
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uint16 psPartialFlush : 1; ///< Stall at ME, waiting for all prior PS waves to complete.
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uint16 csPartialFlush : 1; ///< Stall at ME, waiting for all prior CS waves to complete.
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uint16 pfpSyncMe : 1; ///< Stall PFP until ME is at same point in command stream.
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/// flushed/invalidated are specified in the caches bitfield.
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uint16 syncCpDma : 1; ///< Issue dummy cpDma command to confirm all prior cpDmas have
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/// completed.
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uint16 eosTsPsDone : 1; ///< Issue an end-of-pixel-shader event that can be waited on.
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uint16 eosTsCsDone : 1; ///< Issue an end-of-compute-shader event that can be waited on
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uint16 waitOnTs : 1; ///< Wait on an timestamp event (EOP or EOS) at the ME.
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/// Which event is not necesarily specified here, though any
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/// that are specified here would be waited on.
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uint16 reserved : 7; ///< Reserved for future use.
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};
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uint16 u16All; ///< Unsigned integer containing all the values.
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} pipelineStalls; ///< Information about pipeline stalls performed.
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union
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{
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struct
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{
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uint16 depthStencilExpand : 1; ///< Decompression of depth/stencil image.
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uint16 htileHiZRangeExpand : 1; ///< Expansion of HTile's HiZ range.
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uint16 depthStencilResummarize : 1; ///< Resummarization of depth stencil.
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uint16 dccDecompress : 1; ///< DCC decompress BLT for color images.
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uint16 fmaskDecompress : 1; ///< Fmask decompression for shader readability.
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uint16 fastClearEliminate : 1; ///< Expand latest specified clear color into pixel data for the fast
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/// cleared color/depth resource.
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uint16 fmaskColorExpand : 1; ///< Completely decompresses the specified color resource.
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uint16 initMaskRam : 1; ///< Memsets uninitialized memory to prepare it for use as
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/// CMask/FMask/DCC/HTile.
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uint16 updateDccStateMetadata : 1; ///< DCC state metadata was updated.
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uint16 reserved : 7; ///< Reserved for future use.
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};
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uint16 u16All; ///< Unsigned integer containing all the values.
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} layoutTransitions; ///< Information about layout translation performed.
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union
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{
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struct
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{
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uint16 invalTcp : 1; ///< Invalidate vector caches.
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uint16 invalSqI$ : 1; ///< Invalidate the SQ instruction caches.
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uint16 invalSqK$ : 1; ///< Invalidate the SQ constant caches (scalar caches).
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uint16 flushTcc : 1; ///< Flush L2 cache.
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uint16 invalTcc : 1; ///< Invalidate L2 cache.
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uint16 flushCb : 1; ///< Flush CB caches.
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uint16 invalCb : 1; ///< Invalidate CB caches.
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uint16 flushDb : 1; ///< Flush DB caches.
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uint16 invalDb : 1; ///< Invalidate DB caches.
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uint16 invalCbMetadata : 1; ///< Invalidate CB meta-data cache.
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uint16 flushCbMetadata : 1; ///< Flush CB meta-data cache.
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uint16 invalDbMetadata : 1; ///< Invalidate DB meta-data cache.
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uint16 flushDbMetadata : 1; ///< Flush DB meta-data cache.
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uint16 invalTccMetadata : 1; ///< Invalidate L2 meta-data cache (also called the GLM).
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uint16 invalGl1 : 1; ///< Invalidate the global L1 cache
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uint16 placeholder : 1; ///< Reserved for future use.
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};
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uint16 u16All; ///< Unsigned integer containing all the values.
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} caches; ///< Information about cache operations performed for the barrier.
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#if PAL_DEVELOPER_BUILD
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AcquirePoint acquirePoint;
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#endif
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};
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/// Enumeration for PAL barrier reasons
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enum BarrierReason : uint32
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{
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BarrierReasonInvalid = 0, ///< Invalid barrier reason
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BarrierReasonFirst = 0x80000000, ///< The first valid barrier reason value
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/// The only value that can smaller than this is the
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/// invalid value.
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BarrierReasonLast = 0xbfffffff, ///< The last valid barrier reason value
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/// The only value that can larger than this is the
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/// unknown value.
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BarrierReasonPreComputeColorClear = BarrierReasonFirst, ///< Barrier issued before a color clear
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BarrierReasonPostComputeColorClear, ///< Barrier issued after a color clear
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BarrierReasonPreComputeDepthStencilClear, ///< Barrier issued before a depth/stencil clear
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BarrierReasonPostComputeDepthStencilClear, ///< Barrier issued after a depth/stencil clear
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BarrierReasonMlaaResolveEdgeSync, ///< Barrier issued to sync mlaa edge calculations
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BarrierReasonAqlWaitForParentKernel, ///< Barrier issued to wait for the parent kernel to
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/// complete in an AQL submission
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BarrierReasonAqlWaitForChildrenKernels, ///< Barrier issued to wait for the children kernels to
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/// complete in an AQL submission
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BarrierReasonP2PBlitSync, ///< Barrier issued to synchronize peer-to-peer blits
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BarrierReasonTimeGraphGrid, ///< Barrier issued to wait for the time graph grid
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BarrierReasonTimeGraphGpuLine, ///< Barrier issued to wait for the time graph gpu line
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BarrierReasonDebugOverlayText, ///< Barrier issued to wait for the debug overlay text
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BarrierReasonDebugOverlayGraph, ///< Barrier issued to wait for the debug overlay graph
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BarrierReasonDevDriverOverlay, ///< Barrier issued to wait for developer driver overlay
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BarrierReasonDmaImgScanlineCopySync, ///< Barrier issued to synchronize between image scanline
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/// copies on the dma hardware
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BarrierReasonPostSqttTrace, ///< Barrier issued to wait for work from an sqtt trace
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BarrierReasonPrePerfDataCopy, ///< Barrier issued to wait for perf data to become
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/// available for copy
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BarrierReasonFlushL2CachedData, ///< Barrier issued to flush L2 cached data to main memory
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BarrierReasonResolveImage, ///< Barrier issued before and after resolve image shader
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BarrierReasonPerPixelCopy, ///< Barrier issued between CS copy and per-pixel copy steps
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BarrierReasonGenerateMipmaps, ///< Barrier issued between generating mip levels
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/// Newly defined barrier reasons should be before this one.
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BarrierReasonInternalLastDefined, ///< Only used for asserts.
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BarrierReasonUnknown = 0xFFFFFFFF, ///< Unknown barrier reason
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/// Backwards compatibility reasons
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BarrierReasonPreSyncClear = BarrierReasonPreComputeColorClear,
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BarrierReasonPostSyncClear = BarrierReasonPostComputeColorClear
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};
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/// Style of barrier
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enum class BarrierType : uint32
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{
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Full = 0, ///< A traditional blocking barrier.
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Release, ///< A pipelined barrier that flushes caches and starts transitions.
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Acquire, ///< A barrier that waits on previous 'Release' barriers.
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Count
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};
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/// Information for barrier executions.
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struct BarrierData
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{
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ICmdBuffer* pCmdBuffer; ///< The command buffer that is executing the barrier.
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#if PAL_CLIENT_INTERFACE_MAJOR_VERSION >= 902
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ImgBarrier transition; ///< The particular image barrier with layout transition blt that is currently
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/// executing, only used during a CallbackType::ImageBarrier.
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#else
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BarrierTransition transition; ///< The particular transition with layout transition blt that is currently
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/// executing, only used during a CallbackType::ImageBarrier.
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#endif
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bool hasTransition; ///< Whether or not the transition structure is populated.
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BarrierOperations operations; ///< Detailed cache and pipeline operations performed during this barrier execution
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uint32 reason; ///< Reason that the barrier was invoked. Only filled at BarrierBegin.
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BarrierType type; ///< What style of barrier this is. Only filled at BarrierBegin.
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};
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#if PAL_CLIENT_INTERFACE_MAJOR_VERSION < 888
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/// Enumeration describing the different types of tile mode dimensions
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enum class Gfx6ImageTileModeDimension : uint32
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{
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Linear = 0, ///< Linear tile mode.
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Dim1d, ///< 1D tile mode.
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Dim2d, ///< 2D tile mode.
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Dim3d, ///< 3D tile mode.
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};
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/// Tile mode information
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struct Gfx6ImageTileMode
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{
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Gfx6ImageTileModeDimension dimension; ///< Dimensionality of tile mode.
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union
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{
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struct
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{
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uint32 prt : 1; ///< Image is a PRT.
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uint32 thin : 1; ///< Thin tiled.
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uint32 thick : 1; ///< Thick tiled.
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uint32 reserved : 29; ///< Reserved for future use.
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};
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uint32 u32All; ///< Flags packed as 32-bit uint.
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} properties; ///< Bitfield of properties
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};
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/// Enumeration describing the different tile types
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enum class Gfx6ImageTileType : uint32
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{
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Displayable = 0, ///< Displayable tiling.
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NonDisplayable, ///< Non-displayable tiling.
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DepthSampleOrder, ///< Same as non-displayable plus depth-sample-order.
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Rotated, ///< Rotated displayable tiling.
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Thick, ///< Thick micro-tiling.
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};
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#endif
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/// Meta-data-related properties
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struct ImageMetaDataInfo
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{
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union
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{
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struct
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{
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uint32 color : 1; ///< Flag indicates this is a color buffer.
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uint32 depth : 1; ///< Flag indicates this is a depth/stencil buffer.
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uint32 stencil : 1; ///< Flag indicates this is a stencil buffer.
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uint32 texture : 1; ///< Flag indicates this is a texture.
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uint32 cube : 1; ///< Flag indicates this is a cubemap.
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uint32 volume : 1; ///< Flag indicates this is a volume texture.
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uint32 fmask : 1; ///< Flag indicates this is an fmask.
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uint32 compressZ : 1; ///< Flag indicates z buffer is compressed.
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uint32 overlay : 1; ///< Flag indicates this is an overlay surface.
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uint32 noStencil : 1; ///< Flag indicates this depth has no separate stencil.
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uint32 display : 1; ///< Flag indicates this should match display controller req.
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uint32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space
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/// i.e. save some memory but may lose performance.
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uint32 prt : 1; ///< Flag for partially resident texture.
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uint32 tcCompatible : 1; ///< Image's metadata is TC-compatible. This reduces the maximum
|
|
/// compression levels, but allows the shader to read the data without
|
|
/// an expensive decompress operation.
|
|
uint32 dccCompatible : 1; ///< GFX 8: whether to make MSAA surface support dcc fast clear.
|
|
uint32 dccPipeWorkaround : 1; ///< GFX 8: whether to workaround the HW limit that
|
|
/// dcc can't be enabled if pipe config of tile mode
|
|
/// is different from that of ASIC.
|
|
uint32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear.
|
|
uint32 reserved : 15; ///< Reserved for future use.
|
|
};
|
|
uint32 u32All; ///< Flags packed as 32-bit uint.
|
|
} properties; ///< Bitfield of properties
|
|
};
|
|
|
|
/// Information for allocation of a PAL Image - AddrLib surface info.
|
|
struct ImageDataAddrMgrSurfInfo
|
|
{
|
|
#if PAL_CLIENT_INTERFACE_MAJOR_VERSION < 888
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
Gfx6ImageTileMode mode; ///< Tile mode.
|
|
Gfx6ImageTileType type; ///< Micro tiling type.
|
|
} gfx6;
|
|
struct
|
|
{
|
|
uint32 swizzle; ///< Swizzle mode.
|
|
} gfx9;
|
|
} tiling;
|
|
#endif
|
|
|
|
ImageMetaDataInfo flags; ///< Metadata info.
|
|
uint32 swizzle; ///< HW-specific swizzle mode.
|
|
uint64 size; ///< Surface size, in bytes.
|
|
uint32 bpp; ///< Bits per pixel.
|
|
uint32 width; ///< Width.
|
|
uint32 height; ///< Height.
|
|
uint32 depth; ///< Depth.
|
|
};
|
|
|
|
/// Type of surface for which the register data is being provided
|
|
enum class SurfRegDataType : uint32
|
|
{
|
|
RenderTargetView, ///< Render Target View information.
|
|
};
|
|
|
|
/// Information for surface addresses for a SurfRegData callback
|
|
struct SurfRegDataInfo
|
|
{
|
|
SurfRegDataType type; ///< Type of surface to which the register data corresponds.
|
|
uint32 regData; ///< Hardware-specific register data for the specific surface type.
|
|
};
|
|
|
|
/// Type of draw or dispatch operation for a DrawDispatch callback
|
|
enum class DrawDispatchType : uint32
|
|
{
|
|
CmdDraw = 0, ///< Auto-indexed draw.
|
|
CmdDrawOpaque, ///< Auto draw.
|
|
CmdDrawIndexed, ///< Indexed draw.
|
|
CmdDrawIndirectMulti, ///< (Multi) indirect draw.
|
|
CmdDrawIndexedIndirectMulti, ///< (Multi) indirect indexed draw.
|
|
CmdDispatchMesh, ///< Task/Mesh shader dispatch.
|
|
CmdDispatchMeshIndirectMulti, ///< Indirect Task/Mesh shader dispatch.
|
|
CmdGenExecuteIndirectDraw, ///< ExecuteIndirect draw.
|
|
CmdGenExecuteIndirectDrawIndexed, ///< ExecuteIndirect indexed draw.
|
|
CmdGenExecuteIndirectDispatchMesh, ///< ExecuteIndirect Task/Mesh shader dispatch.
|
|
CmdDispatch, ///< Direct compute dispatch.
|
|
CmdDispatchAce, ///< Direct Compute dispatch through implicit ganged-submit ACE stream.
|
|
CmdDispatchIndirect, ///< Indirect compute dispatch.
|
|
CmdDispatchOffset, ///< Direct compute dispatch (offsetted start).
|
|
CmdGenExecuteIndirectDispatch, ///< ExecuteIndirect dispatch.
|
|
CmdDispatchAql, ///< AQL compute dispatch
|
|
|
|
Count,
|
|
FirstDispatch = CmdDispatch ///< All callbacks with an enum value greater or equal than this are dispatches
|
|
};
|
|
|
|
/// Draw-specific information for DrawDispatch callbacks
|
|
struct DrawDispatchDrawArgs
|
|
{
|
|
/// Contains information about user data register indices for certain draw parameter state.
|
|
/// Some of these values may not be available for all draws on all clients, and in such
|
|
/// cases the value will be UINT_MAX.
|
|
struct
|
|
{
|
|
uint32 firstVertex; ///< Vertex offset (first vertex) user data register index
|
|
uint32 instanceOffset; ///< Instance offset (start instance) user data register index
|
|
uint32 drawIndex; ///< Draw ID SPI user data register index
|
|
} userDataRegs;
|
|
};
|
|
|
|
/// Dispatch-specific information for DrawDispatch callbacks
|
|
struct DrawDispatchDispatchArgs
|
|
{
|
|
DispatchDims groupStart; ///< Thread/workgroup start offsets in X/Y/Z dimensions. Only valid for CmdDispatchOffset.
|
|
DispatchDims groupDims; ///< Thread/workgroup counts in X/Y/Z dimensions. Only valid for CmdDispatch[Offset].
|
|
DispatchDims logicalSize; ///< Thread/workgroup counts as seen by the shader. Only valid for CmdDispatchOffset.
|
|
/// Optional flags to help the client driver understand the dispatch.
|
|
/// For example, if the dispatch originated in PAL rather than the client driver.
|
|
DispatchInfoFlags infoFlags;
|
|
};
|
|
|
|
/// Information for DrawDispatch callbacks
|
|
struct DrawDispatchData
|
|
{
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer that is recording this command
|
|
DrawDispatchType cmdType; ///< Draw/dispatch command type. This influences which sub-structure below is valid.
|
|
|
|
union
|
|
{
|
|
/// Draw-specific parameters. Valid when cmdType is CmdDraw*.
|
|
DrawDispatchDrawArgs draw;
|
|
|
|
/// Dispatch-specific parameters. Valid when cmdType is CmdDispatch*
|
|
DrawDispatchDispatchArgs dispatch;
|
|
};
|
|
|
|
/// If the handler of this callback inserts an RGP trace marker using ICmdBuffer::CmdInsertRgpTraceMarker(),
|
|
/// these flags should be passed to that call to control which sub-queue(s) in the command buffer should insert
|
|
/// the marker.
|
|
RgpMarkerSubQueueFlags subQueueFlags;
|
|
};
|
|
|
|
/// Information for BindPipeline callbacks
|
|
struct BindPipelineData
|
|
{
|
|
const IPipeline* pPipeline; ///< The currently-bound pipeline
|
|
const PipelineInfo* pPipelineInfo; ///< General information about the bound pipeline
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer that is recording this command
|
|
uint64 apiPsoHash; ///< The hash to correlate APIs and corresponding PSOs.
|
|
PipelineBindPoint bindPoint; ///< The bind point of the pipeline within a queue.
|
|
|
|
/// If the handler of this callback inserts an RGP trace marker using ICmdBuffer::CmdInsertRgpTraceMarker(),
|
|
/// these flags should be passed to that call to control which sub-queue(s) in the command buffer should insert
|
|
/// the marker.
|
|
RgpMarkerSubQueueFlags subQueueFlags;
|
|
};
|
|
|
|
#if PAL_DEVELOPER_BUILD
|
|
/// Information for DrawDispatchValidation callbacks
|
|
struct DrawDispatchValidationData
|
|
{
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer which is recording the triggering draw or dispatch.
|
|
uint32 userDataCmdSize; ///< Size of PM4 commands used to validate the current user-data entries (bytes).
|
|
uint32 miscCmdSize; ///< Size of PM4 commands for all other draw- or dispatch-time validation (bytes).
|
|
};
|
|
|
|
// Information for BindPipelineValidation callbacks
|
|
struct BindPipelineValidationData
|
|
{
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer which is recording the triggering draw or dispatch.
|
|
uint32 pipelineCmdSize; ///< Size of PM4 commands used to validate the current pipeline state (bytes).
|
|
};
|
|
|
|
/// Information for OptimizedRegisters callbacks
|
|
struct OptimizedRegistersData
|
|
{
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer which is recording the triggering PM4 stream.
|
|
/// Array containing the number of times the PM4 optimizer saw a SET packet which modified each register
|
|
const uint32* pShRegSeenSets;
|
|
///< Array containing the number of times the PM4 optimizer kept a SET packet which modified each register
|
|
const uint32* pShRegKeptSets;
|
|
uint32 shRegCount; ///< Number of SH registers
|
|
uint16 shRegBase; ///< Base address of SH registers
|
|
/// Array containing the number of times the PM4 optimizer saw a SET or RMW packet which modified each register
|
|
const uint32* pCtxRegSeenSets;
|
|
///< Array containing the number of times the PM4 optimizer kept a SET or RMW packet which modified each register
|
|
const uint32* pCtxRegKeptSets;
|
|
uint32 ctxRegCount; ///< Number of context registers
|
|
uint16 ctxRegBase; ///< Base address of context registers
|
|
};
|
|
|
|
/// Internal RPM blt type
|
|
enum class RpmBltType : uint32
|
|
{
|
|
CpDmaCopy = 0,
|
|
CpDmaUpdate,
|
|
Draw,
|
|
Dispatch,
|
|
|
|
Count
|
|
};
|
|
|
|
/// Describes the RPM blt call
|
|
struct RpmBltData
|
|
{
|
|
ICmdBuffer* pCmdBuffer; ///< The command buffer that is executing the blt.
|
|
RpmBltType bltType; ///< Type of RPM blt, @ref RpmBltType.
|
|
};
|
|
#endif
|
|
|
|
/// Describes the binding of a GPU Memory object to a resource
|
|
struct BindGpuMemoryData
|
|
{
|
|
const void* pObj; ///< Opaque pointer to the resource having memory bound to it.
|
|
gpusize requiredGpuMemSize; ///< GPU memory size required by pObj.
|
|
const IGpuMemory* pGpuMemory; ///< IGpuMemory object being bound to the resource.
|
|
gpusize offset; ///< Offset within pGpuMemory where the resource is being bound.
|
|
bool isSystemMemory; ///< If true then system memory is being bound to the object. In this case,
|
|
/// pGpuMemory and offset should be set to zero.
|
|
};
|
|
|
|
/// Describes an user marker operation
|
|
enum class UserMarkerOpType : uint8
|
|
{
|
|
Invalid = 0, ///< Invalid user marker operation
|
|
Push, ///< Push user marker operation
|
|
Pop, ///< Pop user marker operation
|
|
Set ///< Set user marker operation
|
|
};
|
|
|
|
/// Describes an user marker operation, used in UserMarkerHistoryTraceSource
|
|
struct UserMarkerOpInfo
|
|
{
|
|
union
|
|
{
|
|
struct
|
|
{
|
|
uint32 opType : 2; ///< UserMarkerOpType
|
|
uint32 strIndex : 30; ///< Index of the user marker in the in corresponding string table
|
|
};
|
|
uint32 u32All;
|
|
};
|
|
};
|
|
|
|
} // Developer
|
|
} // Pal
|