German Andryeyev 1086195745 SWDEV-268381 - Enable wait on CPU before SDMA transfer ...

- There is a performance regression with a HW wait for HSA signal
on ROCr async operation. For now move the logic back to CPU wait.

- Fix profiling issue with multiple HSA signal per single timestamp
object. Some copies require multiple ROCR calls and if profiling is
required, then the execution time is derived from all used signals.

Change-Id: Id003e4abb8c2de378eedc152a7e389500fc6f4ce


[ROCm/clr commit: 5a8946190a]

2021-01-19 18:24:21 -05:00

..

clr/rocclr

SWDEV-268381 - Enable wait on CPU before SDMA transfer

2021-01-19 18:24:21 -05:00