JoseSantosAMD
2d1f73ad11
* updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * Adding generate workloads script Signed-off-by: Jose Santos <josantos@amd.com> * Changing output workloads dir in shell script Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: Jose Santos <josantos@amd.com>
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_1 | obj_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | SQ_INSTS_VSKIPPED | SQ_INSTS_SMEM | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_2 | obj_2 | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | SQ_INSTS | SQ_WAIT_ANY | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_3 | obj_3 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_4 | obj_4 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_5 | obj_5 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_BUSY_CU_CYCLES | SQ_WAVES | SQ_WAVE_CYCLES | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | SQC_TC_DATA_WRITE_REQ | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_6 | obj_6 | TCC_EA_ATOMIC_LEVEL_sum | wave_size_7 | obj_7 | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | wave_size_8 | obj_8 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_9 | obj_9 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | SQ_INSTS_SMEM_NORM | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | wave_size_10 | obj_10 | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | TCC_EA_RDREQ_DRAM_sum | wave_size_11 | obj_11 | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_INSTS_VALU | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_WRREQ_IO_CREDIT_STALL_sum | TCC_EA_WRREQ_GMI_CREDIT_STALL_sum | TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum | wave_size_12 | obj_12 | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_13 | obj_13 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_14 | obj_14 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_15 | obj_15 | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | SQC_DCACHE_REQ_READ_1 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_16 | obj_16 | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_EA_RDREQ_IO_CREDIT_STALL_sum | TCC_EA_RDREQ_GMI_CREDIT_STALL_sum | TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum | TCC_TAG_STALL_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f12bd3f8e80 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 0 | 48475 | 0 | 0 | 64 | 0x7f2ee4d8ae80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 913 | 46676 | 0 | 131457.0 | 131072.0 | 0.0 | 131104.0 | 64 | 0x7f723da44e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 23245492 | 960.0 | 513958.0 | 0.0 | 524288.0 | 864612.0 | 32768.0 | 0 | 0 | 0 | 16688 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7f765377ce80 | 3803 | 0 | 0 | 2050751 | 2948 | 0 | 0 | 1907601 | 4438 | 0 | 0 | 2009672 | 2506 | 0 | 0 | 1846516 | 3553 | 0 | 0 | 2063265 | 3122 | 0 | 0 | 2001634 | 6281 | 0 | 0 | 2188123 | 4631 | 0 | 0 | 1971154 | 4775 | 0 | 0 | 2093927 | 3614 | 0 | 0 | 2007124 | 4597 | 0 | 0 | 2016215 | 2488 | 0 | 0 | 1868344 | 7225 | 0 | 0 | 2333755 | 5246 | 0 | 0 | 2154204 | 3683 | 0 | 0 | 1825353 | 3452 | 0 | 0 | 1954749 | 2750 | 0 | 0 | 1912391 | 2426 | 0 | 0 | 1905874 | 5256 | 0 | 0 | 2058377 | 3648 | 0 | 0 | 1922036 | 1547 | 0 | 0 | 1801613 | 4405 | 0 | 0 | 2005810 | 4918 | 0 | 0 | 2077046 | 4546 | 0 | 0 | 2032713 | 3648 | 0 | 0 | 1924672 | 3039 | 0 | 0 | 1873915 | 4101 | 0 | 0 | 1915983 | 3887 | 0 | 0 | 1981375 | 2121 | 0 | 0 | 1900717 | 3129 | 0 | 0 | 1907824 | 3754 | 0 | 0 | 1946808 | 4578 | 0 | 0 | 2009432 | 64 | 0x7f6deb08ae80 | 0 | 4045610 | 4096 | 4096 | 0 | 2754344 | 4096 | 4096 | 0 | 3323405 | 4096 | 4096 | 0 | 3527872 | 4096 | 4096 | 0 | 3406980 | 4096 | 4096 | 0 | 3174374 | 4096 | 4096 | 0 | 3334181 | 4096 | 4096 | 0 | 3509505 | 4096 | 4096 | 0 | 3404632 | 4096 | 4096 | 0 | 3215697 | 4096 | 4096 | 0 | 3347082 | 4096 | 4096 | 0 | 3380165 | 4096 | 4096 | 0 | 3376779 | 4096 | 4096 | 0 | 3101938 | 4096 | 4096 | 0 | 3610518 | 4096 | 4096 | 0 | 3756848 | 4096 | 4096 | 0 | 3674020 | 4096 | 4096 | 0 | 3557150 | 4096 | 4096 | 0 | 3976795 | 4096 | 4096 | 0 | 3370194 | 4096 | 4096 | 0 | 2932604 | 4096 | 4096 | 0 | 4858757 | 4096 | 4096 | 0 | 3944008 | 4096 | 4096 | 0 | 3434283 | 4096 | 4096 | 0 | 3246129 | 4096 | 4096 | 0 | 3538331 | 4096 | 4096 | 0 | 3852946 | 4096 | 4096 | 0 | 3229022 | 4096 | 4096 | 0 | 3290823 | 4096 | 4096 | 0 | 3388016 | 4096 | 4096 | 0 | 3514130 | 4096 | 4096 | 0 | 3292753 | 4096 | 4096 | 64 | 0x7fb825d5ee80 | 390992 | 235328 | 3440250 | 16384 | 25374933 | 144 | 48 | 0 | 48873 | 48873 | 3882836.0 | 2994659.0 | 6362.0 | 1019222.0 | 2059199.0 | 0.0 | 2985375.0 | 2674492.0 | 389279 | 245268 | 48873 | 0 | 48873 | 0 | 1563936.0 | 956160.0 | 0.0 | 0.0 | 64 | 0x7fe2687fce80 | 0.0 | 64 | 0x7f828a3bce80 | 131072.0 | 131072.0 | 0.0 | 2463975.0 | 0.0 | 0.0 | 103714313.0 | 62067519.0 | 64 | 0x7f07ae27ee80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8336 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f66a97eae80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86451.0 | 44621.0 | 131111.0 | 0.0 | 64 | 0x7f065ce4ce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131350.0 | 0.0 | 548.0 | 131349.0 | 64 | 0x7f4dc183ae80 | 1333803 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 72411040.0 | 189696272.0 | 76711798.0 | 131072.0 | 0.0 | 555164.0 | 0 | 0 | 25978 | 106998.0 | 0.0 | 0.0 | 106998.0 | 64 | 0x7f945a6c2e80 | 0 | 0 | 192 | 0 | 65536 | 64488 | 48 | 1338 | 31834 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 539 | 48479 | 1751 | 0 | 48.0 | 264.0 | 0.0 | 262288.0 | 64 | 0x7f13640cae80 | 4096 | 0 | 753 | 0 | 4096 | 0 | 1566 | 0 | 4096 | 0 | 1776 | 0 | 4099 | 0 | 74 | 0 | 4096 | 0 | 222 | 0 | 4096 | 0 | 400 | 0 | 4096 | 0 | 893 | 0 | 4096 | 0 | 2135 | 0 | 4096 | 0 | 357 | 0 | 4096 | 0 | 1004 | 0 | 4096 | 0 | 1223 | 0 | 4096 | 0 | 1793 | 0 | 4096 | 0 | 1361 | 0 | 4096 | 0 | 74 | 0 | 4096 | 0 | 843 | 0 | 4367 | 0 | 4956 | 0 | 4096 | 0 | 2375 | 0 | 4096 | 0 | 1645 | 0 | 4144 | 0 | 1991 | 0 | 4096 | 0 | 2263 | 0 | 4096 | 0 | 1389 | 0 | 4096 | 0 | 450 | 0 | 4096 | 0 | 714 | 0 | 4096 | 0 | 21 | 0 | 4096 | 0 | 2600 | 0 | 4096 | 0 | 1004 | 0 | 4096 | 0 | 427 | 0 | 4144 | 0 | 441 | 0 | 4096 | 0 | 3006 | 0 | 4096 | 0 | 554 | 0 | 4096 | 0 | 850 | 0 | 4217 | 0 | 763 | 0 | 64 | 0x7fa388310e80 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 141 | 8195 | 4240 | 8336 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8431 | 4335 | 8431 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7f052e260e80 | 189671 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13199 | 29583 | 10023 | 550 | 0 | 46827 | 262552.0 | 0.0 | 188.0 | 262364.0 | 64 | 0x7fabca440e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 25189.0 | 98683.0 | 2187927658864610 | 2187927658888930 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f12bd3f8e80 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 0 | 43227 | 0 | 0 | 64 | 0x7f2ee4d8ae80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 240.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 7127 | 45750 | 1071 | 131850.0 | 131072.0 | 0.0 | 116749.0 | 64 | 0x7f723da44e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22801818 | 960.0 | 514040.0 | 0.0 | 524288.0 | 884750.0 | 32768.0 | 0 | 0 | 0 | 13892 | 86738.0 | 86738.0 | 0.0 | 86738.0 | 64 | 0x7f765377ce80 | 4435 | 0 | 0 | 1660266 | 4059 | 0 | 0 | 1603955 | 3778 | 0 | 0 | 1673562 | 3475 | 0 | 0 | 1529857 | 1747 | 0 | 0 | 1406300 | 3331 | 0 | 0 | 1566248 | 3043 | 0 | 0 | 1533691 | 3761 | 0 | 0 | 1738262 | 4105 | 0 | 0 | 1631101 | 3849 | 0 | 0 | 1628099 | 2862 | 0 | 0 | 1531975 | 2602 | 0 | 0 | 1466753 | 4795 | 0 | 0 | 1660650 | 5820 | 0 | 0 | 1792830 | 1765 | 0 | 0 | 1365104 | 2671 | 0 | 0 | 1503614 | 4432 | 0 | 0 | 1701802 | 2982 | 0 | 0 | 1491383 | 5058 | 0 | 0 | 1769697 | 4246 | 0 | 0 | 1699349 | 4080 | 0 | 0 | 1606513 | 3500 | 0 | 0 | 1591112 | 4331 | 0 | 0 | 1625843 | 4137 | 0 | 0 | 1624402 | 3371 | 0 | 0 | 1460907 | 3916 | 0 | 0 | 1553880 | 3278 | 0 | 0 | 1514425 | 4048 | 0 | 0 | 1612443 | 2810 | 0 | 0 | 1534713 | 5500 | 0 | 0 | 1720567 | 4236 | 0 | 0 | 1676296 | 3276 | 0 | 0 | 1548912 | 64 | 0x7f6deb08ae80 | 0 | 4036927 | 2710 | 2710 | 0 | 3683883 | 2700 | 2700 | 0 | 3183247 | 2656 | 2656 | 0 | 3070843 | 2738 | 2738 | 0 | 3626307 | 2684 | 2684 | 0 | 3430827 | 2724 | 2724 | 0 | 3525718 | 2681 | 2681 | 0 | 3734955 | 2730 | 2730 | 0 | 3318904 | 2720 | 2720 | 0 | 3553739 | 2721 | 2721 | 0 | 3181715 | 2704 | 2704 | 0 | 3657438 | 2742 | 2742 | 0 | 3860523 | 2728 | 2728 | 0 | 3850930 | 2698 | 2698 | 0 | 3500847 | 2682 | 2682 | 0 | 3602211 | 2744 | 2744 | 0 | 3885341 | 2688 | 2688 | 0 | 3820603 | 2752 | 2752 | 0 | 3491388 | 2691 | 2691 | 0 | 3800725 | 2748 | 2748 | 0 | 3572555 | 2704 | 2704 | 0 | 4944388 | 2776 | 2776 | 0 | 3322215 | 2652 | 2652 | 0 | 3258427 | 2700 | 2700 | 0 | 3445778 | 2676 | 2676 | 0 | 3488305 | 2727 | 2727 | 0 | 3359497 | 2672 | 2672 | 0 | 2988778 | 2726 | 2726 | 0 | 3187009 | 2708 | 2708 | 0 | 3456296 | 2700 | 2700 | 0 | 3435387 | 2701 | 2701 | 0 | 3798215 | 2714 | 2714 | 64 | 0x7fb825d5ee80 | 355176 | 236794 | 3460725 | 16384 | 25071742 | 0 | 48 | 0 | 44396 | 44396 | 3841500.0 | 3083567.0 | 7562.0 | 1177895.0 | 2062339.0 | 0.0 | 3074189.0 | 2763113.0 | 355168 | 246131 | 44396 | 0 | 44396 | 0 | 1420672.0 | 826304.0 | 0.0 | 0.0 | 64 | 0x7fe2687fce80 | 0.0 | 64 | 0x7f828a3bce80 | 131072.0 | 131072.0 | 0.0 | 2533366.0 | 0.0 | 0.0 | 100543267.0 | 48215300.0 | 64 | 0x7f07ae27ee80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f66a97eae80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 70450.0 | 16338.0 | 82263.0 | 0.0 | 64 | 0x7f065ce4ce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131273.0 | 0.0 | 400.0 | 131272.0 | 64 | 0x7f4dc183ae80 | 241651 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 74133268.0 | 204464778.0 | 78437280.0 | 131072.0 | 0.0 | 636199.0 | 0 | 0 | 23740 | 50376.0 | 0.0 | 0.0 | 50376.0 | 64 | 0x7f945a6c2e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 30908 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 457 | 42350 | 1684 | 0 | 48.0 | 270.0 | 0.0 | 262144.0 | 64 | 0x7f13640cae80 | 4096 | 0 | 538 | 0 | 4096 | 0 | 180 | 0 | 4096 | 0 | 3991 | 0 | 4096 | 0 | 210 | 0 | 4096 | 0 | 1849 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 1310 | 0 | 4096 | 0 | 0 | 0 | 4098 | 0 | 1131 | 0 | 4096 | 0 | 1347 | 0 | 4097 | 0 | 2559 | 0 | 4096 | 0 | 2430 | 0 | 4096 | 0 | 143 | 0 | 4096 | 0 | 278 | 0 | 4096 | 0 | 3293 | 0 | 4315 | 0 | 4328 | 0 | 4096 | 0 | 1154 | 0 | 4096 | 0 | 402 | 0 | 4144 | 0 | 2784 | 0 | 4096 | 0 | 3052 | 0 | 4096 | 0 | 467 | 0 | 4096 | 0 | 101 | 0 | 4096 | 0 | 2197 | 0 | 4096 | 0 | 233 | 0 | 4096 | 0 | 153 | 0 | 4096 | 0 | 125 | 0 | 4096 | 0 | 1703 | 0 | 4144 | 0 | 317 | 0 | 4096 | 0 | 881 | 0 | 4096 | 0 | 245 | 0 | 4099 | 0 | 397 | 0 | 4217 | 0 | 0 | 0 | 64 | 0x7fa388310e80 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8403 | 4307 | 8403 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7f052e260e80 | 188744 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13436 | 29820 | 8486 | 2567 | 0 | 40349 | 262412.0 | 0.0 | 47.0 | 262365.0 | 64 | 0x7fabca440e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 71629.0 | 150071.0 | 2187927658989730 | 2187927659008610 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f12bd3f8e80 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 0 | 42896 | 0 | 0 | 64 | 0x7f2ee4d8ae80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 4098 | 38321 | 0 | 131315.0 | 131072.0 | 0.0 | 86584.0 | 64 | 0x7f723da44e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22387728 | 960.0 | 513941.0 | 0.0 | 524288.0 | 888268.0 | 32768.0 | 0 | 0 | 0 | 14588 | 86632.0 | 86632.0 | 0.0 | 86632.0 | 64 | 0x7f765377ce80 | 3527 | 0 | 0 | 1522569 | 2677 | 0 | 0 | 1424653 | 3316 | 0 | 0 | 1437550 | 4607 | 0 | 0 | 1625227 | 2178 | 0 | 0 | 1438530 | 2519 | 0 | 0 | 1518288 | 3340 | 0 | 0 | 1611803 | 4969 | 0 | 0 | 1731968 | 3270 | 0 | 0 | 1552064 | 2818 | 0 | 0 | 1511385 | 3180 | 0 | 0 | 1417421 | 3638 | 0 | 0 | 1589113 | 2443 | 0 | 0 | 1452583 | 2254 | 0 | 0 | 1456660 | 3278 | 0 | 0 | 1453422 | 4205 | 0 | 0 | 1641308 | 3123 | 0 | 0 | 1531545 | 2385 | 0 | 0 | 1438183 | 4749 | 0 | 0 | 1677203 | 3548 | 0 | 0 | 1485085 | 3079 | 0 | 0 | 1452001 | 3904 | 0 | 0 | 1608432 | 3098 | 0 | 0 | 1564134 | 4573 | 0 | 0 | 1637351 | 3476 | 0 | 0 | 1469354 | 3591 | 0 | 0 | 1536708 | 3897 | 0 | 0 | 1555865 | 4468 | 0 | 0 | 1655286 | 1227 | 0 | 0 | 1355103 | 6129 | 0 | 0 | 1791661 | 4356 | 0 | 0 | 1630443 | 3432 | 0 | 0 | 1559875 | 64 | 0x7f6deb08ae80 | 0 | 4547015 | 2742 | 2742 | 0 | 3300216 | 2706 | 2706 | 0 | 4210457 | 2684 | 2684 | 0 | 3897271 | 2680 | 2680 | 0 | 3856939 | 2672 | 2672 | 0 | 3568738 | 2746 | 2746 | 0 | 3854516 | 2691 | 2691 | 0 | 3820386 | 2692 | 2692 | 0 | 4194161 | 2708 | 2708 | 0 | 3479657 | 2718 | 2718 | 0 | 3561451 | 2686 | 2686 | 0 | 4232110 | 2670 | 2670 | 0 | 3661315 | 2734 | 2734 | 0 | 3321032 | 2732 | 2732 | 0 | 3949113 | 2707 | 2707 | 0 | 3759284 | 2656 | 2656 | 0 | 3612117 | 2732 | 2732 | 0 | 3700399 | 2726 | 2726 | 0 | 3729587 | 2678 | 2678 | 0 | 3327015 | 2712 | 2712 | 0 | 3625581 | 2698 | 2698 | 0 | 4476780 | 2765 | 2765 | 0 | 4233949 | 2698 | 2698 | 0 | 3760499 | 2698 | 2698 | 0 | 3607673 | 2700 | 2700 | 0 | 3290136 | 2718 | 2718 | 0 | 3458330 | 2722 | 2722 | 0 | 3564144 | 2688 | 2688 | 0 | 4334022 | 2704 | 2704 | 0 | 3388638 | 2728 | 2728 | 0 | 3530672 | 2690 | 2690 | 0 | 3593272 | 2676 | 2676 | 64 | 0x7fb825d5ee80 | 343248 | 230566 | 3373952 | 16384 | 24814803 | 0 | 48 | 0 | 42905 | 42905 | 3748388.0 | 3007908.0 | 7725.0 | 1100199.0 | 2106009.0 | 0.0 | 2999174.0 | 2688771.0 | 343240 | 240043 | 42905 | 0 | 42905 | 0 | 1372960.0 | 808808.0 | 0.0 | 0.0 | 64 | 0x7fe2687fce80 | 0.0 | 64 | 0x7f828a3bce80 | 131072.0 | 131072.0 | 0.0 | 2339866.0 | 0.0 | 0.0 | 86391680.0 | 45120910.0 | 64 | 0x7f07ae27ee80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f66a97eae80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86550.0 | 0.0 | 131112.0 | 0.0 | 64 | 0x7f065ce4ce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131260.0 | 0.0 | 374.0 | 131259.0 | 64 | 0x7f4dc183ae80 | 635880 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 72143762.0 | 187442625.0 | 74842958.0 | 131072.0 | 0.0 | 595381.0 | 0 | 0 | 24262 | 76911.0 | 0.0 | 0.0 | 76911.0 | 64 | 0x7f945a6c2e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 30399 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 457 | 41717 | 1760 | 0 | 48.0 | 270.0 | 0.0 | 262144.0 | 64 | 0x7f13640cae80 | 4096 | 0 | 2464 | 0 | 4096 | 0 | 3459 | 0 | 4096 | 0 | 351 | 0 | 4096 | 0 | 1214 | 0 | 4096 | 0 | 1875 | 0 | 4096 | 0 | 2434 | 0 | 4096 | 0 | 1577 | 0 | 4096 | 0 | 1596 | 0 | 4098 | 0 | 2592 | 0 | 4096 | 0 | 2353 | 0 | 4097 | 0 | 1267 | 0 | 4096 | 0 | 2149 | 0 | 4096 | 0 | 2439 | 0 | 4096 | 0 | 921 | 0 | 4096 | 0 | 1524 | 0 | 4330 | 0 | 2147 | 0 | 4096 | 0 | 1599 | 0 | 4096 | 0 | 2486 | 0 | 4144 | 0 | 1516 | 0 | 4096 | 0 | 1420 | 0 | 4096 | 0 | 1726 | 0 | 4096 | 0 | 1726 | 0 | 4096 | 0 | 837 | 0 | 4096 | 0 | 914 | 0 | 4096 | 0 | 1192 | 0 | 4096 | 0 | 2227 | 0 | 4096 | 0 | 836 | 0 | 4144 | 0 | 1524 | 0 | 4096 | 0 | 1617 | 0 | 4096 | 0 | 1823 | 0 | 4099 | 0 | 512 | 0 | 4217 | 0 | 2180 | 0 | 64 | 0x7fa388310e80 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8433 | 4337 | 8433 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7f052e260e80 | 187070 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 12966 | 29350 | 8623 | 2692 | 0 | 40901 | 262412.0 | 0.0 | 47.0 | 262365.0 | 64 | 0x7fabca440e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 48058.0 | 116690.0 | 2187927659032130 | 2187927659051170 |