JoseSantosAMD
2d1f73ad11
* updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * Adding generate workloads script Signed-off-by: Jose Santos <josantos@amd.com> * Changing output workloads dir in shell script Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: Jose Santos <josantos@amd.com>
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_1 | obj_1 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_2 | obj_2 | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | SQC_DCACHE_REQ_READ_1 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_3 | obj_3 | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | SQ_INSTS | SQ_WAIT_ANY | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_4 | obj_4 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_5 | obj_5 | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | wave_size_6 | obj_6 | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_EA_RDREQ_IO_CREDIT_STALL_sum | TCC_EA_RDREQ_GMI_CREDIT_STALL_sum | TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum | TCC_TAG_STALL_sum | wave_size_7 | obj_7 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | SQ_INSTS_SMEM_NORM | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | wave_size_8 | obj_8 | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_INSTS_VALU | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_WRREQ_IO_CREDIT_STALL_sum | TCC_EA_WRREQ_GMI_CREDIT_STALL_sum | TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum | wave_size_9 | obj_9 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_BUSY_CU_CYCLES | SQ_WAVES | SQ_WAVE_CYCLES | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | SQC_TC_DATA_WRITE_REQ | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_10 | obj_10 | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | TCC_EA_RDREQ_DRAM_sum | wave_size_11 | obj_11 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_12 | obj_12 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | SQ_INSTS_VSKIPPED | SQ_INSTS_SMEM | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_13 | obj_13 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_14 | obj_14 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_15 | obj_15 | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_16 | obj_16 | TCC_EA_ATOMIC_LEVEL_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7fa1427fce80 | 0 | 3878725 | 4096 | 4096 | 0 | 4103994 | 4096 | 4096 | 0 | 3748355 | 4096 | 4096 | 0 | 3797819 | 4096 | 4096 | 0 | 3878923 | 4096 | 4096 | 0 | 3780268 | 4096 | 4096 | 0 | 4067104 | 4096 | 4096 | 0 | 4102862 | 4096 | 4096 | 0 | 3684344 | 4096 | 4096 | 0 | 5017328 | 4096 | 4096 | 0 | 4849838 | 4096 | 4096 | 0 | 4606563 | 4096 | 4096 | 0 | 2843411 | 4096 | 4096 | 0 | 3669854 | 4096 | 4096 | 0 | 4122786 | 4096 | 4096 | 0 | 3692928 | 4096 | 4096 | 0 | 3975208 | 4096 | 4096 | 0 | 5246071 | 4096 | 4096 | 0 | 4837605 | 4096 | 4096 | 0 | 5063441 | 4096 | 4096 | 0 | 3275576 | 4096 | 4096 | 0 | 3660812 | 4096 | 4096 | 0 | 3560743 | 4096 | 4096 | 0 | 4717799 | 4096 | 4096 | 0 | 3593196 | 4096 | 4096 | 0 | 3448332 | 4096 | 4096 | 0 | 3556395 | 4096 | 4096 | 0 | 2943212 | 4096 | 4096 | 0 | 4028854 | 4096 | 4096 | 0 | 3432132 | 4096 | 4096 | 0 | 3456849 | 4096 | 4096 | 0 | 3304151 | 4096 | 4096 | 64 | 0x7f67fc0e0e80 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 0 | 47267 | 0 | 0 | 64 | 0x7f58d6496e80 | 171144 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 11073 | 27457 | 10001 | 550 | 0 | 48037 | 262691.0 | 0.0 | 188.0 | 262503.0 | 64 | 0x7fb6b8cd8e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22342173 | 960.0 | 513969.0 | 0.0 | 524288.0 | 994552.0 | 32768.0 | 0 | 0 | 0 | 16591 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7fd27dddce80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8336 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f989f5ece80 | 131072.0 | 131072.0 | 0.0 | 2263915.0 | 0.0 | 0.0 | 110282773.0 | 63143117.0 | 64 | 0x7f2f9a21ae80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 69777.0 | 135995.0 | 64 | 0x7f133e226e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 87017.0 | 44055.0 | 131112.0 | 0.0 | 64 | 0x7f5f9af14e80 | 2299913 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 69500298.0 | 173495453.0 | 73156049.0 | 131072.0 | 0.0 | 561985.0 | 0 | 0 | 26201 | 72246.0 | 0.0 | 0.0 | 72246.0 | 64 | 0x7f527e452e80 | 394800 | 245008 | 3586455 | 16384 | 26864125 | 144 | 48 | 0 | 49349 | 49349 | 4027696.0 | 3098693.0 | 5214.0 | 1011051.0 | 2213701.0 | 0.0 | 3088540.0 | 2778272.0 | 393279 | 254942 | 49349 | 0 | 49349 | 0 | 1579168.0 | 968348.0 | 0.0 | 0.0 | 64 | 0x7f81736bce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131340.0 | 0.0 | 528.0 | 131339.0 | 64 | 0x7fd1b5a42e80 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8312 | 4216 | 8312 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 141 | 8195 | 4240 | 8336 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 64 | 0x7f85a3448e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 913 | 47372 | 0 | 131528.0 | 131072.0 | 0.0 | 131104.0 | 64 | 0x7f7e31e62e80 | 1832 | 0 | 0 | 1838741 | 2571 | 0 | 0 | 1912474 | 3421 | 0 | 0 | 1997215 | 2534 | 0 | 0 | 1827649 | 2082 | 0 | 0 | 1823999 | 2379 | 0 | 0 | 1799530 | 5072 | 0 | 0 | 2220534 | 3380 | 0 | 0 | 1988286 | 1897 | 0 | 0 | 1848333 | 2837 | 0 | 0 | 1895637 | 2052 | 0 | 0 | 1848880 | 2788 | 0 | 0 | 1971805 | 2126 | 0 | 0 | 1797201 | 1963 | 0 | 0 | 1833184 | 2157 | 0 | 0 | 1875975 | 2679 | 0 | 0 | 1907076 | 3523 | 0 | 0 | 1988854 | 1455 | 0 | 0 | 1733155 | 4048 | 0 | 0 | 2088227 | 3015 | 0 | 0 | 1900036 | 1055 | 0 | 0 | 1677942 | 2765 | 0 | 0 | 1950987 | 3432 | 0 | 0 | 1985265 | 3488 | 0 | 0 | 1964706 | 3577 | 0 | 0 | 2000111 | 1458 | 0 | 0 | 1700260 | 5000 | 0 | 0 | 2128429 | 3984 | 0 | 0 | 1999890 | 5387 | 0 | 0 | 2120325 | 3221 | 0 | 0 | 1987919 | 4378 | 0 | 0 | 2127532 | 2696 | 0 | 0 | 1965941 | 64 | 0x7f0565a1ee80 | 4096 | 0 | 1447 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 3191 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 458 | 0 | 4096 | 0 | 423 | 0 | 4096 | 0 | 3597 | 0 | 4096 | 0 | 3839 | 0 | 4096 | 0 | 341 | 0 | 4096 | 0 | 6415 | 0 | 4096 | 0 | 440 | 0 | 4096 | 0 | 7837 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 541 | 0 | 4096 | 0 | 3461 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 120 | 0 | 4096 | 0 | 858 | 0 | 4096 | 0 | 2265 | 0 | 4216 | 0 | 319 | 0 | 4096 | 0 | 66 | 0 | 4096 | 0 | 171 | 0 | 4096 | 0 | 1804 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 265 | 0 | 4096 | 0 | 575 | 0 | 4096 | 0 | 1235 | 0 | 4192 | 0 | 3049 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4098 | 0 | 3501 | 0 | 64 | 0x7fcf21906e80 | 0 | 0 | 192 | 0 | 65536 | 64503 | 48 | 1317 | 31071 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 538 | 47163 | 1764 | 0 | 48.0 | 216.0 | 0.0 | 262288.0 | 64 | 0x7fd968430e80 | 0.0 | 2187943271073379 | 2187943271097699 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7fa1427fce80 | 0 | 4918468 | 2696 | 2696 | 0 | 3890284 | 2716 | 2716 | 0 | 3993520 | 2676 | 2676 | 0 | 3975815 | 2706 | 2706 | 0 | 3375759 | 2668 | 2668 | 0 | 3862020 | 2714 | 2714 | 0 | 3850765 | 2699 | 2699 | 0 | 4657132 | 2714 | 2714 | 0 | 4715993 | 2698 | 2698 | 0 | 3958542 | 2668 | 2668 | 0 | 4790673 | 2714 | 2714 | 0 | 4138870 | 2734 | 2734 | 0 | 3419283 | 2706 | 2706 | 0 | 4144043 | 2696 | 2696 | 0 | 4397625 | 2694 | 2694 | 0 | 4083127 | 2686 | 2686 | 0 | 3154116 | 2684 | 2684 | 0 | 5243872 | 2712 | 2712 | 0 | 3474870 | 2690 | 2690 | 0 | 4406086 | 2716 | 2716 | 0 | 3752698 | 2704 | 2704 | 0 | 3056551 | 2737 | 2737 | 0 | 3729826 | 2676 | 2676 | 0 | 3437864 | 2685 | 2685 | 0 | 3132211 | 2672 | 2672 | 0 | 5022079 | 2680 | 2680 | 0 | 4320846 | 2722 | 2722 | 0 | 3567005 | 2714 | 2714 | 0 | 4382236 | 2714 | 2714 | 0 | 3257045 | 2707 | 2707 | 0 | 4143306 | 2719 | 2719 | 0 | 3386945 | 2704 | 2704 | 64 | 0x7f67fc0e0e80 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 0 | 43225 | 0 | 0 | 64 | 0x7f58d6496e80 | 188004 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 11834 | 28218 | 8563 | 3270 | 0 | 41541 | 262554.0 | 0.0 | 47.0 | 262507.0 | 64 | 0x7fb6b8cd8e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22688322 | 960.0 | 514030.0 | 0.0 | 524288.0 | 909941.0 | 32768.0 | 0 | 0 | 0 | 13020 | 86652.0 | 86652.0 | 0.0 | 86652.0 | 64 | 0x7fd27dddce80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f989f5ece80 | 131072.0 | 131072.0 | 0.0 | 2579851.0 | 0.0 | 0.0 | 102780109.0 | 31303553.0 | 64 | 0x7f2f9a21ae80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 48192.0 | 122001.0 | 64 | 0x7f133e226e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86688.0 | 0.0 | 131110.0 | 0.0 | 64 | 0x7f5f9af14e80 | 1714840 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 71540552.0 | 197113942.0 | 77080583.0 | 131072.0 | 0.0 | 605267.0 | 0 | 0 | 25715 | 66781.0 | 0.0 | 0.0 | 66781.0 | 64 | 0x7f527e452e80 | 349624 | 236434 | 3478250 | 16384 | 25323983 | 0 | 48 | 0 | 43702 | 43702 | 3835936.0 | 3104356.0 | 6681.0 | 950371.0 | 2086776.0 | 0.0 | 3093919.0 | 2783281.0 | 349616 | 245687 | 43702 | 0 | 43702 | 0 | 1398464.0 | 822274.0 | 0.0 | 0.0 | 64 | 0x7f81736bce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131347.0 | 0.0 | 548.0 | 131346.0 | 64 | 0x7fd1b5a42e80 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8312 | 4216 | 8312 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8195 | 4099 | 8195 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 64 | 0x7f85a3448e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 240.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 5240 | 42207 | 1066 | 131557.0 | 131072.0 | 0.0 | 86653.0 | 64 | 0x7f7e31e62e80 | 3429 | 0 | 0 | 1660463 | 940 | 0 | 0 | 1403464 | 989 | 0 | 0 | 1298807 | 1573 | 0 | 0 | 1466149 | 668 | 0 | 0 | 1289601 | 116 | 0 | 0 | 1165810 | 1029 | 0 | 0 | 1361279 | 2123 | 0 | 0 | 1510575 | 1453 | 0 | 0 | 1450236 | 539 | 0 | 0 | 1255471 | 1298 | 0 | 0 | 1422329 | 1292 | 0 | 0 | 1394874 | 1628 | 0 | 0 | 1483064 | 733 | 0 | 0 | 1251835 | 496 | 0 | 0 | 1260705 | 3935 | 0 | 0 | 1718403 | 759 | 0 | 0 | 1405936 | 902 | 0 | 0 | 1401475 | 1581 | 0 | 0 | 1471398 | 3532 | 0 | 0 | 1674710 | 4232 | 0 | 0 | 1760350 | 5244 | 0 | 0 | 1859699 | 718 | 0 | 0 | 1321109 | 1755 | 0 | 0 | 1439483 | 1442 | 0 | 0 | 1392420 | 2078 | 0 | 0 | 1514953 | 928 | 0 | 0 | 1325711 | 3270 | 0 | 0 | 1619775 | 837 | 0 | 0 | 1363664 | 6018 | 0 | 0 | 1872100 | 1052 | 0 | 0 | 1312896 | 815 | 0 | 0 | 1344047 | 64 | 0x7f0565a1ee80 | 4096 | 0 | 826 | 0 | 4096 | 0 | 4971 | 0 | 4096 | 0 | 497 | 0 | 4096 | 0 | 967 | 0 | 4096 | 0 | 7753 | 0 | 4096 | 0 | 2081 | 0 | 4096 | 0 | 562 | 0 | 4096 | 0 | 1366 | 0 | 4096 | 0 | 2781 | 0 | 4096 | 0 | 337 | 0 | 4096 | 0 | 1592 | 0 | 4096 | 0 | 2448 | 0 | 4097 | 0 | 1518 | 0 | 4096 | 0 | 3602 | 0 | 4096 | 0 | 266 | 0 | 4096 | 0 | 589 | 0 | 4097 | 0 | 1791 | 0 | 4096 | 0 | 4248 | 0 | 4096 | 0 | 2125 | 0 | 4216 | 0 | 6793 | 0 | 4096 | 0 | 525 | 0 | 4096 | 0 | 1111 | 0 | 4096 | 0 | 422 | 0 | 4096 | 0 | 4902 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 1182 | 0 | 4096 | 0 | 838 | 0 | 4192 | 0 | 737 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 165 | 0 | 4101 | 0 | 193 | 0 | 4097 | 0 | 474 | 0 | 64 | 0x7fcf21906e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 29880 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 458 | 41649 | 1710 | 0 | 48.0 | 223.0 | 0.0 | 262144.0 | 64 | 0x7fd968430e80 | 0.0 | 2187943271198499 | 2187943271217539 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7fa1427fce80 | 0 | 3878771 | 2752 | 2752 | 0 | 3523856 | 2708 | 2708 | 0 | 4606824 | 2670 | 2670 | 0 | 3368124 | 2692 | 2692 | 0 | 4756627 | 2708 | 2708 | 0 | 3057583 | 2724 | 2724 | 0 | 3215981 | 2728 | 2728 | 0 | 3806523 | 2682 | 2682 | 0 | 3308417 | 2732 | 2732 | 0 | 3333847 | 2704 | 2704 | 0 | 4271198 | 2716 | 2716 | 0 | 3497868 | 2720 | 2720 | 0 | 3437606 | 2732 | 2732 | 0 | 3309715 | 2688 | 2688 | 0 | 3274018 | 2686 | 2686 | 0 | 3369647 | 2684 | 2684 | 0 | 3089325 | 2720 | 2720 | 0 | 4977073 | 2701 | 2701 | 0 | 3894272 | 2680 | 2680 | 0 | 3848435 | 2714 | 2714 | 0 | 3611568 | 2732 | 2732 | 0 | 4051064 | 2752 | 2752 | 0 | 4247845 | 2724 | 2724 | 0 | 3317314 | 2668 | 2668 | 0 | 3104254 | 2718 | 2718 | 0 | 3676488 | 2680 | 2680 | 0 | 3294363 | 2748 | 2748 | 0 | 3057865 | 2674 | 2674 | 0 | 3460285 | 2736 | 2736 | 0 | 3545133 | 2714 | 2714 | 0 | 4584786 | 2720 | 2720 | 0 | 3227289 | 2658 | 2658 | 64 | 0x7f67fc0e0e80 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 0 | 42616 | 0 | 0 | 64 | 0x7f58d6496e80 | 186079 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 11355 | 27739 | 8556 | 3714 | 0 | 42119 | 262542.0 | 0.0 | 47.0 | 262495.0 | 64 | 0x7fb6b8cd8e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 21962973 | 960.0 | 513958.0 | 0.0 | 524288.0 | 1155379.0 | 32768.0 | 0 | 0 | 0 | 13675 | 86855.0 | 86855.0 | 0.0 | 86855.0 | 64 | 0x7fd27dddce80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f989f5ece80 | 131072.0 | 131072.0 | 0.0 | 2352325.0 | 0.0 | 0.0 | 126352442.0 | 52021838.0 | 64 | 0x7f2f9a21ae80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 66644.0 | 138028.0 | 64 | 0x7f133e226e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86297.0 | 0.0 | 131112.0 | 0.0 | 64 | 0x7f5f9af14e80 | 2113987 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 66089601.0 | 176452209.0 | 75511968.0 | 131072.0 | 0.0 | 498972.0 | 0 | 0 | 26052 | 87866.0 | 0.0 | 0.0 | 87866.0 | 64 | 0x7f527e452e80 | 342280 | 228407 | 3332525 | 16384 | 24446733 | 0 | 48 | 0 | 42784 | 42784 | 3715949.0 | 3000643.0 | 8016.0 | 1284027.0 | 2083238.0 | 0.0 | 2991277.0 | 2679534.0 | 342272 | 238081 | 42784 | 0 | 42784 | 0 | 1369088.0 | 808240.0 | 0.0 | 0.0 | 64 | 0x7f81736bce80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131343.0 | 0.0 | 540.0 | 131342.0 | 64 | 0x7fd1b5a42e80 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8312 | 4216 | 8312 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8198 | 4102 | 8198 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8195 | 4099 | 8195 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 64 | 0x7f85a3448e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 2759 | 39416 | 0 | 131388.0 | 131072.0 | 0.0 | 86618.0 | 64 | 0x7f7e31e62e80 | 610 | 0 | 0 | 1294455 | 1251 | 0 | 0 | 1318285 | 505 | 0 | 0 | 1286846 | 1544 | 0 | 0 | 1403768 | 95 | 0 | 0 | 1150966 | 1207 | 0 | 0 | 1304802 | 1306 | 0 | 0 | 1407656 | 2254 | 0 | 0 | 1502537 | 878 | 0 | 0 | 1300605 | 1190 | 0 | 0 | 1330596 | 3067 | 0 | 0 | 1579789 | 1599 | 0 | 0 | 1445184 | 642 | 0 | 0 | 1311476 | 863 | 0 | 0 | 1325861 | 456 | 0 | 0 | 1316738 | 4983 | 0 | 0 | 1758107 | 771 | 0 | 0 | 1304559 | 861 | 0 | 0 | 1313149 | 2615 | 0 | 0 | 1576439 | 928 | 0 | 0 | 1312032 | 5196 | 0 | 0 | 1799192 | 340 | 0 | 0 | 1150650 | 927 | 0 | 0 | 1327074 | 1642 | 0 | 0 | 1389385 | 1849 | 0 | 0 | 1416122 | 3959 | 0 | 0 | 1613856 | 1590 | 0 | 0 | 1373782 | 3544 | 0 | 0 | 1629172 | 2096 | 0 | 0 | 1464078 | 3246 | 0 | 0 | 1661032 | 1111 | 0 | 0 | 1356935 | 1004 | 0 | 0 | 1363389 | 64 | 0x7f0565a1ee80 | 4096 | 0 | 1011 | 0 | 4096 | 0 | 590 | 0 | 4096 | 0 | 2391 | 0 | 4096 | 0 | 1295 | 0 | 4096 | 0 | 2350 | 0 | 4096 | 0 | 405 | 0 | 4096 | 0 | 1217 | 0 | 4096 | 0 | 1423 | 0 | 4096 | 0 | 6368 | 0 | 4096 | 0 | 688 | 0 | 4096 | 0 | 2356 | 0 | 4096 | 0 | 1447 | 0 | 4097 | 0 | 7135 | 0 | 4096 | 0 | 956 | 0 | 4096 | 0 | 966 | 0 | 4096 | 0 | 1779 | 0 | 4097 | 0 | 625 | 0 | 4096 | 0 | 1725 | 0 | 4096 | 0 | 988 | 0 | 4216 | 0 | 4372 | 0 | 4096 | 0 | 1658 | 0 | 4096 | 0 | 449 | 0 | 4096 | 0 | 767 | 0 | 4096 | 0 | 598 | 0 | 4096 | 0 | 1287 | 0 | 4096 | 0 | 6367 | 0 | 4096 | 0 | 1604 | 0 | 4192 | 0 | 768 | 0 | 4096 | 0 | 670 | 0 | 4096 | 0 | 744 | 0 | 4101 | 0 | 101 | 0 | 4099 | 0 | 436 | 0 | 64 | 0x7fcf21906e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 30008 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 458 | 41764 | 1768 | 0 | 48.0 | 223.0 | 0.0 | 262144.0 | 64 | 0x7fd968430e80 | 0.0 | 2187943271238819 | 2187943271257699 |