JoseSantosAMD
2d1f73ad11
* updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * updating workloads Signed-off-by: Jose Santos <josantos@amd.com> * Adding generate workloads script Signed-off-by: Jose Santos <josantos@amd.com> * Changing output workloads dir in shell script Signed-off-by: Jose Santos <josantos@amd.com> --------- Signed-off-by: Jose Santos <josantos@amd.com>
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_1 | obj_1 | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | TCC_EA_RDREQ_DRAM_sum | wave_size_2 | obj_2 | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_3 | obj_3 | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | SQC_DCACHE_REQ_READ_1 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_4 | obj_4 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_5 | obj_5 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_BUSY_CU_CYCLES | SQ_WAVES | SQ_WAVE_CYCLES | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | SQC_TC_DATA_WRITE_REQ | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_6 | obj_6 | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_EA_RDREQ_IO_CREDIT_STALL_sum | TCC_EA_RDREQ_GMI_CREDIT_STALL_sum | TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum | TCC_TAG_STALL_sum | wave_size_7 | obj_7 | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | SQC_ICACHE_MISSES_DUPLICATE | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_COALESCABLE_WAVEFRONT_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_8 | obj_8 | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_INSTS_VALU | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_WRREQ_IO_CREDIT_STALL_sum | TCC_EA_WRREQ_GMI_CREDIT_STALL_sum | TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum | wave_size_9 | obj_9 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_10 | obj_10 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_11 | obj_11 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | SQ_INSTS_SMEM_NORM | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | wave_size_12 | obj_12 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | wave_size_13 | obj_13 | TCC_EA_ATOMIC_LEVEL_sum | wave_size_14 | obj_14 | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | wave_size_15 | obj_15 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | SQ_INSTS_VSKIPPED | SQ_INSTS_SMEM | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_16 | obj_16 | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | SQ_INSTS | SQ_WAIT_ANY | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f6498f94e80 | 4096 | 0 | 1643 | 0 | 4096 | 0 | 1733 | 0 | 4096 | 0 | 1615 | 0 | 4102 | 0 | 454 | 0 | 4096 | 0 | 6712 | 0 | 4096 | 0 | 933 | 0 | 4096 | 0 | 5673 | 0 | 4098 | 0 | 4037 | 0 | 4096 | 0 | 1492 | 0 | 4096 | 0 | 3378 | 0 | 4096 | 0 | 1082 | 0 | 4144 | 0 | 2476 | 0 | 4096 | 0 | 1876 | 0 | 4096 | 0 | 3718 | 0 | 4096 | 0 | 611 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 436 | 0 | 4096 | 0 | 5095 | 0 | 4096 | 0 | 1043 | 0 | 4096 | 0 | 4138 | 0 | 4096 | 0 | 1667 | 0 | 4096 | 0 | 605 | 0 | 4096 | 0 | 895 | 0 | 4096 | 0 | 541 | 0 | 4096 | 0 | 1367 | 0 | 4096 | 0 | 705 | 0 | 4096 | 0 | 2402 | 0 | 4144 | 0 | 260 | 0 | 4096 | 0 | 490 | 0 | 4096 | 0 | 44 | 0 | 4096 | 0 | 242 | 0 | 4096 | 0 | 417 | 0 | 64 | 0x7f59a5096e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131305.0 | 0.0 | 458.0 | 131304.0 | 64 | 0x7f5d2c2f6e80 | 4829 | 0 | 0 | 2129266 | 2363 | 0 | 0 | 1882798 | 2896 | 0 | 0 | 1736714 | 1879 | 0 | 0 | 1725295 | 2908 | 0 | 0 | 1975519 | 4533 | 0 | 0 | 2126419 | 3027 | 0 | 0 | 1856901 | 732 | 0 | 0 | 1708569 | 1018 | 0 | 0 | 1552172 | 1458 | 0 | 0 | 1725024 | 2060 | 0 | 0 | 1819178 | 444 | 0 | 0 | 1588564 | 2423 | 0 | 0 | 1954435 | 2019 | 0 | 0 | 1813218 | 2065 | 0 | 0 | 1795262 | 1636 | 0 | 0 | 1770592 | 2935 | 0 | 0 | 1912590 | 3223 | 0 | 0 | 2023705 | 3999 | 0 | 0 | 2071622 | 2245 | 0 | 0 | 1874014 | 2745 | 0 | 0 | 1795405 | 752 | 0 | 0 | 1585128 | 2873 | 0 | 0 | 1896431 | 8830 | 0 | 0 | 2375300 | 2088 | 0 | 0 | 1867078 | 1781 | 0 | 0 | 1799401 | 1697 | 0 | 0 | 1811871 | 1570 | 0 | 0 | 1771462 | 2656 | 0 | 0 | 1800735 | 1853 | 0 | 0 | 1770382 | 3548 | 0 | 0 | 1939050 | 937 | 0 | 0 | 1683685 | 64 | 0x7f832b1dce80 | 206730 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 14057 | 30441 | 9907 | 550 | 0 | 47557 | 262713.0 | 0.0 | 188.0 | 262525.0 | 64 | 0x7ffbc7a20e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8336 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f404524ee80 | 377648 | 228791 | 3325353 | 16384 | 24458783 | 144 | 48 | 0 | 47205 | 47205 | 3784508.0 | 2939974.0 | 4713.0 | 1101060.0 | 2167040.0 | 0.0 | 2931222.0 | 2623154.0 | 376255 | 238738 | 47205 | 0 | 47205 | 0 | 1510560.0 | 964914.0 | 0.0 | 0.0 | 64 | 0x7fdf4abc6e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 52554.0 | 123129.0 | 64 | 0x7f380e6e6e80 | 0 | 0 | 192 | 0 | 65536 | 64281 | 48 | 1888 | 32481 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 538 | 48845 | 1668 | 0 | 48.0 | 384.0 | 0.0 | 262288.0 | 64 | 0x7f442ec9ce80 | 2832273 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 63063880.0 | 182726621.0 | 73509932.0 | 131072.0 | 0.0 | 792646.0 | 0 | 0 | 27281 | 113156.0 | 0.0 | 0.0 | 113156.0 | 64 | 0x7f5b4839ae80 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 0 | 47503 | 0 | 0 | 64 | 0x7ff6dfe38e80 | 0 | 3298003 | 4096 | 4096 | 0 | 3346739 | 4096 | 4096 | 0 | 3271742 | 4096 | 4096 | 0 | 2634514 | 4096 | 4096 | 0 | 3394041 | 4096 | 4096 | 0 | 3309019 | 4096 | 4096 | 0 | 3221938 | 4096 | 4096 | 0 | 3052326 | 4096 | 4096 | 0 | 3056966 | 4096 | 4096 | 0 | 2769168 | 4096 | 4096 | 0 | 3085722 | 4096 | 4096 | 0 | 2934436 | 4096 | 4096 | 0 | 3432961 | 4096 | 4096 | 0 | 2977450 | 4096 | 4096 | 0 | 3038836 | 4096 | 4096 | 0 | 2685183 | 4096 | 4096 | 0 | 3267212 | 4096 | 4096 | 0 | 3372497 | 4096 | 4096 | 0 | 3174395 | 4096 | 4096 | 0 | 2607771 | 4096 | 4096 | 0 | 3048516 | 4096 | 4096 | 0 | 3129195 | 4096 | 4096 | 0 | 3119664 | 4096 | 4096 | 0 | 2937515 | 4096 | 4096 | 0 | 3547398 | 4096 | 4096 | 0 | 3413272 | 4096 | 4096 | 0 | 2750570 | 4096 | 4096 | 0 | 2873569 | 4096 | 4096 | 0 | 3627247 | 4096 | 4096 | 0 | 2853614 | 4096 | 4096 | 0 | 2804514 | 4096 | 4096 | 0 | 4938266 | 4096 | 4096 | 64 | 0x7fe1d4338e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 87440.0 | 43632.0 | 131112.0 | 0.0 | 64 | 0x7f4f30368e80 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 141 | 8196 | 4241 | 8337 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8334 | 4238 | 8334 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fdbd5232e80 | 0.0 | 64 | 0x7ff44ef22e80 | 131072.0 | 131072.0 | 0.0 | 2309906.0 | 0.0 | 0.0 | 119690272.0 | 59894761.0 | 64 | 0x7fed6a790e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 913 | 47978 | 0 | 131722.0 | 131072.0 | 0.0 | 131104.0 | 64 | 0x7f4b6a732e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 21980888 | 960.0 | 513862.0 | 0.0 | 524288.0 | 1304330.0 | 32768.0 | 0 | 0 | 0 | 16862 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 2187922015837329 | 2187922015861489 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f6498f94e80 | 4096 | 0 | 561 | 0 | 4096 | 0 | 1313 | 0 | 4096 | 0 | 2069 | 0 | 4154 | 0 | 1246 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 1702 | 0 | 4096 | 0 | 843 | 0 | 4110 | 0 | 5748 | 0 | 4098 | 0 | 1121 | 0 | 4096 | 0 | 2909 | 0 | 4096 | 0 | 1879 | 0 | 4144 | 0 | 1334 | 0 | 4096 | 0 | 782 | 0 | 4096 | 0 | 266 | 0 | 4096 | 0 | 1250 | 0 | 4096 | 0 | 149 | 0 | 4096 | 0 | 626 | 0 | 4096 | 0 | 2886 | 0 | 4096 | 0 | 4839 | 0 | 4096 | 0 | 3333 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 967 | 0 | 4096 | 0 | 629 | 0 | 4096 | 0 | 323 | 0 | 4098 | 0 | 384 | 0 | 4096 | 0 | 2694 | 0 | 4096 | 0 | 1778 | 0 | 4144 | 0 | 440 | 0 | 4096 | 0 | 250 | 0 | 4096 | 0 | 2727 | 0 | 4096 | 0 | 214 | 0 | 4096 | 0 | 484 | 0 | 64 | 0x7f59a5096e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131277.0 | 0.0 | 408.0 | 131276.0 | 64 | 0x7f5d2c2f6e80 | 3120 | 0 | 0 | 1536279 | 2418 | 0 | 0 | 1566523 | 1811 | 0 | 0 | 1354936 | 1372 | 0 | 0 | 1473912 | 463 | 0 | 0 | 1325309 | 472 | 0 | 0 | 1317226 | 2624 | 0 | 0 | 1512574 | 1150 | 0 | 0 | 1417408 | 579 | 0 | 0 | 1328205 | 1081 | 0 | 0 | 1316935 | 3163 | 0 | 0 | 1465593 | 273 | 0 | 0 | 1177449 | 2659 | 0 | 0 | 1478119 | 1081 | 0 | 0 | 1386202 | 1395 | 0 | 0 | 1370908 | 3758 | 0 | 0 | 1696953 | 2402 | 0 | 0 | 1587864 | 3141 | 0 | 0 | 1562100 | 2219 | 0 | 0 | 1479336 | 2425 | 0 | 0 | 1601556 | 5408 | 0 | 0 | 1769750 | 2178 | 0 | 0 | 1447503 | 4599 | 0 | 0 | 1672669 | 996 | 0 | 0 | 1319335 | 638 | 0 | 0 | 1287644 | 1420 | 0 | 0 | 1416439 | 3148 | 0 | 0 | 1465782 | 728 | 0 | 0 | 1280205 | 668 | 0 | 0 | 1325913 | 2226 | 0 | 0 | 1477686 | 2933 | 0 | 0 | 1480492 | 430 | 0 | 0 | 1327275 | 64 | 0x7f832b1dce80 | 203365 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 13478 | 29862 | 9008 | 3827 | 0 | 42167 | 262554.0 | 0.0 | 47.0 | 262507.0 | 64 | 0x7ffbc7a20e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f404524ee80 | 331720 | 222098 | 3257691 | 16384 | 24182412 | 0 | 48 | 0 | 41464 | 41464 | 3620722.0 | 2964800.0 | 5718.0 | 1139817.0 | 2091296.0 | 0.0 | 2956307.0 | 2645681.0 | 331712 | 231405 | 41464 | 0 | 41464 | 0 | 1326848.0 | 808771.0 | 0.0 | 0.0 | 64 | 0x7fdf4abc6e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 71495.0 | 137932.0 | 64 | 0x7f380e6e6e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 32442 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 458 | 46674 | 1755 | 0 | 48.0 | 395.0 | 0.0 | 262144.0 | 64 | 0x7f442ec9ce80 | 2362326 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 69173861.0 | 207621779.0 | 72410478.0 | 131072.0 | 0.0 | 1024336.0 | 0 | 0 | 27024 | 86886.0 | 0.0 | 0.0 | 86886.0 | 64 | 0x7f5b4839ae80 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 0 | 43367 | 0 | 0 | 64 | 0x7ff6dfe38e80 | 0 | 5533170 | 2740 | 2740 | 0 | 3974574 | 2746 | 2746 | 0 | 3014325 | 2725 | 2725 | 0 | 3601426 | 2698 | 2698 | 0 | 3460424 | 2720 | 2720 | 0 | 2691551 | 2726 | 2726 | 0 | 3100731 | 2740 | 2740 | 0 | 4103367 | 2714 | 2714 | 0 | 3954754 | 2703 | 2703 | 0 | 4957124 | 2712 | 2712 | 0 | 2731690 | 2716 | 2716 | 0 | 3800703 | 2718 | 2718 | 0 | 3388691 | 2734 | 2734 | 0 | 4207858 | 2704 | 2704 | 0 | 2724158 | 2718 | 2718 | 0 | 3219518 | 2676 | 2676 | 0 | 3436850 | 2708 | 2708 | 0 | 3870024 | 2722 | 2722 | 0 | 3102531 | 2702 | 2702 | 0 | 3234642 | 2704 | 2704 | 0 | 4303239 | 2700 | 2700 | 0 | 4617493 | 2751 | 2751 | 0 | 2858349 | 2682 | 2682 | 0 | 3575089 | 2676 | 2676 | 0 | 4003318 | 2705 | 2705 | 0 | 3429844 | 2740 | 2740 | 0 | 2659745 | 2736 | 2736 | 0 | 3196069 | 2700 | 2700 | 0 | 2827014 | 2711 | 2711 | 0 | 3529063 | 2734 | 2734 | 0 | 2857735 | 2728 | 2728 | 0 | 4686180 | 2692 | 2692 | 64 | 0x7fe1d4338e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86563.0 | 0.0 | 131113.0 | 0.0 | 64 | 0x7f4f30368e80 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8399 | 4303 | 8399 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fdbd5232e80 | 0.0 | 64 | 0x7ff44ef22e80 | 131072.0 | 131072.0 | 0.0 | 2471838.0 | 0.0 | 0.0 | 119900899.0 | 46029151.0 | 64 | 0x7fed6a790e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 3413 | 40724 | 0 | 131528.0 | 131072.0 | 0.0 | 86842.0 | 64 | 0x7f4b6a732e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22340503 | 960.0 | 513958.0 | 0.0 | 524288.0 | 1147342.0 | 32768.0 | 0 | 0 | 0 | 21782 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 2187922015985649 | 2187922016004529 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) [clone .kd] | 2 | 1048576 | 256 | 0 | 0 | 8 | 8 | 16 | 64 | 0x7f6498f94e80 | 4096 | 0 | 2033 | 0 | 4096 | 0 | 872 | 0 | 4096 | 0 | 0 | 0 | 4100 | 0 | 1550 | 0 | 4096 | 0 | 168 | 0 | 4096 | 0 | 261 | 0 | 4096 | 0 | 1907 | 0 | 4162 | 0 | 4411 | 0 | 4098 | 0 | 455 | 0 | 4096 | 0 | 1213 | 0 | 4096 | 0 | 4379 | 0 | 4144 | 0 | 4080 | 0 | 4096 | 0 | 1604 | 0 | 4096 | 0 | 2345 | 0 | 4096 | 0 | 1601 | 0 | 4096 | 0 | 176 | 0 | 4096 | 0 | 5984 | 0 | 4096 | 0 | 3974 | 0 | 4096 | 0 | 3357 | 0 | 4096 | 0 | 709 | 0 | 4096 | 0 | 297 | 0 | 4096 | 0 | 888 | 0 | 4096 | 0 | 5281 | 0 | 4096 | 0 | 1001 | 0 | 4098 | 0 | 0 | 0 | 4096 | 0 | 2172 | 0 | 4096 | 0 | 303 | 0 | 4144 | 0 | 425 | 0 | 4096 | 0 | 385 | 0 | 4096 | 0 | 1429 | 0 | 4096 | 0 | 255 | 0 | 4096 | 0 | 1202 | 0 | 64 | 0x7f59a5096e80 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 11534336 | 65536 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131253.0 | 0.0 | 360.0 | 131252.0 | 64 | 0x7f5d2c2f6e80 | 1189 | 0 | 0 | 1329827 | 2093 | 0 | 0 | 1395072 | 1165 | 0 | 0 | 1371343 | 1322 | 0 | 0 | 1342583 | 559 | 0 | 0 | 1193819 | 1156 | 0 | 0 | 1415496 | 1746 | 0 | 0 | 1461250 | 1509 | 0 | 0 | 1329244 | 581 | 0 | 0 | 1368232 | 1711 | 0 | 0 | 1375586 | 3636 | 0 | 0 | 1643794 | 197 | 0 | 0 | 1187022 | 678 | 0 | 0 | 1285971 | 1014 | 0 | 0 | 1281207 | 1631 | 0 | 0 | 1462272 | 1249 | 0 | 0 | 1298474 | 1338 | 0 | 0 | 1336199 | 914 | 0 | 0 | 1258225 | 2813 | 0 | 0 | 1574930 | 2674 | 0 | 0 | 1429853 | 6302 | 0 | 0 | 1856536 | 2953 | 0 | 0 | 1528400 | 2214 | 0 | 0 | 1506562 | 700 | 0 | 0 | 1244235 | 748 | 0 | 0 | 1284770 | 1132 | 0 | 0 | 1241223 | 2097 | 0 | 0 | 1499565 | 972 | 0 | 0 | 1299747 | 1261 | 0 | 0 | 1279841 | 1356 | 0 | 0 | 1285609 | 2321 | 0 | 0 | 1490219 | 1596 | 0 | 0 | 1442432 | 64 | 0x7f832b1dce80 | 203624 | 0 | 0 | 65536 | 64048 | 48 | 1440 | 32768 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 14980 | 31364 | 8897 | 3935 | 0 | 42359 | 262581.0 | 0.0 | 47.0 | 262534.0 | 64 | 0x7ffbc7a20e80 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 8192 | 0 | 4096 | 64 | 0x7f404524ee80 | 336520 | 226190 | 3286022 | 16384 | 23537813 | 0 | 48 | 0 | 42064 | 42064 | 3682766.0 | 3001178.0 | 5258.0 | 1015366.0 | 2170593.0 | 0.0 | 2992592.0 | 2683297.0 | 336512 | 235967 | 42064 | 0 | 42064 | 0 | 1346048.0 | 821984.0 | 0.0 | 0.0 | 64 | 0x7fdf4abc6e80 | 0 | 0 | 0 | 16384 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 81920 | 0.0 | 0.0 | 35724.0 | 106795.0 | 64 | 0x7f380e6e6e80 | 0 | 0 | 48 | 0 | 65536 | 65536 | 0 | 0 | 31932 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 4096 | 16384 | 458 | 43623 | 1745 | 0 | 48.0 | 390.0 | 0.0 | 262144.0 | 64 | 0x7f442ec9ce80 | 2979338 | 360448 | 163840 | 0 | 0 | 180224 | 114688 | 0 | 60352424.0 | 162813579.0 | 58777467.0 | 131072.0 | 0.0 | 840692.0 | 0 | 0 | 26760 | 62515.0 | 0.0 | 0.0 | 62515.0 | 64 | 0x7f5b4839ae80 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 | 0 | 43548 | 0 | 0 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4542244 | 2806 | 2806 | 64 | 0x7fe1d4338e80 | 1048576 | 0 | 0 | 0 | 0 | 0 | 131072 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 86539.0 | 0.0 | 131113.0 | 0.0 | 64 | 0x7f4f30368e80 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8193 | 4097 | 8193 | 0 | 8192 | 4096 | 8192 | 47 | 8193 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8194 | 4098 | 8194 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8346 | 4250 | 8346 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8193 | 4097 | 8193 | 0 | 8240 | 4144 | 8240 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 0 | 8192 | 4096 | 8192 | 64 | 0x7fdbd5232e80 | 0.0 | 64 | 0x7ff44ef22e80 | 131072.0 | 131072.0 | 0.0 | 2554590.0 | 0.0 | 0.0 | 118062600.0 | 43753527.0 | 64 | 0x7fed6a790e80 | 32768 | 0 | 16384 | 16384 | 32768 | 49152 | 0 | 65536 | 0.0 | 0.0 | 120.0 | 524288.0 | 0.0 | 0.0 | 0 | 0 | 3150 | 39907 | 0 | 131522.0 | 131072.0 | 0.0 | 86522.0 | 64 | 0x7f4b6a732e80 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 393216 | 22705919 | 960.0 | 514058.0 | 0.0 | 524288.0 | 1118614.0 | 32768.0 | 0 | 0 | 0 | 14736 | 86337.0 | 86337.0 | 0.0 | 86337.0 | 2187922016025809 | 2187922016044849 |