1b79caa214
Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: David Yat Sin <David.YatSin@amd.com>
381 lines
13 KiB
C++
381 lines
13 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "core/inc/interrupt_signal.h"
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#include "core/inc/runtime.h"
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#include "core/util/locks.h"
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namespace rocr {
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namespace core {
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HsaEvent* InterruptSignal::EventPool::alloc() {
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ScopedAcquire<HybridMutex> lock(&lock_);
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if (events_.empty()) {
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if (!allEventsAllocated) {
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HsaEvent* evt = InterruptSignal::CreateEvent(HSA_EVENTTYPE_SIGNAL, false);
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if (evt == nullptr) allEventsAllocated = true;
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return evt;
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}
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return nullptr;
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}
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HsaEvent* ret = events_.back().release();
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events_.pop_back();
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return ret;
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}
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void InterruptSignal::EventPool::free(HsaEvent* evt) {
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if (evt == nullptr) return;
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ScopedAcquire<HybridMutex> lock(&lock_);
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events_.push_back(unique_event_ptr(evt));
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}
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HsaEvent* InterruptSignal::CreateEvent(HSA_EVENTTYPE type, bool manual_reset) {
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HsaEventDescriptor event_descriptor;
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event_descriptor.EventType = type;
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event_descriptor.SyncVar.SyncVar.UserData = NULL;
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event_descriptor.SyncVar.SyncVarSize = sizeof(hsa_signal_value_t);
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event_descriptor.NodeId = 0;
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HsaEvent* ret = NULL;
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if (HSAKMT_STATUS_SUCCESS ==
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HSAKMT_CALL(hsaKmtCreateEvent(&event_descriptor, manual_reset, false, &ret))) {
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if (type == HSA_EVENTTYPE_MEMORY) {
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memset(&ret->EventData.EventData.MemoryAccessFault.Failure, 0,
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sizeof(HsaAccessAttributeFailure));
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} else if (type == HSA_EVENTTYPE_HW_EXCEPTION) {
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memset(&ret->EventData.EventData.HwException, 0, sizeof(HsaHwException));
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}
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}
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return ret;
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}
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void InterruptSignal::DestroyEvent(HsaEvent* evt) { HSAKMT_CALL(hsaKmtDestroyEvent(evt)); }
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InterruptSignal::InterruptSignal(hsa_signal_value_t initial_value, HsaEvent* use_event)
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: LocalSignal(initial_value, false), Signal(signal()) {
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if (use_event != nullptr) {
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event_ = use_event;
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free_event_ = false;
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} else {
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event_ = Runtime::runtime_singleton_->GetEventPool()->alloc();
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free_event_ = true;
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}
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if (event_ != nullptr) {
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signal_.event_id = event_->EventId;
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signal_.event_mailbox_ptr = event_->EventData.HWData2;
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} else {
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signal_.event_id = 0;
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signal_.event_mailbox_ptr = 0;
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}
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signal_.kind = AMD_SIGNAL_KIND_USER;
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}
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InterruptSignal::~InterruptSignal() {
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if (free_event_) Runtime::runtime_singleton_->GetEventPool()->free(event_);
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}
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hsa_signal_value_t InterruptSignal::LoadRelaxed() {
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return hsa_signal_value_t(
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atomic::Load(&signal_.value, std::memory_order_relaxed));
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}
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hsa_signal_value_t InterruptSignal::LoadAcquire() {
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return hsa_signal_value_t(
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atomic::Load(&signal_.value, std::memory_order_acquire));
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}
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void InterruptSignal::StoreRelaxed(hsa_signal_value_t value) {
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atomic::Store(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::StoreRelease(hsa_signal_value_t value) {
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atomic::Store(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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hsa_signal_value_t InterruptSignal::WaitRelaxed(hsa_signal_condition_t condition,
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hsa_signal_value_t compare_value,
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uint64_t timeout,
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hsa_wait_state_t wait_hint) {
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Retain();
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MAKE_SCOPE_GUARD([&]() { Release(); });
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uint32_t prior = waiting_++;
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MAKE_SCOPE_GUARD([&]() { waiting_--; });
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uint64_t event_age = core::Runtime::runtime_singleton_->KfdVersion().supports_event_age ? 1 : 0;
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if (!event_age && prior != 0) wait_hint = HSA_WAIT_STATE_ACTIVE;
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const timer::fast_clock::time_point start_time = timer::fast_clock::now();
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const timer::fast_clock::duration fast_timeout = timer::GetFastTimeout(timeout);
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const timer::fast_clock::duration kMaxElapsed = std::chrono::microseconds(200);
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const uint32_t &signal_abort_timeout =
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core::Runtime::runtime_singleton_->flag().signal_abort_timeout();
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while (true) {
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if (!IsValid()) return 0;
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int64_t value = atomic::Load(&signal_.value, std::memory_order_relaxed);
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if (CheckSignalCondition(value, condition, compare_value)) {
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return value;
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}
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auto now = timer::fast_clock::now();
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if (now - start_time > fast_timeout) {
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return value;
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}
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timer::CheckAbortTimeout(start_time, signal_abort_timeout);
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if (wait_hint == HSA_WAIT_STATE_ACTIVE) {
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if (g_use_mwaitx) {
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// Short timeout for active waiting
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timer::DoMwaitx(const_cast<int64_t*>(&signal_.value), 1000);
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}
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continue;
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}
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if (now - start_time < kMaxElapsed) {
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if (g_use_mwaitx) {
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// Longer timeout with timer for passive waiting
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timer::DoMwaitx(const_cast<int64_t*>(&signal_.value), 60000, true);
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}
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continue;
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}
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auto remaining_ms = timer::duration_cast<std::chrono::milliseconds>(
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fast_timeout - (now - start_time)).count();
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uint32_t wait_ms = std::min<uint32_t>(
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static_cast<uint32_t>(std::min<uint64_t>(remaining_ms, 0xFFFFFFFEUL)),
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static_cast<uint32_t>(signal_abort_timeout ? signal_abort_timeout * 1000 : 0xFFFFFFFFUL)
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);
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HSAKMT_CALL(hsaKmtWaitOnEvent_Ext(event_, wait_ms, &event_age));
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}
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}
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hsa_signal_value_t InterruptSignal::WaitAcquire(
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hsa_signal_condition_t condition, hsa_signal_value_t compare_value,
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uint64_t timeout, hsa_wait_state_t wait_hint) {
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hsa_signal_value_t ret =
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WaitRelaxed(condition, compare_value, timeout, wait_hint);
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std::atomic_thread_fence(std::memory_order_acquire);
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return ret;
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}
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void InterruptSignal::AndRelaxed(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::AndAcquire(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_acquire);
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SetEvent();
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}
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void InterruptSignal::AndRelease(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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void InterruptSignal::AndAcqRel(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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SetEvent();
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}
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void InterruptSignal::OrRelaxed(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::OrAcquire(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_acquire);
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SetEvent();
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}
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void InterruptSignal::OrRelease(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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void InterruptSignal::OrAcqRel(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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SetEvent();
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}
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void InterruptSignal::XorRelaxed(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::XorAcquire(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_acquire);
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SetEvent();
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}
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void InterruptSignal::XorRelease(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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void InterruptSignal::XorAcqRel(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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SetEvent();
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}
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void InterruptSignal::AddRelaxed(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::AddAcquire(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_acquire);
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SetEvent();
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}
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void InterruptSignal::AddRelease(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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void InterruptSignal::AddAcqRel(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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SetEvent();
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}
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void InterruptSignal::SubRelaxed(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_relaxed);
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SetEvent();
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}
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void InterruptSignal::SubAcquire(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_acquire);
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SetEvent();
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}
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void InterruptSignal::SubRelease(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_release);
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SetEvent();
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}
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void InterruptSignal::SubAcqRel(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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SetEvent();
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}
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hsa_signal_value_t InterruptSignal::ExchRelaxed(hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(atomic::Exchange(
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&signal_.value, int64_t(value), std::memory_order_relaxed));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::ExchAcquire(hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(atomic::Exchange(
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&signal_.value, int64_t(value), std::memory_order_acquire));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::ExchRelease(hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(atomic::Exchange(
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&signal_.value, int64_t(value), std::memory_order_release));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::ExchAcqRel(hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(atomic::Exchange(
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&signal_.value, int64_t(value), std::memory_order_acq_rel));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::CasRelaxed(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(
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atomic::Cas(&signal_.value, int64_t(value), int64_t(expected),
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std::memory_order_relaxed));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::CasAcquire(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(
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atomic::Cas(&signal_.value, int64_t(value), int64_t(expected),
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std::memory_order_acquire));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::CasRelease(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(
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atomic::Cas(&signal_.value, int64_t(value), int64_t(expected),
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std::memory_order_release));
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SetEvent();
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return ret;
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}
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hsa_signal_value_t InterruptSignal::CasAcqRel(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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hsa_signal_value_t ret = hsa_signal_value_t(
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atomic::Cas(&signal_.value, int64_t(value), int64_t(expected),
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std::memory_order_acq_rel));
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SetEvent();
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return ret;
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}
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/// @brief Notify driver of signal value change if necessary.
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void InterruptSignal::SetEvent() {
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std::atomic_signal_fence(std::memory_order_seq_cst);
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if (InWaiting()) HSAKMT_CALL(hsaKmtSetEvent(event_));
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}
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} // namespace core
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} // namespace rocr
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