Ammar ELWazir
6eb06cf201
Squashed commit of the following: commit f029195705a15700380c6f832ba5d15d46fd6de7 Author: Jonathan R. Madsen <jrmadsen@users.noreply.github.com> Date: Thu Jul 13 14:38:56 2023 -0500 Formatting workflows for source (clang-format) and cmake (cmake-format) (#4) * Add .cmake-format.yaml file * Add formatting workflow * provide base input for creating PR * Update scheme for extracting branch name - disable running formatting on push to amd-staging branch * patch .cmake-format.yaml for find_package signature - apparently cmake-format doesn't format the full signature of find_package * run formatting (clang-format v11) (#7) Co-authored-by: jrmadsen <jrmadsen@users.noreply.github.com> * run cmake formatting (cmake-format) (#6) Co-authored-by: jrmadsen <jrmadsen@users.noreply.github.com> --------- Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com> commit bc4d135fdd8a1a9e51235f18a5d575fd2b3735e6 Author: Ammar ELWazir <aelwazir@amd.com> Date: Thu Jul 13 12:55:17 2023 -0500 Removing Build cache for potential issues with auto-generated header files (#5) Change-Id: I9e2319f4335e2f88585ffa6fac2bd88a1c952e6e commit ce86dea6a311d44d880fa684eb78f3329295e2a4 Author: Jonathan R. Madsen <jrmadsen@users.noreply.github.com> Date: Thu Jul 13 11:08:58 2023 -0500 Fix decltype(<hsa-function>) function pointer usage (#3) - the following is done in several places: decltype(hsa_memory_allocate)* hsa_memory_allocate - above can cause compiler errors - replace decltype(<hsa-function>) with decltype(::<hsa-function>) - this ensures that the type within the decltype is recognized as the global scope HSA function, not the variable - in many places, the variable has a "_fn" suffix to prevent this issue but added '::' anyway for consistency commit ac49fdd92a72e9c99394253a02da413a6c2e3b3a Merge: a07946a 03a0855 Author: Ammar ELWazir <aelwazir@amd.com> Date: Wed Jul 12 11:36:24 2023 -0500 Merge pull request #2 from ROCm-Developer-Tools/gerrit-amd-staging Pull from gerrit commit 03a085588cffe863e8f466de67be1cfb205b675a Merge:c26b32ba07946a Author: Ammar ELWazir <aelwazir@amd.com> Date: Wed Jul 12 10:57:30 2023 -0500 Merge branch 'amd-staging' into gerrit-amd-staging commit a07946a5cd4c670c83c27ad1a076a9d4567ce6d7 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 15:46:04 2023 +0000 Enabling Cached Builds commit 525e494a7f13941077a8fd4ad6840904db4d27d4 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 04:53:54 2023 +0000 Updating missed GPU Targets commit 42c75862f628c9bee7cfb7dc04dff2619430efbc Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 04:43:02 2023 +0000 Adding V1 Testing commit 9d72fd4aee85e4b0c12e717060d2730fa5b73be1 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:34:31 2023 +0000 Fixing Artifacts directory path commit f4000cc558b3b2e4676f7994f7ce8c8e6f94518e Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:27:26 2023 +0000 Fixing CMake for test build job commit 2ce8115d4c33948c3c8f957f545a95a04e1d6cd2 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 03:16:18 2023 +0000 Fixing Ubuntu CMake for ubuntu test build commit 6d0ed439191be900748d0c025157f9d689a73ec7 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 01:28:41 2023 +0000 Removing Navi21 commit e349a7642e5ae5eb03ab9fcd0a0f74f09f78cab5 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 01:14:14 2023 +0000 Removing Navi21 commit fefd02fe68d2a4bca7ec2e381960ad004ee9fc5b Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:42:48 2023 +0000 Fixing CMake Job commit 2ea46abf7bf92643efa8c549fa70346ffbd79d65 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:35:13 2023 +0000 Fixing CMake Job commit d99d681ed1999c5fcf291dc678b11a77205fb0f3 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Wed Jul 12 00:32:13 2023 +0000 Fixing Pull Latest Dockers and CMake Jobs commit dfc4498072d13b4a1df3a63047d34c682c3d9a29 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 23:54:21 2023 +0000 Fixing CMake job commit 919efe04de707f7c702031be15c3e2c5f8442cbb Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 23:52:13 2023 +0000 Adding Pull Last dockers job commit be1b1256e8b0e05308e8f7e7e69bee3acca55281 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:25:40 2023 -0500 Update cmake.yml commit 212299fa4355ae6ec18f9aaacbb79c51ea6c6f97 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:23:35 2023 -0500 Update cmake.yml commit 7c2c1327086a61466cc6cac39f70865c051a8bc7 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 18:18:53 2023 -0500 Update cmake.yml commit 191b5ce007e612e814c1d7a3afb4ad398f3852e1 Author: Ammar ELWazir <aelwazir@amd.com> Date: Tue Jul 11 16:03:22 2023 -0500 Update cmake.yml commit 8824113d95f3e13c7ce4d0af8e0d9d8f522a6c4a Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 16:28:09 2023 +0000 Fixing Pull from Gerrit job name Change-Id: I9e7ed9a27a13ca49d62c93bdadb30f0057e4d385 commit cc3d5e4b02ffb439e8cc2b3efa53527c376f9982 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 16:21:43 2023 +0000 Adding Staging sync job Change-Id: I0551f43878b0678ce4b3e74e27d62357cf95ad95 commit b9be2eee71380a2e6dd34d520e92d0c4209277a0 Author: Ammar ELWazir <Ammar.ELWazir@amd.com> Date: Tue Jul 11 15:57:11 2023 +0000 Fixing build.sh Change-Id: Ia987b0244f0875370d5fe69907b3f5e9cea914de commit 9eee33a95a1abd656a7ac5ca10a9f245e9825431 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:39:46 2023 -0500 Update cmake.yml commit 7093b85a78497140e8b52632ca2a002bdaeacd62 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:33:29 2023 -0500 Update cmake.yml commit f54697172c72a67740f9fdfa0c217b6ea6931576 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 21:01:26 2023 -0500 Update cmake.yml commit 1b6620e16f8940386b0f4f04e69e2410d21c0e26 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 20:21:02 2023 -0500 Update cmake.yml commit a94bec740c6b42c4b79c87bca20fa87b99bf060d Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:46:35 2023 -0500 Update cmake.yml commit 85d6b29d4375a69d575c18ece8542c50f2ddfcc3 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:34:39 2023 -0500 Update cmake.yml commit 8c004887cf1435f1a6214c3d2455299a8a27bd4c Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:31:17 2023 -0500 Update cmake.yml commit a14a9168e17d9348a53c6e9c9a47ba1edb4c4509 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:25:46 2023 -0500 Update cmake.yml commit 000f2f40b84e6a2f7d4becdbf5aed01436ca4c83 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:08:18 2023 -0500 Update cmake.yml commit a28a53d56731cad848fa9133d1c4dbaa8fc7afa7 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 19:03:39 2023 -0500 Update cmake.yml commit a6a2db01027f0b01fdfbb5997ddb772c7f51b649 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 18:21:53 2023 -0500 Update cmake.yml commit 118ef2a88b2d44e3207c31c343da3e5e5ec6f176 Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 17:55:57 2023 -0500 Update cmake.yml commit 03c4c232396440cd0be6d2dd7baf4ceea1c2589d Author: Ammar ELWazir <aelwazir@amd.com> Date: Mon Jul 10 17:48:49 2023 -0500 Create cmake.yml Change-Id: I77992f15694e77cbae49c56f9ff02f4f9079235d [ROCm/rocprofiler commit:d4a33cf33a]
1050 linhas
33 KiB
C
1050 linhas
33 KiB
C
/*
|
|
* Copyright (C) 2018 Advanced Micro Devices, Inc.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice shall be included
|
|
* in all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
|
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
|
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
#ifndef _vega20_ip_offset_HEADER
|
|
#define _vega20_ip_offset_HEADER
|
|
|
|
#define MAX_INSTANCE 6
|
|
#define MAX_SEGMENT 6
|
|
|
|
|
|
struct IP_BASE_INSTANCE {
|
|
unsigned int segment[MAX_SEGMENT];
|
|
};
|
|
|
|
struct IP_BASE {
|
|
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
|
|
} __maybe_unused;
|
|
|
|
|
|
static const struct IP_BASE ATHUB_BASE = {{{{0x00000C20, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE CLK_BASE = {
|
|
{{{0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE DCE_BASE = {{{{0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE DF_BASE = {{{{0x00007000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE FUSE_BASE = {{{{0x00017400, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE GC_BASE = {{{{0x00002000, 0x0000A000, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE HDP_BASE = {{{{0x00000F20, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE MMHUB_BASE = {{{{0x0001A000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE MP0_BASE = {{{{0x00016000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE MP1_BASE = {{{{0x00016000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE NBIO_BASE = {{{{0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE OSSSYS_BASE = {{{{0x000010A0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE SDMA0_BASE = {{{{0x00001260, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE SDMA1_BASE = {{{{0x00001860, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE SMUIO_BASE = {{{{0x00016800, 0x00016A00, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE THM_BASE = {{{{0x00016600, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE UMC_BASE = {{{{0x00014000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE UVD_BASE = {{{{0x00007800, 0x00007E00, 0, 0, 0, 0}},
|
|
{{0, 0x00009000, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
/* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/
|
|
static const struct IP_BASE VCE_BASE = {{{{0x00007E00 /* 0x00008800 */, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE XDMA_BASE = {{{{0x00003400, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
static const struct IP_BASE RSMU_BASE = {{{{0x00012000, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}},
|
|
{{0, 0, 0, 0, 0, 0}}}};
|
|
|
|
|
|
#define ATHUB_BASE__INST0_SEG0 0x00000C20
|
|
#define ATHUB_BASE__INST0_SEG1 0
|
|
#define ATHUB_BASE__INST0_SEG2 0
|
|
#define ATHUB_BASE__INST0_SEG3 0
|
|
#define ATHUB_BASE__INST0_SEG4 0
|
|
#define ATHUB_BASE__INST0_SEG5 0
|
|
|
|
#define ATHUB_BASE__INST1_SEG0 0
|
|
#define ATHUB_BASE__INST1_SEG1 0
|
|
#define ATHUB_BASE__INST1_SEG2 0
|
|
#define ATHUB_BASE__INST1_SEG3 0
|
|
#define ATHUB_BASE__INST1_SEG4 0
|
|
#define ATHUB_BASE__INST1_SEG5 0
|
|
|
|
#define ATHUB_BASE__INST2_SEG0 0
|
|
#define ATHUB_BASE__INST2_SEG1 0
|
|
#define ATHUB_BASE__INST2_SEG2 0
|
|
#define ATHUB_BASE__INST2_SEG3 0
|
|
#define ATHUB_BASE__INST2_SEG4 0
|
|
#define ATHUB_BASE__INST2_SEG5 0
|
|
|
|
#define ATHUB_BASE__INST3_SEG0 0
|
|
#define ATHUB_BASE__INST3_SEG1 0
|
|
#define ATHUB_BASE__INST3_SEG2 0
|
|
#define ATHUB_BASE__INST3_SEG3 0
|
|
#define ATHUB_BASE__INST3_SEG4 0
|
|
#define ATHUB_BASE__INST3_SEG5 0
|
|
|
|
#define ATHUB_BASE__INST4_SEG0 0
|
|
#define ATHUB_BASE__INST4_SEG1 0
|
|
#define ATHUB_BASE__INST4_SEG2 0
|
|
#define ATHUB_BASE__INST4_SEG3 0
|
|
#define ATHUB_BASE__INST4_SEG4 0
|
|
#define ATHUB_BASE__INST4_SEG5 0
|
|
|
|
#define ATHUB_BASE__INST5_SEG0 0
|
|
#define ATHUB_BASE__INST5_SEG1 0
|
|
#define ATHUB_BASE__INST5_SEG2 0
|
|
#define ATHUB_BASE__INST5_SEG3 0
|
|
#define ATHUB_BASE__INST5_SEG4 0
|
|
#define ATHUB_BASE__INST5_SEG5 0
|
|
|
|
#define CLK_BASE__INST0_SEG0 0x00016C00
|
|
#define CLK_BASE__INST0_SEG1 0x00016E00
|
|
#define CLK_BASE__INST0_SEG2 0x00017000
|
|
#define CLK_BASE__INST0_SEG3 0x00017200
|
|
#define CLK_BASE__INST0_SEG4 0x0001B000
|
|
#define CLK_BASE__INST0_SEG5 0x0001B200
|
|
|
|
#define CLK_BASE__INST1_SEG0 0
|
|
#define CLK_BASE__INST1_SEG1 0
|
|
#define CLK_BASE__INST1_SEG2 0
|
|
#define CLK_BASE__INST1_SEG3 0
|
|
#define CLK_BASE__INST1_SEG4 0
|
|
#define CLK_BASE__INST1_SEG5 0
|
|
|
|
#define CLK_BASE__INST2_SEG0 0
|
|
#define CLK_BASE__INST2_SEG1 0
|
|
#define CLK_BASE__INST2_SEG2 0
|
|
#define CLK_BASE__INST2_SEG3 0
|
|
#define CLK_BASE__INST2_SEG4 0
|
|
#define CLK_BASE__INST2_SEG5 0
|
|
|
|
#define CLK_BASE__INST3_SEG0 0
|
|
#define CLK_BASE__INST3_SEG1 0
|
|
#define CLK_BASE__INST3_SEG2 0
|
|
#define CLK_BASE__INST3_SEG3 0
|
|
#define CLK_BASE__INST3_SEG4 0
|
|
#define CLK_BASE__INST3_SEG5 0
|
|
|
|
#define CLK_BASE__INST4_SEG0 0
|
|
#define CLK_BASE__INST4_SEG1 0
|
|
#define CLK_BASE__INST4_SEG2 0
|
|
#define CLK_BASE__INST4_SEG3 0
|
|
#define CLK_BASE__INST4_SEG4 0
|
|
#define CLK_BASE__INST4_SEG5 0
|
|
|
|
#define CLK_BASE__INST5_SEG0 0
|
|
#define CLK_BASE__INST5_SEG1 0
|
|
#define CLK_BASE__INST5_SEG2 0
|
|
#define CLK_BASE__INST5_SEG3 0
|
|
#define CLK_BASE__INST5_SEG4 0
|
|
#define CLK_BASE__INST5_SEG5 0
|
|
|
|
#define DCE_BASE__INST0_SEG0 0x00000012
|
|
#define DCE_BASE__INST0_SEG1 0x000000C0
|
|
#define DCE_BASE__INST0_SEG2 0x000034C0
|
|
#define DCE_BASE__INST0_SEG3 0
|
|
#define DCE_BASE__INST0_SEG4 0
|
|
#define DCE_BASE__INST0_SEG5 0
|
|
|
|
#define DCE_BASE__INST1_SEG0 0
|
|
#define DCE_BASE__INST1_SEG1 0
|
|
#define DCE_BASE__INST1_SEG2 0
|
|
#define DCE_BASE__INST1_SEG3 0
|
|
#define DCE_BASE__INST1_SEG4 0
|
|
#define DCE_BASE__INST1_SEG5 0
|
|
|
|
#define DCE_BASE__INST2_SEG0 0
|
|
#define DCE_BASE__INST2_SEG1 0
|
|
#define DCE_BASE__INST2_SEG2 0
|
|
#define DCE_BASE__INST2_SEG3 0
|
|
#define DCE_BASE__INST2_SEG4 0
|
|
#define DCE_BASE__INST2_SEG5 0
|
|
|
|
#define DCE_BASE__INST3_SEG0 0
|
|
#define DCE_BASE__INST3_SEG1 0
|
|
#define DCE_BASE__INST3_SEG2 0
|
|
#define DCE_BASE__INST3_SEG3 0
|
|
#define DCE_BASE__INST3_SEG4 0
|
|
#define DCE_BASE__INST3_SEG5 0
|
|
|
|
#define DCE_BASE__INST4_SEG0 0
|
|
#define DCE_BASE__INST4_SEG1 0
|
|
#define DCE_BASE__INST4_SEG2 0
|
|
#define DCE_BASE__INST4_SEG3 0
|
|
#define DCE_BASE__INST4_SEG4 0
|
|
#define DCE_BASE__INST4_SEG5 0
|
|
|
|
#define DCE_BASE__INST5_SEG0 0
|
|
#define DCE_BASE__INST5_SEG1 0
|
|
#define DCE_BASE__INST5_SEG2 0
|
|
#define DCE_BASE__INST5_SEG3 0
|
|
#define DCE_BASE__INST5_SEG4 0
|
|
#define DCE_BASE__INST5_SEG5 0
|
|
|
|
#define DF_BASE__INST0_SEG0 0x00007000
|
|
#define DF_BASE__INST0_SEG1 0
|
|
#define DF_BASE__INST0_SEG2 0
|
|
#define DF_BASE__INST0_SEG3 0
|
|
#define DF_BASE__INST0_SEG4 0
|
|
#define DF_BASE__INST0_SEG5 0
|
|
|
|
#define DF_BASE__INST1_SEG0 0
|
|
#define DF_BASE__INST1_SEG1 0
|
|
#define DF_BASE__INST1_SEG2 0
|
|
#define DF_BASE__INST1_SEG3 0
|
|
#define DF_BASE__INST1_SEG4 0
|
|
#define DF_BASE__INST1_SEG5 0
|
|
|
|
#define DF_BASE__INST2_SEG0 0
|
|
#define DF_BASE__INST2_SEG1 0
|
|
#define DF_BASE__INST2_SEG2 0
|
|
#define DF_BASE__INST2_SEG3 0
|
|
#define DF_BASE__INST2_SEG4 0
|
|
#define DF_BASE__INST2_SEG5 0
|
|
|
|
#define DF_BASE__INST3_SEG0 0
|
|
#define DF_BASE__INST3_SEG1 0
|
|
#define DF_BASE__INST3_SEG2 0
|
|
#define DF_BASE__INST3_SEG3 0
|
|
#define DF_BASE__INST3_SEG4 0
|
|
#define DF_BASE__INST3_SEG5 0
|
|
|
|
#define DF_BASE__INST4_SEG0 0
|
|
#define DF_BASE__INST4_SEG1 0
|
|
#define DF_BASE__INST4_SEG2 0
|
|
#define DF_BASE__INST4_SEG3 0
|
|
#define DF_BASE__INST4_SEG4 0
|
|
#define DF_BASE__INST4_SEG5 0
|
|
|
|
#define DF_BASE__INST5_SEG0 0
|
|
#define DF_BASE__INST5_SEG1 0
|
|
#define DF_BASE__INST5_SEG2 0
|
|
#define DF_BASE__INST5_SEG3 0
|
|
#define DF_BASE__INST5_SEG4 0
|
|
#define DF_BASE__INST5_SEG5 0
|
|
|
|
#define FUSE_BASE__INST0_SEG0 0x00017400
|
|
#define FUSE_BASE__INST0_SEG1 0
|
|
#define FUSE_BASE__INST0_SEG2 0
|
|
#define FUSE_BASE__INST0_SEG3 0
|
|
#define FUSE_BASE__INST0_SEG4 0
|
|
#define FUSE_BASE__INST0_SEG5 0
|
|
|
|
#define FUSE_BASE__INST1_SEG0 0
|
|
#define FUSE_BASE__INST1_SEG1 0
|
|
#define FUSE_BASE__INST1_SEG2 0
|
|
#define FUSE_BASE__INST1_SEG3 0
|
|
#define FUSE_BASE__INST1_SEG4 0
|
|
#define FUSE_BASE__INST1_SEG5 0
|
|
|
|
#define FUSE_BASE__INST2_SEG0 0
|
|
#define FUSE_BASE__INST2_SEG1 0
|
|
#define FUSE_BASE__INST2_SEG2 0
|
|
#define FUSE_BASE__INST2_SEG3 0
|
|
#define FUSE_BASE__INST2_SEG4 0
|
|
#define FUSE_BASE__INST2_SEG5 0
|
|
|
|
#define FUSE_BASE__INST3_SEG0 0
|
|
#define FUSE_BASE__INST3_SEG1 0
|
|
#define FUSE_BASE__INST3_SEG2 0
|
|
#define FUSE_BASE__INST3_SEG3 0
|
|
#define FUSE_BASE__INST3_SEG4 0
|
|
#define FUSE_BASE__INST3_SEG5 0
|
|
|
|
#define FUSE_BASE__INST4_SEG0 0
|
|
#define FUSE_BASE__INST4_SEG1 0
|
|
#define FUSE_BASE__INST4_SEG2 0
|
|
#define FUSE_BASE__INST4_SEG3 0
|
|
#define FUSE_BASE__INST4_SEG4 0
|
|
#define FUSE_BASE__INST4_SEG5 0
|
|
|
|
#define FUSE_BASE__INST5_SEG0 0
|
|
#define FUSE_BASE__INST5_SEG1 0
|
|
#define FUSE_BASE__INST5_SEG2 0
|
|
#define FUSE_BASE__INST5_SEG3 0
|
|
#define FUSE_BASE__INST5_SEG4 0
|
|
#define FUSE_BASE__INST5_SEG5 0
|
|
|
|
#define GC_BASE__INST0_SEG0 0x00002000
|
|
#define GC_BASE__INST0_SEG1 0x0000A000
|
|
#define GC_BASE__INST0_SEG2 0
|
|
#define GC_BASE__INST0_SEG3 0
|
|
#define GC_BASE__INST0_SEG4 0
|
|
#define GC_BASE__INST0_SEG5 0
|
|
|
|
#define GC_BASE__INST1_SEG0 0
|
|
#define GC_BASE__INST1_SEG1 0
|
|
#define GC_BASE__INST1_SEG2 0
|
|
#define GC_BASE__INST1_SEG3 0
|
|
#define GC_BASE__INST1_SEG4 0
|
|
#define GC_BASE__INST1_SEG5 0
|
|
|
|
#define GC_BASE__INST2_SEG0 0
|
|
#define GC_BASE__INST2_SEG1 0
|
|
#define GC_BASE__INST2_SEG2 0
|
|
#define GC_BASE__INST2_SEG3 0
|
|
#define GC_BASE__INST2_SEG4 0
|
|
#define GC_BASE__INST2_SEG5 0
|
|
|
|
#define GC_BASE__INST3_SEG0 0
|
|
#define GC_BASE__INST3_SEG1 0
|
|
#define GC_BASE__INST3_SEG2 0
|
|
#define GC_BASE__INST3_SEG3 0
|
|
#define GC_BASE__INST3_SEG4 0
|
|
#define GC_BASE__INST3_SEG5 0
|
|
|
|
#define GC_BASE__INST4_SEG0 0
|
|
#define GC_BASE__INST4_SEG1 0
|
|
#define GC_BASE__INST4_SEG2 0
|
|
#define GC_BASE__INST4_SEG3 0
|
|
#define GC_BASE__INST4_SEG4 0
|
|
#define GC_BASE__INST4_SEG5 0
|
|
|
|
#define GC_BASE__INST5_SEG0 0
|
|
#define GC_BASE__INST5_SEG1 0
|
|
#define GC_BASE__INST5_SEG2 0
|
|
#define GC_BASE__INST5_SEG3 0
|
|
#define GC_BASE__INST5_SEG4 0
|
|
#define GC_BASE__INST5_SEG5 0
|
|
|
|
#define HDP_BASE__INST0_SEG0 0x00000F20
|
|
#define HDP_BASE__INST0_SEG1 0
|
|
#define HDP_BASE__INST0_SEG2 0
|
|
#define HDP_BASE__INST0_SEG3 0
|
|
#define HDP_BASE__INST0_SEG4 0
|
|
#define HDP_BASE__INST0_SEG5 0
|
|
|
|
#define HDP_BASE__INST1_SEG0 0
|
|
#define HDP_BASE__INST1_SEG1 0
|
|
#define HDP_BASE__INST1_SEG2 0
|
|
#define HDP_BASE__INST1_SEG3 0
|
|
#define HDP_BASE__INST1_SEG4 0
|
|
#define HDP_BASE__INST1_SEG5 0
|
|
|
|
#define HDP_BASE__INST2_SEG0 0
|
|
#define HDP_BASE__INST2_SEG1 0
|
|
#define HDP_BASE__INST2_SEG2 0
|
|
#define HDP_BASE__INST2_SEG3 0
|
|
#define HDP_BASE__INST2_SEG4 0
|
|
#define HDP_BASE__INST2_SEG5 0
|
|
|
|
#define HDP_BASE__INST3_SEG0 0
|
|
#define HDP_BASE__INST3_SEG1 0
|
|
#define HDP_BASE__INST3_SEG2 0
|
|
#define HDP_BASE__INST3_SEG3 0
|
|
#define HDP_BASE__INST3_SEG4 0
|
|
#define HDP_BASE__INST3_SEG5 0
|
|
|
|
#define HDP_BASE__INST4_SEG0 0
|
|
#define HDP_BASE__INST4_SEG1 0
|
|
#define HDP_BASE__INST4_SEG2 0
|
|
#define HDP_BASE__INST4_SEG3 0
|
|
#define HDP_BASE__INST4_SEG4 0
|
|
#define HDP_BASE__INST4_SEG5 0
|
|
|
|
#define HDP_BASE__INST5_SEG0 0
|
|
#define HDP_BASE__INST5_SEG1 0
|
|
#define HDP_BASE__INST5_SEG2 0
|
|
#define HDP_BASE__INST5_SEG3 0
|
|
#define HDP_BASE__INST5_SEG4 0
|
|
#define HDP_BASE__INST5_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST0_SEG0 0x0001A000
|
|
#define MMHUB_BASE__INST0_SEG1 0
|
|
#define MMHUB_BASE__INST0_SEG2 0
|
|
#define MMHUB_BASE__INST0_SEG3 0
|
|
#define MMHUB_BASE__INST0_SEG4 0
|
|
#define MMHUB_BASE__INST0_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST1_SEG0 0
|
|
#define MMHUB_BASE__INST1_SEG1 0
|
|
#define MMHUB_BASE__INST1_SEG2 0
|
|
#define MMHUB_BASE__INST1_SEG3 0
|
|
#define MMHUB_BASE__INST1_SEG4 0
|
|
#define MMHUB_BASE__INST1_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST2_SEG0 0
|
|
#define MMHUB_BASE__INST2_SEG1 0
|
|
#define MMHUB_BASE__INST2_SEG2 0
|
|
#define MMHUB_BASE__INST2_SEG3 0
|
|
#define MMHUB_BASE__INST2_SEG4 0
|
|
#define MMHUB_BASE__INST2_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST3_SEG0 0
|
|
#define MMHUB_BASE__INST3_SEG1 0
|
|
#define MMHUB_BASE__INST3_SEG2 0
|
|
#define MMHUB_BASE__INST3_SEG3 0
|
|
#define MMHUB_BASE__INST3_SEG4 0
|
|
#define MMHUB_BASE__INST3_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST4_SEG0 0
|
|
#define MMHUB_BASE__INST4_SEG1 0
|
|
#define MMHUB_BASE__INST4_SEG2 0
|
|
#define MMHUB_BASE__INST4_SEG3 0
|
|
#define MMHUB_BASE__INST4_SEG4 0
|
|
#define MMHUB_BASE__INST4_SEG5 0
|
|
|
|
#define MMHUB_BASE__INST5_SEG0 0
|
|
#define MMHUB_BASE__INST5_SEG1 0
|
|
#define MMHUB_BASE__INST5_SEG2 0
|
|
#define MMHUB_BASE__INST5_SEG3 0
|
|
#define MMHUB_BASE__INST5_SEG4 0
|
|
#define MMHUB_BASE__INST5_SEG5 0
|
|
|
|
#define MP0_BASE__INST0_SEG0 0x00016000
|
|
#define MP0_BASE__INST0_SEG1 0
|
|
#define MP0_BASE__INST0_SEG2 0
|
|
#define MP0_BASE__INST0_SEG3 0
|
|
#define MP0_BASE__INST0_SEG4 0
|
|
#define MP0_BASE__INST0_SEG5 0
|
|
|
|
#define MP0_BASE__INST1_SEG0 0
|
|
#define MP0_BASE__INST1_SEG1 0
|
|
#define MP0_BASE__INST1_SEG2 0
|
|
#define MP0_BASE__INST1_SEG3 0
|
|
#define MP0_BASE__INST1_SEG4 0
|
|
#define MP0_BASE__INST1_SEG5 0
|
|
|
|
#define MP0_BASE__INST2_SEG0 0
|
|
#define MP0_BASE__INST2_SEG1 0
|
|
#define MP0_BASE__INST2_SEG2 0
|
|
#define MP0_BASE__INST2_SEG3 0
|
|
#define MP0_BASE__INST2_SEG4 0
|
|
#define MP0_BASE__INST2_SEG5 0
|
|
|
|
#define MP0_BASE__INST3_SEG0 0
|
|
#define MP0_BASE__INST3_SEG1 0
|
|
#define MP0_BASE__INST3_SEG2 0
|
|
#define MP0_BASE__INST3_SEG3 0
|
|
#define MP0_BASE__INST3_SEG4 0
|
|
#define MP0_BASE__INST3_SEG5 0
|
|
|
|
#define MP0_BASE__INST4_SEG0 0
|
|
#define MP0_BASE__INST4_SEG1 0
|
|
#define MP0_BASE__INST4_SEG2 0
|
|
#define MP0_BASE__INST4_SEG3 0
|
|
#define MP0_BASE__INST4_SEG4 0
|
|
#define MP0_BASE__INST4_SEG5 0
|
|
|
|
#define MP0_BASE__INST5_SEG0 0
|
|
#define MP0_BASE__INST5_SEG1 0
|
|
#define MP0_BASE__INST5_SEG2 0
|
|
#define MP0_BASE__INST5_SEG3 0
|
|
#define MP0_BASE__INST5_SEG4 0
|
|
#define MP0_BASE__INST5_SEG5 0
|
|
|
|
#define MP1_BASE__INST0_SEG0 0x00016000
|
|
#define MP1_BASE__INST0_SEG1 0
|
|
#define MP1_BASE__INST0_SEG2 0
|
|
#define MP1_BASE__INST0_SEG3 0
|
|
#define MP1_BASE__INST0_SEG4 0
|
|
#define MP1_BASE__INST0_SEG5 0
|
|
|
|
#define MP1_BASE__INST1_SEG0 0
|
|
#define MP1_BASE__INST1_SEG1 0
|
|
#define MP1_BASE__INST1_SEG2 0
|
|
#define MP1_BASE__INST1_SEG3 0
|
|
#define MP1_BASE__INST1_SEG4 0
|
|
#define MP1_BASE__INST1_SEG5 0
|
|
|
|
#define MP1_BASE__INST2_SEG0 0
|
|
#define MP1_BASE__INST2_SEG1 0
|
|
#define MP1_BASE__INST2_SEG2 0
|
|
#define MP1_BASE__INST2_SEG3 0
|
|
#define MP1_BASE__INST2_SEG4 0
|
|
#define MP1_BASE__INST2_SEG5 0
|
|
|
|
#define MP1_BASE__INST3_SEG0 0
|
|
#define MP1_BASE__INST3_SEG1 0
|
|
#define MP1_BASE__INST3_SEG2 0
|
|
#define MP1_BASE__INST3_SEG3 0
|
|
#define MP1_BASE__INST3_SEG4 0
|
|
#define MP1_BASE__INST3_SEG5 0
|
|
|
|
#define MP1_BASE__INST4_SEG0 0
|
|
#define MP1_BASE__INST4_SEG1 0
|
|
#define MP1_BASE__INST4_SEG2 0
|
|
#define MP1_BASE__INST4_SEG3 0
|
|
#define MP1_BASE__INST4_SEG4 0
|
|
#define MP1_BASE__INST4_SEG5 0
|
|
|
|
#define MP1_BASE__INST5_SEG0 0
|
|
#define MP1_BASE__INST5_SEG1 0
|
|
#define MP1_BASE__INST5_SEG2 0
|
|
#define MP1_BASE__INST5_SEG3 0
|
|
#define MP1_BASE__INST5_SEG4 0
|
|
#define MP1_BASE__INST5_SEG5 0
|
|
|
|
#define NBIO_BASE__INST0_SEG0 0x00000000
|
|
#define NBIO_BASE__INST0_SEG1 0x00000014
|
|
#define NBIO_BASE__INST0_SEG2 0x00000D20
|
|
#define NBIO_BASE__INST0_SEG3 0x00010400
|
|
#define NBIO_BASE__INST0_SEG4 0
|
|
#define NBIO_BASE__INST0_SEG5 0
|
|
|
|
#define NBIO_BASE__INST1_SEG0 0
|
|
#define NBIO_BASE__INST1_SEG1 0
|
|
#define NBIO_BASE__INST1_SEG2 0
|
|
#define NBIO_BASE__INST1_SEG3 0
|
|
#define NBIO_BASE__INST1_SEG4 0
|
|
#define NBIO_BASE__INST1_SEG5 0
|
|
|
|
#define NBIO_BASE__INST2_SEG0 0
|
|
#define NBIO_BASE__INST2_SEG1 0
|
|
#define NBIO_BASE__INST2_SEG2 0
|
|
#define NBIO_BASE__INST2_SEG3 0
|
|
#define NBIO_BASE__INST2_SEG4 0
|
|
#define NBIO_BASE__INST2_SEG5 0
|
|
|
|
#define NBIO_BASE__INST3_SEG0 0
|
|
#define NBIO_BASE__INST3_SEG1 0
|
|
#define NBIO_BASE__INST3_SEG2 0
|
|
#define NBIO_BASE__INST3_SEG3 0
|
|
#define NBIO_BASE__INST3_SEG4 0
|
|
#define NBIO_BASE__INST3_SEG5 0
|
|
|
|
#define NBIO_BASE__INST4_SEG0 0
|
|
#define NBIO_BASE__INST4_SEG1 0
|
|
#define NBIO_BASE__INST4_SEG2 0
|
|
#define NBIO_BASE__INST4_SEG3 0
|
|
#define NBIO_BASE__INST4_SEG4 0
|
|
#define NBIO_BASE__INST4_SEG5 0
|
|
|
|
#define NBIO_BASE__INST5_SEG0 0
|
|
#define NBIO_BASE__INST5_SEG1 0
|
|
#define NBIO_BASE__INST5_SEG2 0
|
|
#define NBIO_BASE__INST5_SEG3 0
|
|
#define NBIO_BASE__INST5_SEG4 0
|
|
#define NBIO_BASE__INST5_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST0_SEG0 0x000010A0
|
|
#define OSSSYS_BASE__INST0_SEG1 0
|
|
#define OSSSYS_BASE__INST0_SEG2 0
|
|
#define OSSSYS_BASE__INST0_SEG3 0
|
|
#define OSSSYS_BASE__INST0_SEG4 0
|
|
#define OSSSYS_BASE__INST0_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST1_SEG0 0
|
|
#define OSSSYS_BASE__INST1_SEG1 0
|
|
#define OSSSYS_BASE__INST1_SEG2 0
|
|
#define OSSSYS_BASE__INST1_SEG3 0
|
|
#define OSSSYS_BASE__INST1_SEG4 0
|
|
#define OSSSYS_BASE__INST1_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST2_SEG0 0
|
|
#define OSSSYS_BASE__INST2_SEG1 0
|
|
#define OSSSYS_BASE__INST2_SEG2 0
|
|
#define OSSSYS_BASE__INST2_SEG3 0
|
|
#define OSSSYS_BASE__INST2_SEG4 0
|
|
#define OSSSYS_BASE__INST2_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST3_SEG0 0
|
|
#define OSSSYS_BASE__INST3_SEG1 0
|
|
#define OSSSYS_BASE__INST3_SEG2 0
|
|
#define OSSSYS_BASE__INST3_SEG3 0
|
|
#define OSSSYS_BASE__INST3_SEG4 0
|
|
#define OSSSYS_BASE__INST3_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST4_SEG0 0
|
|
#define OSSSYS_BASE__INST4_SEG1 0
|
|
#define OSSSYS_BASE__INST4_SEG2 0
|
|
#define OSSSYS_BASE__INST4_SEG3 0
|
|
#define OSSSYS_BASE__INST4_SEG4 0
|
|
#define OSSSYS_BASE__INST4_SEG5 0
|
|
|
|
#define OSSSYS_BASE__INST5_SEG0 0
|
|
#define OSSSYS_BASE__INST5_SEG1 0
|
|
#define OSSSYS_BASE__INST5_SEG2 0
|
|
#define OSSSYS_BASE__INST5_SEG3 0
|
|
#define OSSSYS_BASE__INST5_SEG4 0
|
|
#define OSSSYS_BASE__INST5_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST0_SEG0 0x00001260
|
|
#define SDMA0_BASE__INST0_SEG1 0
|
|
#define SDMA0_BASE__INST0_SEG2 0
|
|
#define SDMA0_BASE__INST0_SEG3 0
|
|
#define SDMA0_BASE__INST0_SEG4 0
|
|
#define SDMA0_BASE__INST0_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST1_SEG0 0
|
|
#define SDMA0_BASE__INST1_SEG1 0
|
|
#define SDMA0_BASE__INST1_SEG2 0
|
|
#define SDMA0_BASE__INST1_SEG3 0
|
|
#define SDMA0_BASE__INST1_SEG4 0
|
|
#define SDMA0_BASE__INST1_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST2_SEG0 0
|
|
#define SDMA0_BASE__INST2_SEG1 0
|
|
#define SDMA0_BASE__INST2_SEG2 0
|
|
#define SDMA0_BASE__INST2_SEG3 0
|
|
#define SDMA0_BASE__INST2_SEG4 0
|
|
#define SDMA0_BASE__INST2_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST3_SEG0 0
|
|
#define SDMA0_BASE__INST3_SEG1 0
|
|
#define SDMA0_BASE__INST3_SEG2 0
|
|
#define SDMA0_BASE__INST3_SEG3 0
|
|
#define SDMA0_BASE__INST3_SEG4 0
|
|
#define SDMA0_BASE__INST3_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST4_SEG0 0
|
|
#define SDMA0_BASE__INST4_SEG1 0
|
|
#define SDMA0_BASE__INST4_SEG2 0
|
|
#define SDMA0_BASE__INST4_SEG3 0
|
|
#define SDMA0_BASE__INST4_SEG4 0
|
|
#define SDMA0_BASE__INST4_SEG5 0
|
|
|
|
#define SDMA0_BASE__INST5_SEG0 0
|
|
#define SDMA0_BASE__INST5_SEG1 0
|
|
#define SDMA0_BASE__INST5_SEG2 0
|
|
#define SDMA0_BASE__INST5_SEG3 0
|
|
#define SDMA0_BASE__INST5_SEG4 0
|
|
#define SDMA0_BASE__INST5_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST0_SEG0 0x00001860
|
|
#define SDMA1_BASE__INST0_SEG1 0
|
|
#define SDMA1_BASE__INST0_SEG2 0
|
|
#define SDMA1_BASE__INST0_SEG3 0
|
|
#define SDMA1_BASE__INST0_SEG4 0
|
|
#define SDMA1_BASE__INST0_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST1_SEG0 0
|
|
#define SDMA1_BASE__INST1_SEG1 0
|
|
#define SDMA1_BASE__INST1_SEG2 0
|
|
#define SDMA1_BASE__INST1_SEG3 0
|
|
#define SDMA1_BASE__INST1_SEG4 0
|
|
#define SDMA1_BASE__INST1_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST2_SEG0 0
|
|
#define SDMA1_BASE__INST2_SEG1 0
|
|
#define SDMA1_BASE__INST2_SEG2 0
|
|
#define SDMA1_BASE__INST2_SEG3 0
|
|
#define SDMA1_BASE__INST2_SEG4 0
|
|
#define SDMA1_BASE__INST2_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST3_SEG0 0
|
|
#define SDMA1_BASE__INST3_SEG1 0
|
|
#define SDMA1_BASE__INST3_SEG2 0
|
|
#define SDMA1_BASE__INST3_SEG3 0
|
|
#define SDMA1_BASE__INST3_SEG4 0
|
|
#define SDMA1_BASE__INST3_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST4_SEG0 0
|
|
#define SDMA1_BASE__INST4_SEG1 0
|
|
#define SDMA1_BASE__INST4_SEG2 0
|
|
#define SDMA1_BASE__INST4_SEG3 0
|
|
#define SDMA1_BASE__INST4_SEG4 0
|
|
#define SDMA1_BASE__INST4_SEG5 0
|
|
|
|
#define SDMA1_BASE__INST5_SEG0 0
|
|
#define SDMA1_BASE__INST5_SEG1 0
|
|
#define SDMA1_BASE__INST5_SEG2 0
|
|
#define SDMA1_BASE__INST5_SEG3 0
|
|
#define SDMA1_BASE__INST5_SEG4 0
|
|
#define SDMA1_BASE__INST5_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST0_SEG0 0x00016800
|
|
#define SMUIO_BASE__INST0_SEG1 0x00016A00
|
|
#define SMUIO_BASE__INST0_SEG2 0
|
|
#define SMUIO_BASE__INST0_SEG3 0
|
|
#define SMUIO_BASE__INST0_SEG4 0
|
|
#define SMUIO_BASE__INST0_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST1_SEG0 0
|
|
#define SMUIO_BASE__INST1_SEG1 0
|
|
#define SMUIO_BASE__INST1_SEG2 0
|
|
#define SMUIO_BASE__INST1_SEG3 0
|
|
#define SMUIO_BASE__INST1_SEG4 0
|
|
#define SMUIO_BASE__INST1_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST2_SEG0 0
|
|
#define SMUIO_BASE__INST2_SEG1 0
|
|
#define SMUIO_BASE__INST2_SEG2 0
|
|
#define SMUIO_BASE__INST2_SEG3 0
|
|
#define SMUIO_BASE__INST2_SEG4 0
|
|
#define SMUIO_BASE__INST2_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST3_SEG0 0
|
|
#define SMUIO_BASE__INST3_SEG1 0
|
|
#define SMUIO_BASE__INST3_SEG2 0
|
|
#define SMUIO_BASE__INST3_SEG3 0
|
|
#define SMUIO_BASE__INST3_SEG4 0
|
|
#define SMUIO_BASE__INST3_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST4_SEG0 0
|
|
#define SMUIO_BASE__INST4_SEG1 0
|
|
#define SMUIO_BASE__INST4_SEG2 0
|
|
#define SMUIO_BASE__INST4_SEG3 0
|
|
#define SMUIO_BASE__INST4_SEG4 0
|
|
#define SMUIO_BASE__INST4_SEG5 0
|
|
|
|
#define SMUIO_BASE__INST5_SEG0 0
|
|
#define SMUIO_BASE__INST5_SEG1 0
|
|
#define SMUIO_BASE__INST5_SEG2 0
|
|
#define SMUIO_BASE__INST5_SEG3 0
|
|
#define SMUIO_BASE__INST5_SEG4 0
|
|
#define SMUIO_BASE__INST5_SEG5 0
|
|
|
|
#define THM_BASE__INST0_SEG0 0x00016600
|
|
#define THM_BASE__INST0_SEG1 0
|
|
#define THM_BASE__INST0_SEG2 0
|
|
#define THM_BASE__INST0_SEG3 0
|
|
#define THM_BASE__INST0_SEG4 0
|
|
#define THM_BASE__INST0_SEG5 0
|
|
|
|
#define THM_BASE__INST1_SEG0 0
|
|
#define THM_BASE__INST1_SEG1 0
|
|
#define THM_BASE__INST1_SEG2 0
|
|
#define THM_BASE__INST1_SEG3 0
|
|
#define THM_BASE__INST1_SEG4 0
|
|
#define THM_BASE__INST1_SEG5 0
|
|
|
|
#define THM_BASE__INST2_SEG0 0
|
|
#define THM_BASE__INST2_SEG1 0
|
|
#define THM_BASE__INST2_SEG2 0
|
|
#define THM_BASE__INST2_SEG3 0
|
|
#define THM_BASE__INST2_SEG4 0
|
|
#define THM_BASE__INST2_SEG5 0
|
|
|
|
#define THM_BASE__INST3_SEG0 0
|
|
#define THM_BASE__INST3_SEG1 0
|
|
#define THM_BASE__INST3_SEG2 0
|
|
#define THM_BASE__INST3_SEG3 0
|
|
#define THM_BASE__INST3_SEG4 0
|
|
#define THM_BASE__INST3_SEG5 0
|
|
|
|
#define THM_BASE__INST4_SEG0 0
|
|
#define THM_BASE__INST4_SEG1 0
|
|
#define THM_BASE__INST4_SEG2 0
|
|
#define THM_BASE__INST4_SEG3 0
|
|
#define THM_BASE__INST4_SEG4 0
|
|
#define THM_BASE__INST4_SEG5 0
|
|
|
|
#define THM_BASE__INST5_SEG0 0
|
|
#define THM_BASE__INST5_SEG1 0
|
|
#define THM_BASE__INST5_SEG2 0
|
|
#define THM_BASE__INST5_SEG3 0
|
|
#define THM_BASE__INST5_SEG4 0
|
|
#define THM_BASE__INST5_SEG5 0
|
|
|
|
#define UMC_BASE__INST0_SEG0 0x00014000
|
|
#define UMC_BASE__INST0_SEG1 0
|
|
#define UMC_BASE__INST0_SEG2 0
|
|
#define UMC_BASE__INST0_SEG3 0
|
|
#define UMC_BASE__INST0_SEG4 0
|
|
#define UMC_BASE__INST0_SEG5 0
|
|
|
|
#define UMC_BASE__INST1_SEG0 0
|
|
#define UMC_BASE__INST1_SEG1 0
|
|
#define UMC_BASE__INST1_SEG2 0
|
|
#define UMC_BASE__INST1_SEG3 0
|
|
#define UMC_BASE__INST1_SEG4 0
|
|
#define UMC_BASE__INST1_SEG5 0
|
|
|
|
#define UMC_BASE__INST2_SEG0 0
|
|
#define UMC_BASE__INST2_SEG1 0
|
|
#define UMC_BASE__INST2_SEG2 0
|
|
#define UMC_BASE__INST2_SEG3 0
|
|
#define UMC_BASE__INST2_SEG4 0
|
|
#define UMC_BASE__INST2_SEG5 0
|
|
|
|
#define UMC_BASE__INST3_SEG0 0
|
|
#define UMC_BASE__INST3_SEG1 0
|
|
#define UMC_BASE__INST3_SEG2 0
|
|
#define UMC_BASE__INST3_SEG3 0
|
|
#define UMC_BASE__INST3_SEG4 0
|
|
#define UMC_BASE__INST3_SEG5 0
|
|
|
|
#define UMC_BASE__INST4_SEG0 0
|
|
#define UMC_BASE__INST4_SEG1 0
|
|
#define UMC_BASE__INST4_SEG2 0
|
|
#define UMC_BASE__INST4_SEG3 0
|
|
#define UMC_BASE__INST4_SEG4 0
|
|
#define UMC_BASE__INST4_SEG5 0
|
|
|
|
#define UMC_BASE__INST5_SEG0 0
|
|
#define UMC_BASE__INST5_SEG1 0
|
|
#define UMC_BASE__INST5_SEG2 0
|
|
#define UMC_BASE__INST5_SEG3 0
|
|
#define UMC_BASE__INST5_SEG4 0
|
|
#define UMC_BASE__INST5_SEG5 0
|
|
|
|
#define UVD_BASE__INST0_SEG0 0x00007800
|
|
#define UVD_BASE__INST0_SEG1 0x00007E00
|
|
#define UVD_BASE__INST0_SEG2 0
|
|
#define UVD_BASE__INST0_SEG3 0
|
|
#define UVD_BASE__INST0_SEG4 0
|
|
#define UVD_BASE__INST0_SEG5 0
|
|
|
|
#define UVD_BASE__INST1_SEG0 0
|
|
#define UVD_BASE__INST1_SEG1 0x00009000
|
|
#define UVD_BASE__INST1_SEG2 0
|
|
#define UVD_BASE__INST1_SEG3 0
|
|
#define UVD_BASE__INST1_SEG4 0
|
|
#define UVD_BASE__INST1_SEG5 0
|
|
|
|
#define UVD_BASE__INST2_SEG0 0
|
|
#define UVD_BASE__INST2_SEG1 0
|
|
#define UVD_BASE__INST2_SEG2 0
|
|
#define UVD_BASE__INST2_SEG3 0
|
|
#define UVD_BASE__INST2_SEG4 0
|
|
#define UVD_BASE__INST2_SEG5 0
|
|
|
|
#define UVD_BASE__INST3_SEG0 0
|
|
#define UVD_BASE__INST3_SEG1 0
|
|
#define UVD_BASE__INST3_SEG2 0
|
|
#define UVD_BASE__INST3_SEG3 0
|
|
#define UVD_BASE__INST3_SEG4 0
|
|
#define UVD_BASE__INST3_SEG5 0
|
|
|
|
#define UVD_BASE__INST4_SEG0 0
|
|
#define UVD_BASE__INST4_SEG1 0
|
|
#define UVD_BASE__INST4_SEG2 0
|
|
#define UVD_BASE__INST4_SEG3 0
|
|
#define UVD_BASE__INST4_SEG4 0
|
|
#define UVD_BASE__INST4_SEG5 0
|
|
|
|
#define UVD_BASE__INST5_SEG0 0
|
|
#define UVD_BASE__INST5_SEG1 0
|
|
#define UVD_BASE__INST5_SEG2 0
|
|
#define UVD_BASE__INST5_SEG3 0
|
|
#define UVD_BASE__INST5_SEG4 0
|
|
#define UVD_BASE__INST5_SEG5 0
|
|
|
|
#define VCE_BASE__INST0_SEG0 0x00008800
|
|
#define VCE_BASE__INST0_SEG1 0
|
|
#define VCE_BASE__INST0_SEG2 0
|
|
#define VCE_BASE__INST0_SEG3 0
|
|
#define VCE_BASE__INST0_SEG4 0
|
|
#define VCE_BASE__INST0_SEG5 0
|
|
|
|
#define VCE_BASE__INST1_SEG0 0
|
|
#define VCE_BASE__INST1_SEG1 0
|
|
#define VCE_BASE__INST1_SEG2 0
|
|
#define VCE_BASE__INST1_SEG3 0
|
|
#define VCE_BASE__INST1_SEG4 0
|
|
#define VCE_BASE__INST1_SEG5 0
|
|
|
|
#define VCE_BASE__INST2_SEG0 0
|
|
#define VCE_BASE__INST2_SEG1 0
|
|
#define VCE_BASE__INST2_SEG2 0
|
|
#define VCE_BASE__INST2_SEG3 0
|
|
#define VCE_BASE__INST2_SEG4 0
|
|
#define VCE_BASE__INST2_SEG5 0
|
|
|
|
#define VCE_BASE__INST3_SEG0 0
|
|
#define VCE_BASE__INST3_SEG1 0
|
|
#define VCE_BASE__INST3_SEG2 0
|
|
#define VCE_BASE__INST3_SEG3 0
|
|
#define VCE_BASE__INST3_SEG4 0
|
|
#define VCE_BASE__INST3_SEG5 0
|
|
|
|
#define VCE_BASE__INST4_SEG0 0
|
|
#define VCE_BASE__INST4_SEG1 0
|
|
#define VCE_BASE__INST4_SEG2 0
|
|
#define VCE_BASE__INST4_SEG3 0
|
|
#define VCE_BASE__INST4_SEG4 0
|
|
#define VCE_BASE__INST4_SEG5 0
|
|
|
|
#define VCE_BASE__INST5_SEG0 0
|
|
#define VCE_BASE__INST5_SEG1 0
|
|
#define VCE_BASE__INST5_SEG2 0
|
|
#define VCE_BASE__INST5_SEG3 0
|
|
#define VCE_BASE__INST5_SEG4 0
|
|
#define VCE_BASE__INST5_SEG5 0
|
|
|
|
#define XDMA_BASE__INST0_SEG0 0x00003400
|
|
#define XDMA_BASE__INST0_SEG1 0
|
|
#define XDMA_BASE__INST0_SEG2 0
|
|
#define XDMA_BASE__INST0_SEG3 0
|
|
#define XDMA_BASE__INST0_SEG4 0
|
|
#define XDMA_BASE__INST0_SEG5 0
|
|
|
|
#define XDMA_BASE__INST1_SEG0 0
|
|
#define XDMA_BASE__INST1_SEG1 0
|
|
#define XDMA_BASE__INST1_SEG2 0
|
|
#define XDMA_BASE__INST1_SEG3 0
|
|
#define XDMA_BASE__INST1_SEG4 0
|
|
#define XDMA_BASE__INST1_SEG5 0
|
|
|
|
#define XDMA_BASE__INST2_SEG0 0
|
|
#define XDMA_BASE__INST2_SEG1 0
|
|
#define XDMA_BASE__INST2_SEG2 0
|
|
#define XDMA_BASE__INST2_SEG3 0
|
|
#define XDMA_BASE__INST2_SEG4 0
|
|
#define XDMA_BASE__INST2_SEG5 0
|
|
|
|
#define XDMA_BASE__INST3_SEG0 0
|
|
#define XDMA_BASE__INST3_SEG1 0
|
|
#define XDMA_BASE__INST3_SEG2 0
|
|
#define XDMA_BASE__INST3_SEG3 0
|
|
#define XDMA_BASE__INST3_SEG4 0
|
|
#define XDMA_BASE__INST3_SEG5 0
|
|
|
|
#define XDMA_BASE__INST4_SEG0 0
|
|
#define XDMA_BASE__INST4_SEG1 0
|
|
#define XDMA_BASE__INST4_SEG2 0
|
|
#define XDMA_BASE__INST4_SEG3 0
|
|
#define XDMA_BASE__INST4_SEG4 0
|
|
#define XDMA_BASE__INST4_SEG5 0
|
|
|
|
#define XDMA_BASE__INST5_SEG0 0
|
|
#define XDMA_BASE__INST5_SEG1 0
|
|
#define XDMA_BASE__INST5_SEG2 0
|
|
#define XDMA_BASE__INST5_SEG3 0
|
|
#define XDMA_BASE__INST5_SEG4 0
|
|
#define XDMA_BASE__INST5_SEG5 0
|
|
|
|
#define RSMU_BASE__INST0_SEG0 0x00012000
|
|
#define RSMU_BASE__INST0_SEG1 0
|
|
#define RSMU_BASE__INST0_SEG2 0
|
|
#define RSMU_BASE__INST0_SEG3 0
|
|
#define RSMU_BASE__INST0_SEG4 0
|
|
#define RSMU_BASE__INST0_SEG5 0
|
|
|
|
#define RSMU_BASE__INST1_SEG0 0
|
|
#define RSMU_BASE__INST1_SEG1 0
|
|
#define RSMU_BASE__INST1_SEG2 0
|
|
#define RSMU_BASE__INST1_SEG3 0
|
|
#define RSMU_BASE__INST1_SEG4 0
|
|
#define RSMU_BASE__INST1_SEG5 0
|
|
|
|
#define RSMU_BASE__INST2_SEG0 0
|
|
#define RSMU_BASE__INST2_SEG1 0
|
|
#define RSMU_BASE__INST2_SEG2 0
|
|
#define RSMU_BASE__INST2_SEG3 0
|
|
#define RSMU_BASE__INST2_SEG4 0
|
|
#define RSMU_BASE__INST2_SEG5 0
|
|
|
|
#define RSMU_BASE__INST3_SEG0 0
|
|
#define RSMU_BASE__INST3_SEG1 0
|
|
#define RSMU_BASE__INST3_SEG2 0
|
|
#define RSMU_BASE__INST3_SEG3 0
|
|
#define RSMU_BASE__INST3_SEG4 0
|
|
#define RSMU_BASE__INST3_SEG5 0
|
|
|
|
#define RSMU_BASE__INST4_SEG0 0
|
|
#define RSMU_BASE__INST4_SEG1 0
|
|
#define RSMU_BASE__INST4_SEG2 0
|
|
#define RSMU_BASE__INST4_SEG3 0
|
|
#define RSMU_BASE__INST4_SEG4 0
|
|
#define RSMU_BASE__INST4_SEG5 0
|
|
|
|
#define RSMU_BASE__INST5_SEG0 0
|
|
#define RSMU_BASE__INST5_SEG1 0
|
|
#define RSMU_BASE__INST5_SEG2 0
|
|
#define RSMU_BASE__INST5_SEG3 0
|
|
#define RSMU_BASE__INST5_SEG4 0
|
|
#define RSMU_BASE__INST5_SEG5 0
|
|
|
|
#endif
|