shaoyunl
65ab296840
On GFX10, the wave size is determined by the COMPUTE_DISPATCH_INITIATOR value passed to DISPATCH_DIRECT.CS_W32_EN, default 0 value was giving 64 lane waves Change-Id: Ie8c407a24bd2825757ec481be62247b35047e5ca Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
237 lines
10 KiB
C++
237 lines
10 KiB
C++
/*
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* Copyright (C) 2014-2018 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "Dispatch.hpp"
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#include "PM4Packet.hpp"
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#include "asic_reg/gfx_7_2_d.h"
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#include "asic_reg/gfx_7_2_sh_mask.h"
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#include "KFDBaseComponentTest.hpp"
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Dispatch::Dispatch(const HsaMemoryBuffer& isaBuf, const bool eventAutoReset)
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:m_IsaBuf(isaBuf), m_IndirectBuf(PACKETTYPE_PM4, PAGE_SIZE / sizeof(unsigned int), isaBuf.Node()),
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m_DimX(1), m_DimY(1), m_DimZ(1), m_pArg1(NULL), m_pArg2(NULL), m_pEop(NULL), m_ScratchEn(false),
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m_ComputeTmpringSize(0), m_scratch_base(0ll), m_SpiPriority(0) {
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HsaEventDescriptor eventDesc;
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eventDesc.EventType = HSA_EVENTTYPE_SIGNAL;
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eventDesc.NodeId = isaBuf.Node();
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eventDesc.SyncVar.SyncVar.UserData = NULL;
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eventDesc.SyncVar.SyncVarSize = 0;
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hsaKmtCreateEvent(&eventDesc, !eventAutoReset, false, &m_pEop);
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m_FamilyId = g_baseTest->GetFamilyIdFromNodeId(isaBuf.Node());
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}
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Dispatch::~Dispatch() {
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if (m_pEop != NULL)
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hsaKmtDestroyEvent(m_pEop);
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}
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void Dispatch::SetArgs(void* pArg1, void* pArg2) {
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m_pArg1 = pArg1;
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m_pArg2 = pArg2;
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}
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void Dispatch::SetDim(unsigned int x, unsigned int y, unsigned int z) {
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m_DimX = x;
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m_DimY = y;
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m_DimZ = z;
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}
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void Dispatch::SetScratch(int numWaves, int waveSize, HSAuint64 scratch_base) {
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m_ComputeTmpringSize = ((waveSize << 12) | (numWaves));
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m_ScratchEn = true;
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m_scratch_base = scratch_base;
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}
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void Dispatch::SetSpiPriority(unsigned int priority) {
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m_SpiPriority = priority;
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}
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void Dispatch::Submit(BaseQueue& queue) {
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ASSERT_NE(m_pEop, (void*)0);
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EXPECT_EQ(m_FamilyId, queue.GetFamilyId());
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BuildIb();
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queue.PlaceAndSubmitPacket(PM4IndirectBufPacket(&m_IndirectBuf));
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// Write data to SyncVar for synchronization purpose
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if (m_pEop->EventData.EventData.SyncVar.SyncVar.UserData != NULL) {
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queue.PlaceAndSubmitPacket(PM4WriteDataPacket((unsigned int*)m_pEop->
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EventData.EventData.SyncVar.SyncVar.UserData, m_pEop->EventId));
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}
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queue.PlaceAndSubmitPacket(PM4ReleaseMemoryPacket(m_FamilyId, false, m_pEop->EventData.HWData2, m_pEop->EventId));
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if (!queue.GetSkipWaitConsump())
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queue.Wait4PacketConsumption();
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}
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void Dispatch::Sync(unsigned int timeout) {
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ASSERT_SUCCESS(hsaKmtWaitOnEvent(m_pEop, timeout));
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}
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// Returning with status in order to allow actions to be performed before process termination
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int Dispatch::SyncWithStatus(unsigned int timeout) {
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int stat;
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return ((stat = hsaKmtWaitOnEvent(m_pEop, timeout)) != HSAKMT_STATUS_SUCCESS);
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}
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void Dispatch::BuildIb() {
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HSAuint64 shiftedIsaAddr = m_IsaBuf.As<uint64_t>() >> 8;
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unsigned int arg0, arg1, arg2, arg3;
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SplitU64(reinterpret_cast<uint64_t>(m_pArg1), arg0, arg1);
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SplitU64(reinterpret_cast<uint64_t>(m_pArg2), arg2, arg3);
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// Starts at COMPUTE_START_X
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const unsigned int COMPUTE_DISPATCH_DIMS_VALUES[] = {
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0, // START_X
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0, // START_Y
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0, // START_Z
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1, // NUM_THREADS_X - this is actually the number of threads in a thread group
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1, // NUM_THREADS_Y
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1, // NUM_THREADS_Z
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0, // COMPUTE_PIPELINESTAT_ENABLE
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0, // COMPUTE_PERFCOUNT_ENABLE
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};
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unsigned int pgmRsrc2 = 0;
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pgmRsrc2 |= (m_ScratchEn << COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT)
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& COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK;
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pgmRsrc2 |= ((m_scratch_base ? 6 : 4) << COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT)
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& COMPUTE_PGM_RSRC2__USER_SGPR_MASK;
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pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT)
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& COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK;
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pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT)
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& COMPUTE_PGM_RSRC2__TGID_X_EN_MASK;
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pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT)
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& COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK;
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pgmRsrc2 |= (0 << COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT)
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& COMPUTE_PGM_RSRC2__EXCP_EN_MASK;
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pgmRsrc2 |= (1 << COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT)
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& COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK;
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const unsigned int COMPUTE_PGM_RSRC[] = {
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// PGM_RSRC1 = { VGPRS: 16 SGPRS: 16 PRIORITY: m_SpiPriority FLOAT_MODE: c0 PRIV: 0
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// DX10_CLAMP: 0 DEBUG_MODE: 0 IEEE_MODE: 0 BULKY: 0 CDBG_USER: 0 }
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0x000c0084 | ((m_SpiPriority & 3) << 10),
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pgmRsrc2
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};
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// Starts at COMPUTE_PGM_LO
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const unsigned int COMPUTE_PGM_VALUES_GFX8[] = {
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static_cast<uint32_t>(shiftedIsaAddr), // PGM_LO
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static_cast<uint32_t>(shiftedIsaAddr >> 32) // PGM_HI
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| (is_dgpu() ? 0 : (1<<8)) // including PGM_ATC=?
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};
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// Starts at COMPUTE_PGM_LO
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const unsigned int COMPUTE_PGM_VALUES_GFX9[] = {
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static_cast<uint32_t>(shiftedIsaAddr), // PGM_LO
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static_cast<uint32_t>(shiftedIsaAddr >> 32) // PGM_HI
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| (is_dgpu() ? 0 : (1<<8)), // including PGM_ATC=?
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0,
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0,
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static_cast<uint32_t>(m_scratch_base >> 8), // compute_dispatch_scratch_base
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static_cast<uint32_t>(m_scratch_base >> 40)
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};
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// Starts at COMPUTE_RESOURCE_LIMITS
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const unsigned int COMPUTE_RESOURCE_LIMITS[] = {
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0, // COMPUTE_RESOURCE_LIMITS
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};
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// Starts at COMPUTE_TMPRING_SIZE
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const unsigned int COMPUTE_TMPRING_SIZE[] = {
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m_ComputeTmpringSize, // COMPUTE_TMPRING_SIZE
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};
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// Starts at COMPUTE_RESTART_X
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const unsigned int COMPUTE_RESTART_VALUES[] = {
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0, // COMPUTE_RESTART_X
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0, // COMPUTE_RESTART_Y
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0, // COMPUTE_RESTART_Z
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0 // COMPUTE_THREAD_TRACE_ENABLE
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};
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// Starts at COMPUTE_USER_DATA_0
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const unsigned int COMPUTE_USER_DATA_VALUES[] = {
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// Reg name - use in KFDtest - use in ABI
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arg0, // COMPUTE_USER_DATA_0 - arg0 - resource descriptor for the scratch buffer - 1st dword
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arg1, // COMPUTE_USER_DATA_1 - arg1 - resource descriptor for the scratch buffer - 2nd dword
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arg2, // COMPUTE_USER_DATA_2 - arg2 - resource descriptor for the scratch buffer - 3rd dword
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arg3, // COMPUTE_USER_DATA_3 - arg3 - resource descriptor for the scratch buffer - 4th dword
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static_cast<uint32_t>(m_scratch_base), // COMPUTE_USER_DATA_4 - flat_scratch_lo
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static_cast<uint32_t>(m_scratch_base >> 32), // COMPUTE_USER_DATA_4 - flat_scratch_hi
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0, // COMPUTE_USER_DATA_6 - - AQL queue address, low part
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0, // COMPUTE_USER_DATA_7 - - AQL queue address, high part
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0, // COMPUTE_USER_DATA_8 - - kernel arguments block, low part
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0, // COMPUTE_USER_DATA_9 - - kernel arguments block, high part
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0, // COMPUTE_USER_DATA_10 - - unused
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0, // COMPUTE_USER_DATA_11 - - unused
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0, // COMPUTE_USER_DATA_12 - - unused
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0, // COMPUTE_USER_DATA_13 - - unused
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0, // COMPUTE_USER_DATA_14 - - unused
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0, // COMPUTE_USER_DATA_15 - - unused
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};
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const unsigned int DISPATCH_INIT_VALUE = 0x00000021 | (is_dgpu() ? 0 : 0x1000) |
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((m_FamilyId >= FAMILY_NV) ? 0x8000 : 0);
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// {COMPUTE_SHADER_EN=1, PARTIAL_TG_EN=0, FORCE_START_AT_000=0, ORDERED_APPEND_ENBL=0,
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// ORDERED_APPEND_MODE=0, USE_THREAD_DIMENSIONS=1, ORDER_MODE=0, DISPATCH_CACHE_CNTL=0,
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// SCALAR_L1_INV_VOL=0, VECTOR_L1_INV_VOL=0, DATA_ATC=?, RESTORE=0}
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// Set CS_W32_EN for wave32 workloads for gfx10 since all the shaders used in KFDTest is 32 bit .
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m_IndirectBuf.AddPacket(PM4AcquireMemoryPacket(m_FamilyId));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_START_X, COMPUTE_DISPATCH_DIMS_VALUES,
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ARRAY_SIZE(COMPUTE_DISPATCH_DIMS_VALUES)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_PGM_LO,
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(m_FamilyId >= FAMILY_AI) ? COMPUTE_PGM_VALUES_GFX9 : COMPUTE_PGM_VALUES_GFX8,
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(m_FamilyId >= FAMILY_AI) ? ARRAY_SIZE(COMPUTE_PGM_VALUES_GFX9) : ARRAY_SIZE(COMPUTE_PGM_VALUES_GFX8)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_PGM_RSRC1, COMPUTE_PGM_RSRC,
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ARRAY_SIZE(COMPUTE_PGM_RSRC)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_RESOURCE_LIMITS, COMPUTE_RESOURCE_LIMITS,
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ARRAY_SIZE(COMPUTE_RESOURCE_LIMITS)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_TMPRING_SIZE, COMPUTE_TMPRING_SIZE,
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ARRAY_SIZE(COMPUTE_TMPRING_SIZE)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_RESTART_X, COMPUTE_RESTART_VALUES,
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ARRAY_SIZE(COMPUTE_RESTART_VALUES)));
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m_IndirectBuf.AddPacket(PM4SetShaderRegPacket(mmCOMPUTE_USER_DATA_0, COMPUTE_USER_DATA_VALUES,
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ARRAY_SIZE(COMPUTE_USER_DATA_VALUES)));
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m_IndirectBuf.AddPacket(PM4DispatchDirectPacket(m_DimX, m_DimY, m_DimZ, DISPATCH_INIT_VALUE));
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m_IndirectBuf.AddPacket(PM4PartialFlushPacket());
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m_IndirectBuf.AddPacket(PM4AcquireMemoryPacket(m_FamilyId));
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}
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