foreman
2738b30287
ECR #304775 - Add batching to the device enqueue for possible asynchronous execution - Increase the max device queue size to 512KB. That will allow to pass conformance tests that enqueue more jobs than the queue size. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#459 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusched.hpp#13 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuschedcl.cpp#28 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpuvirtual.cpp#333 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.cpp#65 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLContext.h#39 edit
531 строка
24 KiB
C++
531 строка
24 KiB
C++
//
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// Copyright (c) 2010 Advanced Micro Devices, Inc. All rights reserved.
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//
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namespace gpu {
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#define SCHEDULER_KERNEL(...) #__VA_ARGS__
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const char* SchedulerSourceCode = SCHEDULER_KERNEL(
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\n
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//! AmdAqlWrap slot state
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enum AqlWrapState {
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AQL_WRAP_FREE = 0,
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AQL_WRAP_RESERVED,
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AQL_WRAP_READY,
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AQL_WRAP_MARKER,
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AQL_WRAP_BUSY,
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AQL_WRAP_DONE
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};
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//! Profiling states
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enum ProfilingState {
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PROFILING_COMMAND_START = 0,
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PROFILING_COMMAND_END,
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PROFILING_COMMAND_COMPLETE
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};
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typedef struct _HsaAqlDispatchPacket {
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uint mix;
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ushort workgroup_size[3];
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ushort reserved2;
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uint grid_size[3];
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uint private_segment_size_bytes;
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uint group_segment_size_bytes;
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ulong kernel_object_address;
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ulong kernel_arg_address;
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ulong reserved3;
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ulong completion_signal;
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} HsaAqlDispatchPacket;
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typedef struct _AmdVQueueHeader {
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uint aql_slot_num; //!< [LRO/SRO] The total number of the AQL slots (multiple of 64).
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uint event_slot_num; //!< [LRO] The number of kernel events in the events buffer
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ulong event_slot_mask; //!< [LRO] A pointer to the allocation bitmask array for the events
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ulong event_slots; //!< [LRO] Pointer to a buffer for the events.
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// Array of event_slot_num entries of AmdEvent
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ulong aql_slot_mask; //!< [LRO/SRO]A pointer to the allocation bitmask for aql_warp slots
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uint command_counter; //!< [LRW] The global counter for the submitted commands into the queue
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uint wait_size; //!< [LRO] The wait list size (in clk_event_t)
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uint arg_size; //!< [LRO] The size of argument buffer (in bytes)
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uint reserved0; //!< For the future usage
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ulong kernel_table; //!< [LRO] Pointer to an array with all kernel objects (ulong for each entry)
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uint reserved[2]; //!< For the future usage
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} AmdVQueueHeader;
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typedef struct _AmdAqlWrap {
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uint state; //!< [LRW/SRW] The current state of the AQL wrapper: FREE, RESERVED, READY,
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// MARKER, BUSY and DONE. The block could be returned back to a free state.
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uint enqueue_flags; //!< [LWO/SRO] Contains the flags for the kernel execution start –
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// (kernel_enqueue_flags_t)
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// CLK_ENQUEUE_FLAGS_NO_WAIT – we just start processing
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// CLK_ENQUEUE_FLAGS_WAIT_KERNEL – check if parent_wrap->state is done and then start processing
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// CLK_ENQUEUE_FLAGS_WAIT_WORK_GROUP - currently == WAIT_KERNEL
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uint command_id; //!< [LWO/SRO] The unique command ID
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uint child_counter; //!< [LRW/SRW] Counter that determine the launches of child kernels.
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// It’s incremented on the
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// start and decremented on the finish. The parent kernel can be considered as
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// done when the value is 0 and the state is DONE
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ulong completion; //!< [LWO/SRO] CL event for the current execution (clk_event_t)
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ulong parent_wrap; //!< [LWO/SRO] Pointer to the parent AQL wrapper (AmdAqlWrap*)
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ulong wait_list; //!< [LRO/SRO] Pointer to an array of clk_event_t objects (64 bytes default)
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uint wait_num; //!< [LWO/SRO] The number of cl_event_wait objects
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uint reserved[5]; //!< For the future usage
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HsaAqlDispatchPacket aql; //!< [LWO/SRO] AQL packet – 64 bytes AQL packet
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} AmdAqlWrap;
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typedef struct _AmdEvent {
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uint state; //!< [LRO/SRW] Event state: START, END, COMPLETE
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uint counter; //!< [LRW] Event retain/release counter. 0 means the event is free
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ulong timer[3]; //!< [LRO/SWO] Timer values for profiling for each state
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ulong capture_info; //!< [LRW/SRO] Profiling capture info for CLK_PROFILING_COMMAND_EXEC_TIME
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} AmdEvent;
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typedef struct _SchedulerParam {
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uint signal; //!< Signal to stop the child queue
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uint eng_clk; //!< Engine clock in Mhz
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ulong hw_queue; //!< Address to HW queue
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ulong hsa_queue; //!< Address to HSA dummy queue
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uint reserved; //!< reserved
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uint scratchSize; //!< Scratch buffer size
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ulong scratch; //!< GPU address to the scratch buffer
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uint numMaxWaves; //!< Num max waves on the asic
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uint releaseHostCP; //!< Releases CP on the host queue
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ulong parentAQL; //!< Host parent AmdAqlWrap packet
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uint dedicatedQueue; //!< Scheduler uses a dedicated queue
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uint scratchOffset; //!< Scratch buffer offset
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} SchedulerParam;
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typedef struct _HwDispatchHeader {
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uint pad00;
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uint pad01;
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uint pad02;
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uint pad03;
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uint pad04;
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uint pad05;
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uint pad06;
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uint pad07;
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uint rewind; // REWIND execution
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uint startExe; // valid bit
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uint condExe0; // 0xC0032200 -- TYPE 3, COND_EXEC
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uint condExe1; // 0x00000204 ----
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uint condExe2; // 0x00000000 ----
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uint condExe3; // 0x00000000 ----
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uint condExe4; // 0x00000000 ----
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} HwDispatchHeader;
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typedef struct _HwDispatch {
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uint packet0; // 0xC0067602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (6 values)
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uint offset0; // 0x00000204 ---- OFFSET
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uint startX; // 0x00000000 ---- COMPUTE_START_X: START = 0x0
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uint startY; // 0x00000000 ---- COMPUTE_START_Y: START = 0x0
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uint startZ; // 0x00000000 ---- COMPUTE_START_Z: START = 0x0
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uint wrkGrpSizeX; // 0x00000000 ---- COMPUTE_NUM_THREAD_X: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint wrkGrpSizeY; // 0x00000000 ---- COMPUTE_NUM_THREAD_Y: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint wrkGrpSizeZ; // 0x00000000 ---- COMPUTE_NUM_THREAD_Z: NUM_THREAD_FULL = 0x0, NUM_THREAD_PARTIAL = 0x0
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uint packet1; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offset1; // 0x0000020C ---- OFFSET
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uint isaLo; // 0x00000000 ---- COMPUTE_PGM_LO: DATA = 0x0
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uint isaHi; // 0x00000000 ---- COMPUTE_PGM_HI: DATA = 0x0, INST_ATC__CI__VI = 0x0
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uint packet2; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offset2; // 0x00000212 ---- OFFSET
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uint resource1; // 0x00000000 ---- COMPUTE_PGM_RSRC1: VGPRS = 0x0, SGPRS = 0x0, PRIORITY = 0x0, FLOAT_MODE = 0x0, PRIV = 0x0, DX10_CLAMP = 0x0, DEBUG_MODE = 0x0, IEEE_MODE = 0x0, BULKY__CI__VI = 0x0, CDBG_USER__CI__VI = 0x0
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uint resource2; // 0x00000000 ---- COMPUTE_PGM_RSRC2: SCRATCH_EN = 0x0, USER_SGPR = 0x0, TRAP_PRESENT = 0x0, TGID_X_EN = 0x0, TGID_Y_EN = 0x0, TGID_Z_EN = 0x0, TG_SIZE_EN = 0x0, TIDIG_COMP_CNT = 0x0, EXCP_EN_MSB__CI__VI = 0x0, LDS_SIZE = 0x0, EXCP_EN = 0x0
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uint packet3; // 0xC0067602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (6 values)
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uint offset3; // 0x00000215 ---- OFFSET
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uint pad31; // 0x00000000 ---- COMPUTE_RESOURCE_LIMITS: WAVES_PER_SH = 0x0, TG_PER_CU = 0x0, LOCK_THRESHOLD = 0x0, SIMD_DEST_CNTL = 0x0, FORCE_SIMD_DIST__CI__VI = 0x0, CU_GROUP_COUNT__CI__VI = 0x0
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uint pad32; // 0xFFFFFFFF ---- COMPUTE_STATIC_THREAD_MGMT_SE0: SH0_CU_EN = 0xFFFF, SH1_CU_EN = 0xFFFF
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uint pad33; // 0xFFFFFFFF ---- COMPUTE_STATIC_THREAD_MGMT_SE1: SH0_CU_EN = 0xFFFF, SH1_CU_EN = 0xFFFF
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uint ringSize; // 0x00000000 ---- COMPUTE_TMPRING_SIZE: WAVES = 0x0, WAVESIZE = 0x0
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uint pad34; // 0xFFFFFFFF ---- COMPUTE_STATIC_THREAD_MGMT_SE2__CI__VI: SH0_CU_EN = 0xFFFF, SH1_CU_EN = 0xFFFF
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uint pad35; // 0xFFFFFFFF ---- COMPUTE_STATIC_THREAD_MGMT_SE3__CI__VI: SH0_CU_EN = 0xFFFF, SH1_CU_EN = 0xFFFF
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uint user0; // 0xC0047602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (4 values)
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uint offsUser0; // 0x00000240 ---- OFFSET
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uint scratchLo; // 0x00000000 ---- COMPUTE_USER_DATA_0: DATA = 0x0
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uint scratchHi; // 0x80000000 ---- COMPUTE_USER_DATA_1: DATA = 0x80000000
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uint scratchSize; // 0x00000000 ---- COMPUTE_USER_DATA_2: DATA = 0x0
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uint padUser; // 0x00EA7FAC ---- COMPUTE_USER_DATA_3: DATA = 0xEA7FAC
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uint user1; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser1; // 0x00000244 ---- OFFSET
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uint aqlPtrLo; // 0x00000000 ---- COMPUTE_USER_DATA_4: DATA = 0x0
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uint aqlPtrHi; // 0x00000000 ---- COMPUTE_USER_DATA_5: DATA = 0x0
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uint user2; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser2; // 0x00000246 ---- OFFSET
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uint hsaQueueLo; // 0x00000000 ---- COMPUTE_USER_DATA_6: DATA = 0x0
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uint hsaQueueHi; // 0x00000000 ---- COMPUTE_USER_DATA_7: DATA = 0x0
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uint user3; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser3; // 0x00000246 ---- OFFSET
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uint argsLo; // 0x00000000 ---- COMPUTE_USER_DATA_8: DATA = 0x0
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uint argsHi; // 0x00000000 ---- COMPUTE_USER_DATA_9: DATA = 0x0
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uint copyData; // 0xC0044000 -- TYPE 3, COPY_DATA
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uint copyDataFlags; // 0x00000405 ---- srcSel 0x5, destSel 0x4, countSel 0x0, wrConfirm 0x0, engineSel 0x0
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uint scratchAddrLo; // 0x000201C4 ---- srcAddressLo
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uint scratchAddrHi; // 0x00000000 ---- srcAddressHi
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uint shPrivateLo; // 0x00002580 ---- dstAddressLo
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uint shPrivateHi; // 0x00000000 ---- dstAddressHi
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uint user4; // 0xC0027602 -- TYPE 3, SET_SH_REG, TYPE:COMPUTE (2 values)
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uint offsUser4; // 0x00000248 ---- OFFSET
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uint scratchOffs; // 0x00000000 ---- COMPUTE_USER_DATA_10: DATA = 0x0
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uint privSize; // 0x00000030 ---- COMPUTE_USER_DATA_11: DATA = 0x30
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uint packet4; // 0xC0031502 -- TYPE 3, DISPATCH_DIRECT, TYPE:COMPUTE
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uint glbSizeX; // 0x00000000
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uint glbSizeY; // 0x00000000
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uint glbSizeZ; // 0x00000000
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uint padd41; // 0x00000021
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} HwDispatch;
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const uint ResumeExecution = 0x80000000; // 0x81000000
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const uint StallExecution = 0x00000000; // 0x01000000
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const uint WavefrontSize = 64;
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const uint MaxWaveSize = 0x400;
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static inline void
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dispatch(
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volatile __global HwDispatch* dispatch,
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__global HsaAqlDispatchPacket* aqlPkt,
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ulong scratch,
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ulong hsaQueue,
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uint scratchSize,
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uint scratchOffset,
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uint numMaxWaves)
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{
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const uint UsrRegOffset = 0x240;
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const uint Pm4Nop = 0xC0001002;
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const uint Pm4UserRegs = 0xC0007602;
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const uint Pm4CopyReg = 0xC0044000;
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uint usrRegCnt = 0;
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dispatch->wrkGrpSizeX = aqlPkt->workgroup_size[0];
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dispatch->wrkGrpSizeY = aqlPkt->workgroup_size[1];
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dispatch->wrkGrpSizeZ = aqlPkt->workgroup_size[2];
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// ISA address
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__global uchar* kernelObj = (__global uchar*)aqlPkt->kernel_object_address;
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ulong isa = aqlPkt->kernel_object_address + *((__global uint*)(kernelObj + 0x10));
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dispatch->isaLo = (uint)(isa >> 8);
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dispatch->isaHi = (uint)(isa >> 40);
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// Program PGM resource registers
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dispatch->resource1 = *((__global uint*)(kernelObj + 0x30));
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dispatch->resource2 = *((__global uint*)(kernelObj + 0x34));
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uint flags = *((__global uint*)(kernelObj + 0x38));
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uint privateSize = *((__global uint*)(kernelObj + 0x50));
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uint ldsSize = aqlPkt->group_segment_size_bytes +
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*((__global uint*)(kernelObj + 0x54));
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// Align up the LDS blocks 128 * 4(in DWORDs)
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uint ldsBlocks = (ldsSize + 511) >> 9;
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dispatch->resource2 |= (ldsBlocks << 15);
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// Workaround for compiler bug
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dispatch->scratchLo = (flags & 1);
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// privSegEna = (flags & 1);
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if (flags & 0x1) {
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uint waveSize = privateSize * WavefrontSize;
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// 256 DWRODs is the minimum for SQ
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waveSize = max(MaxWaveSize, waveSize);
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uint numWaves = scratchSize / waveSize;
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numWaves = min(numWaves, numMaxWaves);
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dispatch->ringSize = numWaves;
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dispatch->ringSize |= (waveSize >> 10) << 12;
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dispatch->user0 = Pm4UserRegs | (4 << 16);
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dispatch->scratchLo = (uint)scratch;
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dispatch->scratchHi = ((uint)(scratch >> 32)) | 0x80000000; // Enables swizzle
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dispatch->scratchSize = scratchSize;
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usrRegCnt += 4;
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}
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else {
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dispatch->ringSize = 0;
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dispatch->user0 = Pm4Nop | (4 << 16);
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}
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// dispatchEna = (flags & 0x2);
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dispatch->user1 = (flags & 0x2) ? (Pm4UserRegs | (2 << 16)) : (Pm4Nop | (2 << 16));
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dispatch->offsUser1 = UsrRegOffset + usrRegCnt;
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usrRegCnt += (flags & 0x2) ? 2 : 0;
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ulong gpuAqlPtr = (ulong)aqlPkt;
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dispatch->aqlPtrLo = (uint)gpuAqlPtr;
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dispatch->aqlPtrHi = (uint)(gpuAqlPtr >> 32);
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// queuePtr = (flags & 0x4);
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if (flags & 0x4) {
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dispatch->user2 = Pm4UserRegs | (2 << 16);
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dispatch->offsUser2 = UsrRegOffset + usrRegCnt;
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usrRegCnt += 2;
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dispatch->hsaQueueLo = (uint)hsaQueue;
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dispatch->hsaQueueHi = (uint)(hsaQueue >> 32);
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}
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else {
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dispatch->user2 = Pm4Nop | (2 << 16);
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}
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// kernelArgEna = (flags & 0x8);
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dispatch->user3 = (flags & 0x8) ? (Pm4UserRegs | (2 << 16)) : (Pm4Nop | (2 << 16));
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dispatch->offsUser3 = UsrRegOffset + usrRegCnt;
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usrRegCnt += (flags & 0x8) ? 2 : 0;
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dispatch->argsLo = (uint)aqlPkt->kernel_arg_address;
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dispatch->argsHi = (uint)(aqlPkt->kernel_arg_address >> 32);
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// flatScratchEna = (flags & 0x20);
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if (flags & 0x20) {
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dispatch->copyData = Pm4CopyReg;
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dispatch->scratchAddrLo = (uint)((scratch - scratchOffset) >> 16);
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dispatch->offsUser4 = UsrRegOffset + usrRegCnt;
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dispatch->scratchOffs = scratchOffset;
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dispatch->privSize = privateSize;
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}
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else {
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dispatch->copyData = Pm4Nop | (8 << 16);
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}
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dispatch->glbSizeX = aqlPkt->grid_size[0];
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dispatch->glbSizeY = aqlPkt->grid_size[1];
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dispatch->glbSizeZ = aqlPkt->grid_size[2];
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}
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static inline bool
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checkWaitEvents(__global AmdEvent** events, uint numEvents)
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{
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for (uint i = 0; i < numEvents; ++i) {
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if (atomic_load_explicit(
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(__global atomic_uint*)(&events[i]->state),
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memory_order_acquire, memory_scope_device) != CL_COMPLETE) {
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return false;
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}
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}
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return true;
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}
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// release slot in a bitmask controlled resource i is the slot number
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static inline void
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release_slot(__global uint* restrict mask, uint i)
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{
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/* uint b = ~(1UL << (i & 0x1f)); */
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uint b = ~amd_bfm(1U, i);
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__global atomic_uint *p = (__global atomic_uint *)(mask + (i >> 5));
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uint vv;
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uint v = atomic_load_explicit(p, memory_order_acquire, memory_scope_device);
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for (;;) {
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vv = v & b;
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if (atomic_compare_exchange_strong_explicit(p, &v, vv,
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memory_order_acq_rel, memory_order_acquire, memory_scope_device)) {
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break;
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}
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}
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}
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static inline void
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releaseEvent(__global AmdEvent* ev, __global uint* emask, __global AmdEvent* eb)
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{
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uint c = atomic_fetch_sub_explicit((__global atomic_uint *)&ev->counter, 1U,
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memory_order_acq_rel, memory_scope_device);
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if (c == 1U) {
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uint i = ev - eb;
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release_slot(emask, i);
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}
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}
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static inline void
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releaseWaitEvents(__global AmdEvent** events, uint numEvents,
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__global uint* emask, __global AmdEvent* eb)
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{
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for (uint i = 0; i < numEvents; ++i) {
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releaseEvent(events[i], emask, eb);
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}
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}
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static inline uint
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min_command(uint slot_num, __global AmdAqlWrap* wraps)
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{
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uint minCommand = 0xffffffff;
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for (uint idx = 0; idx < slot_num; ++idx) {
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__global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx];
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uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state),
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memory_order_acquire, memory_scope_device);
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if ((slotState != AQL_WRAP_FREE) && (slotState != AQL_WRAP_RESERVED)) {
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minCommand = min(disp->command_id, minCommand);
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}
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}
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return minCommand;
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}
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extern ulong __hsail_get_clock(); // Declaration is required
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__kernel void
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scheduler(
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__global AmdVQueueHeader* queue,
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__global SchedulerParam* params,
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uint paramIdx)
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{
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__global SchedulerParam* param = ¶ms[paramIdx];
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volatile __global HwDispatch* hwDisp = (volatile __global HwDispatch*)
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&((__global HwDispatchHeader*)param->hw_queue)[1];
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__global AmdAqlWrap* hostParent = (__global AmdAqlWrap*)(param->parentAQL);
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__global uint* counter = (__global uint*)(&hostParent->child_counter);
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__global uint* signal = (__global uint*)(¶m->signal);
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__global AmdAqlWrap* wraps = (__global AmdAqlWrap*)&queue[1];
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__global uint* amask = (__global uint *)queue->aql_slot_mask;
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|
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//! @todo This is an unexplained behavior.
|
||
//! The scheduler can be launched one more time after termination.
|
||
if (1 == atomic_load_explicit((__global atomic_uint*)¶m->releaseHostCP,
|
||
memory_order_acquire, memory_scope_device)) {
|
||
return;
|
||
}
|
||
|
||
uint launch = 0;
|
||
uint loop = 1;
|
||
|
||
uint mask = atomic_load_explicit((__global atomic_uint*)(&amask[get_group_id(0)]),
|
||
memory_order_acquire, memory_scope_device);
|
||
|
||
int baseIdx = get_group_id(0) * 32;
|
||
while (mask != 0) {
|
||
uint sIdx = ctz(mask);
|
||
uint idx = baseIdx + sIdx;
|
||
mask &= ~(1 << sIdx);
|
||
__global AmdAqlWrap* disp = (__global AmdAqlWrap*)&wraps[idx];
|
||
uint slotState = atomic_load_explicit((__global atomic_uint*)(&disp->state),
|
||
memory_order_acquire, memory_scope_device);
|
||
__global AmdAqlWrap* parent = (__global AmdAqlWrap*)(disp->parent_wrap);
|
||
__global AmdEvent* event = (__global AmdEvent*)(disp->completion);
|
||
|
||
// Check if the current slot is ready for processing
|
||
if (slotState == AQL_WRAP_READY) {
|
||
if (launch == 0) {
|
||
// Attempt to find a new disaptch if nothing was launched yet
|
||
uint parentState = atomic_load_explicit(
|
||
(__global atomic_uint*)(&parent->state),
|
||
memory_order_acquire, memory_scope_device);
|
||
uint enqueueFlags = atomic_load_explicit(
|
||
(__global atomic_uint*)(&disp->enqueue_flags),
|
||
memory_order_acquire, memory_scope_device);
|
||
|
||
// Check the launch flags
|
||
if (((enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_KERNEL) ||
|
||
(enqueueFlags == CLK_ENQUEUE_FLAGS_WAIT_WORK_GROUP)) &&
|
||
(parentState != AQL_WRAP_DONE)) {
|
||
continue;
|
||
}
|
||
|
||
// Check if the wait list is COMPLETE
|
||
launch = checkWaitEvents(
|
||
(__global AmdEvent**)(disp->wait_list), disp->wait_num);
|
||
|
||
if (launch) {
|
||
if (event != 0) {
|
||
event->timer[PROFILING_COMMAND_START] =
|
||
(__hsail_get_clock() * (ulong)param->eng_clk) >> 10;
|
||
}
|
||
// Launch child kernel ....
|
||
dispatch(&hwDisp[get_group_id(0)], &disp->aql, param->scratch, param->hsa_queue,
|
||
param->scratchSize, param->scratchOffset, param->numMaxWaves);
|
||
disp->state = AQL_WRAP_BUSY;
|
||
releaseWaitEvents((__global AmdEvent**)(disp->wait_list),
|
||
disp->wait_num, (__global uint*)queue->event_slot_mask,
|
||
(__global AmdEvent*)queue->event_slots);
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
else if (slotState == AQL_WRAP_MARKER) {
|
||
bool complete = false;
|
||
if (disp->wait_num == 0) {
|
||
uint minCommand = min_command(queue->aql_slot_num, wraps);
|
||
if (disp->command_id == minCommand) {
|
||
complete = true;
|
||
}
|
||
}
|
||
else {
|
||
// Check if the wait list is COMPLETE
|
||
if (checkWaitEvents(
|
||
(__global AmdEvent**)(disp->wait_list), disp->wait_num)) {
|
||
complete = true;
|
||
releaseWaitEvents((__global AmdEvent**)(disp->wait_list),
|
||
disp->wait_num, (__global uint*)queue->event_slot_mask,
|
||
(__global AmdEvent*)queue->event_slots);
|
||
}
|
||
}
|
||
if (complete) {
|
||
// Decrement the child execution counter on the parent
|
||
atomic_fetch_sub_explicit(
|
||
(__global atomic_uint*)&parent->child_counter,
|
||
1, memory_order_acq_rel, memory_scope_device);
|
||
event->state = CL_COMPLETE;
|
||
disp->state = AQL_WRAP_FREE;
|
||
release_slot(amask, idx);
|
||
releaseEvent(event, (__global uint*)queue->event_slot_mask,
|
||
(__global AmdEvent*)queue->event_slots);
|
||
}
|
||
}
|
||
else if ((slotState == AQL_WRAP_BUSY) ||
|
||
(slotState == AQL_WRAP_DONE)) {
|
||
if (slotState == AQL_WRAP_BUSY) {
|
||
disp->state = AQL_WRAP_DONE;
|
||
if (event != 0) {
|
||
event->timer[PROFILING_COMMAND_END] =
|
||
(__hsail_get_clock() * (ulong)param->eng_clk) >> 10;
|
||
}
|
||
}
|
||
// Was CL_EVENT requested?
|
||
if (event != 0) {
|
||
// The current dispatch doesn't have any outstanding children
|
||
if (disp->child_counter == 0) {
|
||
event->timer[PROFILING_COMMAND_COMPLETE] =
|
||
(__hsail_get_clock() * (ulong)param->eng_clk) >> 10;
|
||
event->state = CL_COMPLETE;
|
||
if (event->capture_info != 0) {
|
||
__global ulong* values = (__global ulong*)event->capture_info;
|
||
values[0] = event->timer[PROFILING_COMMAND_END] -
|
||
event->timer[PROFILING_COMMAND_START];
|
||
values[1] = event->timer[PROFILING_COMMAND_COMPLETE] -
|
||
event->timer[PROFILING_COMMAND_START];
|
||
}
|
||
releaseEvent(event, (__global uint *)queue->event_slot_mask,
|
||
(__global AmdEvent *)queue->event_slots);
|
||
}
|
||
}
|
||
// The current dispatch doesn't have any outstanding children
|
||
if (disp->child_counter == 0) {
|
||
// Decrement the child execution counter on the parent
|
||
atomic_fetch_sub_explicit(
|
||
(__global atomic_uint*)&parent->child_counter,
|
||
1, memory_order_acq_rel, memory_scope_device);
|
||
disp->state = AQL_WRAP_FREE;
|
||
release_slot(amask, idx);
|
||
}
|
||
}
|
||
}
|
||
|
||
if (launch == 0) {
|
||
hwDisp[get_group_id(0)].glbSizeX = 0;
|
||
hwDisp[get_group_id(0)].glbSizeY = 0;
|
||
hwDisp[get_group_id(0)].glbSizeZ = 0;
|
||
}
|
||
|
||
if (param->dedicatedQueue) {
|
||
loop = atomic_load_explicit((__global atomic_uint*)signal,
|
||
memory_order_acquire, memory_scope_device);
|
||
}
|
||
else {
|
||
loop = atomic_load_explicit((__global atomic_uint*)counter,
|
||
memory_order_acquire, memory_scope_device);
|
||
}
|
||
|
||
if (loop == 0) {
|
||
//! \todo Write deadcode to the template, but somehow
|
||
//! the scheduler will be launched one more time.
|
||
hwDisp->packet0 = 0xdeadc0de;
|
||
atomic_store_explicit((__global atomic_uint*)signal,
|
||
0, memory_order_release, memory_scope_device);
|
||
atomic_store_explicit((__global atomic_uint*)¶m->releaseHostCP,
|
||
1, memory_order_release, memory_scope_device);
|
||
}
|
||
}
|
||
\n
|
||
\n
|
||
);
|
||
|
||
} // namespace gpu
|