David Yat Sin 251601b20b Add RISC-V support ...

Patch provided by user Xeonacid via github:
https://github.com/RadeonOpenCompute/ROCR-Runtime/pull/172/

Change-Id: I5f9086b536383093e7995b9cfdc19dab213f0265

2023-12-04 15:05:22 +00:00

..

amd_hsa_common.h

Update copyright date.

2020-06-19 22:34:01 -04:00

amd_hsa_elf.h

Revert "Revert "Add support for GC 11.5.0 and 11.5.1""

2023-12-04 15:03:31 +00:00

amd_hsa_kernel_code.h

Update copyright date.

2020-06-19 22:34:01 -04:00

amd_hsa_queue.h

Update queue structure to support async reclaim

2023-12-04 15:05:22 +00:00

amd_hsa_signal.h

Update copyright date.

2020-06-19 22:34:01 -04:00

Brig.h

Update Brig.h file.

2016-08-18 11:35:55 -05:00

hsa_api_trace.h

Implement async scratch reclaim

2023-12-04 15:05:22 +00:00

hsa_ext_amd.h

Implement async scratch reclaim

2023-12-04 15:05:22 +00:00

hsa_ext_finalize.h

Update copyright date.

2020-06-19 22:34:01 -04:00

hsa_ext_image.h

Update copyright date.

2020-06-19 22:34:01 -04:00

hsa_ven_amd_aqlprofile.h

Extending AQLprofile API to include counter dimensions

2023-12-04 15:05:22 +00:00

hsa_ven_amd_loader.h

Update documentation of hsa_ven_amd_loader_iterate_executables

2021-04-16 20:51:48 -04:00

hsa.h

Add RISC-V support

2023-12-04 15:05:22 +00:00