gilbertlee-amd
ee262819a7
* Upgrading TransferBench to support pinned CPU memory, expanding functionality, cleaning up env vars
40 línte
2.2 KiB
INI
40 línte
2.2 KiB
INI
#Configfile Format:
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#==================
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#A Link is defined as a uni-directional transfer from src memory location to dst memory location
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#Each single line in the configuration file defines a set of Links to run in parallel
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#There are two ways to specify the configuration file:
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#1) Basic
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# The basic specification assumes the same number of threadblocks/CUs used per link
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# A positive number of Links is specified followed by that number of triplets describing each Link
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#Links #CUs (GPUIndex1 srcMem1 dstMem1) ... (GPUIndexL srcMemL dstMemL)
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#2) Advanced
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# The advanced specification allows different number of threadblocks/CUs used per Link
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# A negative number of links is specified, followed by quadruples describing each Link
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# -#Links (GPUIndex1 #CUs1 srcMem1 dstMem1) ... (GPUIndexL #CUsL srcMemL dstMemL)
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#Argument Details:
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# #Links : Number of Links to be run in parallel
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# #CUs : Number of threadblocks/CUs to use for a Link
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# GpuIndex: 0-indexed GPU id executing the Link
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# srcMemL : Source memory location (Where the data is to be read from). Ignored in memset mode
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# dstMemL : Destination memory location (Where the data is to be written to)
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# Memory locations are specified by a character indicating memory type, followed by GPU device index (0-indexed)
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# Supported memory locations are:
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# - P: Pinned host memory (on CPU, on NUMA node closest to provided GPU index)
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# - G: Global device memory (on GPU)
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#Round brackets may be included for human clarity, but will be ignored
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#Examples:
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#1 4 (0 G0 G1) Single Link that uses 4 CUs on GPU 0 that reads memory from GPU 0 and copies it to memory on GPU 1
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#1 4 (0 G1 G0) Single Link that uses 4 CUs on GPU 0 that reads memory from GPU 1 and copies it to memory on GPU 0
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#1 4 (2 P0 G2) Single Link that uses 4 CUs on GPU 2 that reads memory from CPU 0 and copies it to memory on GPU 2
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#2 4 (0 G0 G1) (1 G1 G0) Runs 2 Links in parallel. GPU 0 - > GPU1, and GP1 -> GPU 0, each with 4 CUs
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#-2 (0 G0 G1 4) (1 G1 G0 2) Runs 2 Links in parallel. GPU 0 - > GPU 1 using four CUs, and GPU1 -> GPU 0 using two CUs
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# Single link between GPUs 0 and 1
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1 1 (0 G0 G1)
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