Chris Freehill
081a2cc875
In several places aql packets were written to queue all at once instead of doing the header atomically. These cases have been fixed. There were a few hsa_signal leaked that have been addressed. There was some duplication of code that has been addressed. Addresses ROCMOPS-456 Change-Id: Ia1869bc370f92e49ac560301df47741d5f76978e
508 lines
18 KiB
C++
Executable File
508 lines
18 KiB
C++
Executable File
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2017, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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// The purpose of this test is to provide an example of the use of the
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// common RocrTest classes and utilities that are used in many examples.
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// It can be used as a template to start off with when writing new tests.
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// In many cases, the existing boilerplate code will be sufficient as is.
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// Otherwise, the boilerplate code can be either supplemented or replaced
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// by your own code in your example, as necessary.
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//
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// The comments provided are focused more on the use of the common rocrtst
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// utilities and boilerplate code, rather than the example app. itself.
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//
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// The boilerplate code includes code for:
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// * hsa initialization and clean up
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// * code to load pre-built kernels
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// * creating queues
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// * populating AQL packets
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// * checking for required profiles
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// * finding cpu and gpu agents (callbacks for common use cases)
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// * finding pools (having common requirements)
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// * allocating and setting kernel arguments
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// * somewhat standardized output
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// * handling additional command line arguments, beyond google-test arguments
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// * support for various level of verbosity, controlled from command line arg
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// * support for building OpenCL kernels
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// * timer support
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//
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// Overview of RocrTst code organization:
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// Classes:
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// * class BaseRocR (base_rocr.h) -- base class for all rocrtst examples and
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// tests. Most of the rocrtst common utilities act on BaseRocR objects
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//
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// * TestBase (test_base.h) -- derives from BaseRocR and is the base class
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// for all tests under <rocrtst root>/suites. The implementation in TestBase
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// methods are typically actions that are required for most/all tests and
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// should therefore be called from the derived implementions of the methods.
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//
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// Utilities:
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// * <rocrtst root>/common/base_rocr_utils.<cc/h> contains a set of utilities
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// that act on BaseRocR objects.
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//
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// * <rocrtst root>/common/common.<cc/h> contain other non-BaseRocR utilities
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//
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// Special Files:
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// * main.cc -- The main google test file from which the tests are invoked.
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// There should be an entry for each test to be run there.
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//
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// * kernels -- OpenCL kernel source files should go in the kernels directory
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//
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// * CMakeLists.txt -- Host code (*.cc and *.h files) should build without
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// modifying the CMakeList.txt file, if the files are place in the
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// "performance" directory. However, an entry for OpenCL kernels. For
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// each kernel to be built, the bitcode libraries must be indicated before
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// the call to "build_kernel()" is made. See existing code for examples.
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#include <sys/mman.h>
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#include <algorithm>
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#include <iostream>
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#include <vector>
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#include <atomic>
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#include "suites/functional/ipc.h"
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#include "common/base_rocr_utils.h"
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#include "common/common.h"
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#include "common/helper_funcs.h"
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#include "common/hsatimer.h"
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#include "gtest/gtest.h"
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#include "hsa/hsa.h"
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#include "hsa/hsa_ext_finalize.h"
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static const uint32_t kNumBufferElements = 256;
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struct callback_args {
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hsa_agent_t host;
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hsa_agent_t device;
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hsa_amd_memory_pool_t cpu_pool;
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hsa_amd_memory_pool_t gpu_pool;
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size_t gpu_mem_granule;
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};
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// Wrap printf to add first or second process indicator
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#define PROCESS_LOG(format, ...) { \
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if (verbosity() >= VERBOSE_STANDARD || !processOne_) { \
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fprintf(stdout, "line:%d P%u: " format, \
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__LINE__, static_cast<int>(!processOne_), ##__VA_ARGS__); \
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} \
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}
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// Fork safe ASSERT_EQ.
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#define MSG(y, msg, ...) msg
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#define Y(y, ...) y
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#define FORK_ASSERT_EQ(x, ...) \
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if ((x) != (Y(__VA_ARGS__))) { \
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EXPECT_EQ(x, Y(__VA_ARGS__)) << MSG(__VA_ARGS__, ""); \
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if (!processOne_) exit(0); \
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return; \
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}
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IPCTest::IPCTest(void) :
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TestBase() {
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set_num_iteration(10); // Number of iterations to execute of the main test;
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// This is a default value which can be overridden
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// on the command line.
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set_title("IPC Test");
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set_description("IPCTest verifies that the IPC feature of RocR is "
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"functioning as expected. The test first forks off second process. The "
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"2 processes share pointers to RocR allocated memory and also share "
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"signal handles");
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}
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IPCTest::~IPCTest(void) {
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}
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// See if the other process wrote an error value to the token; if not, write
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// the newVal to the token.
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static int CheckAndSetToken(std::atomic<int> *token, int newVal) {
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if (*token == -1) {
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return -1;
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} else {
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*token = newVal;
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}
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return 0;
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}
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// Any 1-time setup involving member variables used in the rest of the test
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// should be done here.
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void IPCTest::SetUp(void) {
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hsa_status_t err;
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int ret;
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// We must fork process before doing HSA stuff, specifically, hsa_init, as
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// each process needs to do this.
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// Allocate linux shared_ memory.
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shared_ = reinterpret_cast<Shared*>(
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mmap(nullptr, sizeof(Shared), PROT_READ | PROT_WRITE,
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MAP_SHARED | MAP_ANONYMOUS, -1, 0));
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ASSERT_NE(shared_, MAP_FAILED) << "mmap failed to allocated shared_ memory";
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// "token" is used to signal state changes between the 2 processes.
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std::atomic<int> * token = &shared_->token;
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*token = 0;
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// Spawn second process and verify communication
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child_ = 0;
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child_ = fork();
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ASSERT_NE(-1, child_) << "fork failed";
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if (child_ != 0) {
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processOne_ = true;
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// Signal to other process we are waiting, and then wait...
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*token = 1;
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while (*token == 1) {
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sched_yield();
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}
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PROCESS_LOG("Second process observed, handshake...\n");
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*token = 1;
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while (*token == 1) {
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sched_yield();
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}
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} else {
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processOne_ = false;
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set_verbosity(0);
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PROCESS_LOG("Second process running.\n");
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while (*token == 0) {
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sched_yield();
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}
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ret = CheckAndSetToken(token, 0);
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ASSERT_EQ(0, ret) << "Error detected in child process";
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// Wait for handshake
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while (*token == 0) {
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sched_yield();
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}
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ret = CheckAndSetToken(token, 0);
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ASSERT_EQ(0, ret) << "Error detected in child process";
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}
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// TestBase::SetUp() will set HSA_ENABLE_INTERRUPT if enable_interrupt() is
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// true, and call hsa_init(). It also prints the SetUp header.
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TestBase::SetUp();
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// SetDefaultAgents(this) will assign the first CPU and GPU found on
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// iterating through the agents and assign them to cpu_device_ and
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// gpu_device1_, respectively (cpu_device() and gpu_device1()). These
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// BaseRocR member variables are used in some utilities. Additionally,
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// SetDefaultAgents() checks the profile of the gpu and compares this
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// to any required profile.
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err = rocrtst::SetDefaultAgents(this);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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// Find and assign HSA_AMD_SEGMENT_GLOBAL pools for cpu, gpu and a kern_arg
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// pool
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err = rocrtst::SetPoolsTypical(this);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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return;
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}
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// Do a few extra iterations as we toss out some of the inital and final
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// iterations when calculating statistics
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uint32_t IPCTest::RealIterationNum(void) {
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return num_iteration() * 1.2 + 1;
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}
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void IPCTest::Run(void) {
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hsa_status_t err;
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std::atomic<int> *token = &shared_->token;
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TestBase::Run();
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// Print out name of the device.
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char name1[64] = {0};
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char name2[64] = {0};
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err = hsa_agent_get_info(*cpu_device(), HSA_AGENT_INFO_NAME, name1);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "hsa_agent_get_info() failed");
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err = hsa_agent_get_info(*gpu_device1(), HSA_AGENT_INFO_NAME, name2);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "hsa_agent_get_info() failed");
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uint16_t loc1, loc2;
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err = hsa_agent_get_info(*cpu_device(),
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(hsa_agent_info_t)HSA_AMD_AGENT_INFO_BDFID, &loc1);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_agent_get_info(*gpu_device1(),
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(hsa_agent_info_t)HSA_AMD_AGENT_INFO_BDFID, &loc2);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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size_t gpu_mem_granule;
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#ifdef ROCRTST_EMULATOR_BUILD
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gpu_mem_granule = 4;
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#else
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err = hsa_amd_memory_pool_get_info(device_pool(),
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HSA_AMD_MEMORY_POOL_INFO_RUNTIME_ALLOC_GRANULE, &gpu_mem_granule);
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#endif
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if (verbosity() >= VERBOSE_STANDARD) {
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fprintf(stdout, "Using: %s (%d) and %s (%d)\n", name1, loc1, name2, loc2);
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}
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hsa_agent_t ag_list[2] = {*gpu_device1(), *cpu_device()};
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auto CheckAndFillBuffer = [&](void *gpu_src_ptr, uint32_t exp_cur_val,
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uint32_t new_val) -> void {
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hsa_signal_t copy_signal;
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size_t sz = gpu_mem_granule;
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hsa_status_t err;
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hsa_signal_value_t sig;
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err = hsa_signal_create(1, 0, NULL, ©_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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uint32_t *sysBuf;
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err = hsa_amd_memory_pool_allocate(cpu_pool(), sz, 0,
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reinterpret_cast<void **>(&sysBuf));
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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hsa_agent_t ag_list[2] = {*gpu_device1(), *cpu_device()};
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err = hsa_amd_agents_allow_access(2, ag_list, NULL, sysBuf);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_amd_memory_async_copy(sysBuf, *cpu_device(), gpu_src_ptr,
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*gpu_device1(), sz, 0, NULL, copy_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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sig = hsa_signal_wait_relaxed(copy_signal, HSA_SIGNAL_CONDITION_LT,
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1, -1, HSA_WAIT_STATE_BLOCKED);
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FORK_ASSERT_EQ(0, sig, "Expected signal 0, but got " << sig);
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uint32_t count = sz/sizeof(uint32_t);
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for (uint32_t i = 0; i < count; ++i) {
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FORK_ASSERT_EQ(exp_cur_val, sysBuf[i]);
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sysBuf[i] = new_val;
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}
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hsa_signal_store_relaxed(copy_signal, 1);
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err = hsa_amd_memory_async_copy(gpu_src_ptr, *gpu_device1(), sysBuf,
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*cpu_device(), sz, 0, NULL, copy_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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sig = hsa_signal_wait_relaxed(copy_signal, HSA_SIGNAL_CONDITION_LT,
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1, -1, HSA_WAIT_STATE_BLOCKED);
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FORK_ASSERT_EQ(sig, 0, "Expected signal 0, but got " << sig);
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err = hsa_signal_destroy(copy_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_amd_memory_pool_free(sysBuf);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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};
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if (processOne_) {
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// Ignoring the first allocation to exercise fragment allocation.
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uint32_t* discard = NULL;
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err = hsa_amd_memory_pool_allocate(device_pool(), gpu_mem_granule, 0,
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reinterpret_cast<void**>(&discard));
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "Failed to allocate memory from gpu pool");
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// Allocate some VRAM and fill it with 1's
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uint32_t* gpuBuf = NULL;
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err = hsa_amd_memory_pool_allocate(device_pool(), gpu_mem_granule, 0,
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reinterpret_cast<void**>(&gpuBuf));
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "Failed to allocate memory from gpu pool");
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err = hsa_amd_memory_pool_free(discard);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "Failed to free GPU memory");
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PROCESS_LOG("Allocated local memory buffer at %p\n", gpuBuf);
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err = hsa_amd_agents_allow_access(2, ag_list, NULL, gpuBuf);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_amd_ipc_memory_create(gpuBuf, gpu_mem_granule,
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const_cast<hsa_amd_ipc_memory_t*>(&shared_->handle));
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PROCESS_LOG(
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"Created IPC handle associated with gpu-local buffer at P0 address %p\n",
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gpuBuf);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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uint32_t count = gpu_mem_granule/sizeof(uint32_t);
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shared_->size = gpu_mem_granule;
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shared_->count = count;
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err = hsa_amd_memory_fill(gpuBuf, 1, count);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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// Get IPC capable signal
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hsa_signal_t ipc_signal;
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err = hsa_amd_signal_create(1, 0, NULL, HSA_AMD_SIGNAL_IPC, &ipc_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_amd_ipc_signal_create(ipc_signal,
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const_cast<hsa_amd_ipc_signal_t*>(&shared_->signal_handle));
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PROCESS_LOG("Created IPC handle associated with ipc_signal\n");
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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// Signal Process 2 that the gpu buffer is ready to read.
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CheckAndSetToken(token, 1);
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PROCESS_LOG("Allocated buffer and filled it with 1's. Wait for P1...\n");
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hsa_signal_value_t ret =
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hsa_signal_wait_acquire(ipc_signal, HSA_SIGNAL_CONDITION_NE, 1, -1,
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HSA_WAIT_STATE_BLOCKED);
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FORK_ASSERT_EQ(2, ret, "Expected signal value of 2, but got " << ret);
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CheckAndFillBuffer(gpuBuf, 2, 0);
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PROCESS_LOG("Confirmed P1 filled buffer with 2\n")
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PROCESS_LOG("PASSED on P0\n");
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hsa_signal_store_relaxed(ipc_signal, 0);
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err = hsa_signal_destroy(ipc_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = hsa_amd_memory_pool_free(gpuBuf);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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waitpid(child_, nullptr, 0);
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munmap(shared_, sizeof(Shared));
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// Note: Close() (and hsa_shut_down()) will be called from main() in
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// RunCustomEpilog()
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} else { // "ProcessTwo"
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PROCESS_LOG("Waiting for process 0 to write 1 to token...\n");
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while (*token == 0) {
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sched_yield();
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}
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if (*token != 1) {
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*token = -1;
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}
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FORK_ASSERT_EQ(1, *token, "Error detected in signaling token");
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PROCESS_LOG("Process 0 wrote 1 to token...\n");
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// Attach shared_ VRAM
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void* ptr;
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err = hsa_amd_ipc_memory_attach(
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const_cast<hsa_amd_ipc_memory_t*>(&shared_->handle), shared_->size, 1,
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ag_list, &ptr);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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PROCESS_LOG(
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"Attached to IPC handle; P1 buffer address gpu-local memory is %p\n",
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ptr);
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// Attach shared_ signal
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hsa_signal_t ipc_signal;
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err = hsa_amd_ipc_signal_attach(
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const_cast<hsa_amd_ipc_signal_t*>(&shared_->signal_handle), &ipc_signal);
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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PROCESS_LOG("Attached to signal IPC handle\n");
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CheckAndFillBuffer(reinterpret_cast<uint32_t *>(ptr), 1, 2);
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PROCESS_LOG(
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"Confirmed P0 filled buffer with 1; P1 re-filled buffer with 2\n");
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PROCESS_LOG("PASSED on P1\n");
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hsa_signal_store_release(ipc_signal, 2);
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// Test ptrinfo - allocation is a single granule so this tests imported
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// fragment info.
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err = hsa_amd_pointer_info_set_userdata(ptr,
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reinterpret_cast<void*>(0xDEADBEEF));
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FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err, "hsa_amd_pointer_info_set_userdata() failed");
|
|
|
|
hsa_amd_pointer_info_t info;
|
|
info.size = sizeof(info);
|
|
err = hsa_amd_pointer_info(
|
|
reinterpret_cast<uint8_t*>(ptr) + shared_->size / 2, &info,
|
|
nullptr, nullptr, nullptr);
|
|
if ((info.sizeInBytes != shared_->size) ||
|
|
(info.userData != reinterpret_cast<void*>(0xDEADBEEF)) ||
|
|
(info.agentBaseAddress != ptr)) {
|
|
PROCESS_LOG("Pointer Info check failed.\n");
|
|
} else {
|
|
PROCESS_LOG("Pointer Info check PASSED.\n");
|
|
}
|
|
|
|
|
|
|
|
|
|
err = hsa_amd_ipc_memory_detach(ptr);
|
|
FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
|
|
|
|
hsa_signal_wait_relaxed(ipc_signal, HSA_SIGNAL_CONDITION_NE, 2, -1,
|
|
HSA_WAIT_STATE_BLOCKED);
|
|
|
|
err = hsa_signal_destroy(ipc_signal);
|
|
FORK_ASSERT_EQ(HSA_STATUS_SUCCESS, err);
|
|
Close();
|
|
// exit(0);
|
|
// hwloc hack - OpenCL registers exit handlers that can't execute in this process.
|
|
// Skip them.
|
|
abort();
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
void IPCTest::DisplayTestInfo(void) {
|
|
TestBase::DisplayTestInfo();
|
|
}
|
|
|
|
void IPCTest::DisplayResults(void) const {
|
|
TestBase::DisplayResults();
|
|
return;
|
|
}
|
|
|
|
void IPCTest::Close() {
|
|
// This will close handles opened within rocrtst utility calls and call
|
|
// hsa_shut_down(), so it should be done after other hsa cleanup
|
|
TestBase::Close();
|
|
}
|
|
|
|
#undef PROCESS_LOG
|
|
#undef FORK_ASSERT_EQ
|
|
#undef MSG
|
|
#undef Y
|