Chris Freehill
081a2cc875
In several places aql packets were written to queue all at once instead of doing the header atomically. These cases have been fixed. There were a few hsa_signal leaked that have been addressed. There was some duplication of code that has been addressed. Addresses ROCMOPS-456 Change-Id: Ia1869bc370f92e49ac560301df47741d5f76978e
504 lines
18 KiB
C++
Executable File
504 lines
18 KiB
C++
Executable File
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2017, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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#include <fcntl.h>
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#include <algorithm>
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#include <iostream>
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#include <vector>
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#include <memory>
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#include "suites/functional/memory_access.h"
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#include "common/base_rocr_utils.h"
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#include "common/common.h"
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#include "common/helper_funcs.h"
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#include "common/hsatimer.h"
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#include "gtest/gtest.h"
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#include "hsa/hsa.h"
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#include "hsa/hsa_ext_finalize.h"
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#define RET_IF_HSA_ERR(err) { \
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if ((err) != HSA_STATUS_SUCCESS) { \
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const char* msg = 0; \
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hsa_status_string(err, &msg); \
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std::cout << "hsa api call failure at line " << __LINE__ << ", file: " << \
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__FILE__ << ". Call returned " << err << std::endl; \
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std::cout << msg << std::endl; \
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return (err); \
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} \
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}
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MemoryAccessTest::MemoryAccessTest(void) :
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TestBase() {
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set_num_iteration(10); // Number of iterations to execute of the main test;
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// This is a default value which can be overridden
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// on the command line.
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set_title("RocR Memory Access Tests");
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set_description("This series of tests check memory allocation"
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"on GPU and CPU, i.e. GPU access to system memory "
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"and CPU access to GPU memory.");
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}
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MemoryAccessTest::~MemoryAccessTest(void) {
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}
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// Any 1-time setup involving member variables used in the rest of the test
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// should be done here.
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void MemoryAccessTest::SetUp(void) {
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hsa_status_t err;
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TestBase::SetUp();
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err = rocrtst::SetDefaultAgents(this);
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = rocrtst::SetPoolsTypical(this);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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return;
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}
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void MemoryAccessTest::Run(void) {
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// Compare required profile for this test case with what we're actually
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// running on
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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TestBase::Run();
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}
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void MemoryAccessTest::DisplayTestInfo(void) {
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TestBase::DisplayTestInfo();
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}
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void MemoryAccessTest::DisplayResults(void) const {
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// Compare required profile for this test case with what we're actually
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// running on
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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return;
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}
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void MemoryAccessTest::Close() {
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// This will close handles opened within rocrtst utility calls and call
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// hsa_shut_down(), so it should be done after other hsa cleanup
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TestBase::Close();
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}
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typedef struct __attribute__ ((aligned(16))) args_t {
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int *a;
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int *b;
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int *c;
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} args;
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args *kernArgs = NULL;
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static const char kSubTestSeparator[] = " **************************";
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static void PrintMemorySubtestHeader(const char *header) {
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std::cout << " *** Memory Subtest: " << header << " ***" << std::endl;
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}
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#if ROCRTST_EMULATOR_BUILD
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static const int kMemoryAllocSize = 8;
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#else
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static const int kMemoryAllocSize = 1024;
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#endif
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// Test to check GPU can read & write to system memory
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void MemoryAccessTest::GPUAccessToCPUMemoryTest(hsa_agent_t cpuAgent,
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hsa_agent_t gpuAgent) {
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hsa_status_t err;
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// Get Global Memory Pool on the gpuAgent to allocate gpu buffers
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hsa_amd_memory_pool_t gpu_pool;
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err = hsa_amd_agent_iterate_memory_pools(gpuAgent,
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rocrtst::GetGlobalMemoryPool,
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&gpu_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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hsa_amd_memory_pool_access_t access;
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hsa_amd_agent_memory_pool_get_info(cpuAgent, gpu_pool,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
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&access);
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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// hsa objects
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hsa_queue_t *queue = NULL; // command queue
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hsa_signal_t signal = {0}; // completion signal
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// get queue size
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uint32_t queue_size = 0;
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err = hsa_agent_get_info(gpuAgent,
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HSA_AGENT_INFO_QUEUE_MAX_SIZE, &queue_size);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// create queue
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err = hsa_queue_create(gpuAgent,
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queue_size, HSA_QUEUE_TYPE_MULTI,
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NULL, NULL, 0, 0, &queue);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Get System Memory Pool on the cpuAgent to allocate host side buffers
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hsa_amd_memory_pool_t global_pool;
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err = hsa_amd_agent_iterate_memory_pools(cpuAgent,
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rocrtst::GetGlobalMemoryPool,
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&global_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Find a memory pool that supports kernel arguments.
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hsa_amd_memory_pool_t kernarg_pool;
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err = hsa_amd_agent_iterate_memory_pools(cpuAgent,
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rocrtst::GetKernArgMemoryPool,
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&kernarg_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allocate the host side buffers
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// (sys_data,dup_sys_data,cpuResult,kernArg) on system memory
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int *sys_data = NULL;
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int *dup_sys_data = NULL;
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int *cpuResult = NULL;
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int *gpuResult = NULL;
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&cpuResult));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&sys_data));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&dup_sys_data));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allocate the kernel argument buffer from the kernarg_pool.
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err = hsa_amd_memory_pool_allocate(kernarg_pool, sizeof(args_t), 0,
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reinterpret_cast<void **>(&kernArgs));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// initialize the host buffers
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for (int i = 0; i < kMemoryAllocSize; ++i) {
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unsigned int seed = time(NULL);
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sys_data[i] = 1 + rand_r(&seed) % 1;
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dup_sys_data[i] = sys_data[i];
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}
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memset(cpuResult, 0, kMemoryAllocSize * sizeof(int));
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// for the dGPU, we have coarse grained local memory,
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// so allocate memory for it on the GPU's GLOBAL segment .
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// Get local memory of GPU to allocate device side buffers
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err = hsa_amd_memory_pool_allocate(gpu_pool, kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&gpuResult));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allow cpuAgent access to all allocated GPU memory.
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err = hsa_amd_agents_allow_access(1, &cpuAgent, NULL, gpuResult);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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memset(gpuResult, 0, kMemoryAllocSize * sizeof(int));
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// Allow gpuAgent access to all allocated system memory.
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, cpuResult);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, sys_data);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, dup_sys_data);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, kernArgs);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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kernArgs->a = sys_data;
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kernArgs->b = cpuResult; // system memory passed to gpu for write
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kernArgs->c = gpuResult; // gpu memory to verify that gpu read system data
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// Create the executable, get symbol by name and load the code object
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set_kernel_file_name("gpuReadWrite_kernels.hsaco");
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set_kernel_name("gpuReadWrite");
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err = rocrtst::LoadKernelFromObjFile(this, &gpuAgent);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Fill the dispatch packet with
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// workgroup_size, grid_size, kernelArgs and completion signal
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// Put it on the queue and launch the kernel by ringing the doorbell
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// create completion signal
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err = hsa_signal_create(1, 0, NULL, &signal);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// create aql packet
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hsa_kernel_dispatch_packet_t aql;
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memset(&aql, 0, sizeof(aql));
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// initialize aql packet
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aql.workgroup_size_x = 256;
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aql.workgroup_size_y = 1;
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aql.workgroup_size_z = 1;
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aql.grid_size_x = kMemoryAllocSize;
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aql.grid_size_y = 1;
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aql.grid_size_z = 1;
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aql.private_segment_size = 0;
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aql.group_segment_size = 0;
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aql.kernel_object = kernel_object(); // kernel_code;
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aql.kernarg_address = kernArgs;
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aql.completion_signal = signal;
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// const uint32_t queue_size = queue->size;
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const uint32_t queue_mask = queue->size - 1;
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// write to command queue
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uint64_t index = hsa_queue_load_write_index_relaxed(queue);
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hsa_queue_store_write_index_relaxed(queue, index + 1);
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rocrtst::WriteAQLToQueueLoc(queue, index, &aql);
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hsa_kernel_dispatch_packet_t *q_base_addr =
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>(queue->base_address);
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rocrtst::AtomicSetPacketHeader(
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(HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE) |
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(1 << HSA_PACKET_HEADER_BARRIER) |
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(HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE) |
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(HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE),
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(1 << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS),
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reinterpret_cast<hsa_kernel_dispatch_packet_t *>
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(&q_base_addr[index & queue_mask]));
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// ringdoor bell
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hsa_signal_store_relaxed(queue->doorbell_signal, index);
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// wait for the signal and reset it for future use
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while (hsa_signal_wait_scacquire(signal, HSA_SIGNAL_CONDITION_LT, 1,
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(uint64_t)-1, HSA_WAIT_STATE_ACTIVE)) { }
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hsa_signal_store_relaxed(signal, 1);
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// compare device and host side results
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if (verbosity() > 0) {
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std::cout<< "check gpu has read the system memory"<< std::endl;
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}
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for (int i = 0; i < kMemoryAllocSize; ++i) {
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ASSERT_EQ(gpuResult[i], dup_sys_data[i]);
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}
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if (verbosity() > 0) {
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std::cout<< "gpu has read the system memory successfully"<< std::endl;
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std::cout<< "check gpu has written to system memory"<< std::endl;
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}
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for (int i = 0; i < kMemoryAllocSize; ++i) {
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ASSERT_EQ(cpuResult[i], i);
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}
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if (verbosity() > 0) {
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std::cout<< "gpu has written to system memory successfully"<< std::endl;
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}
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if (sys_data) { hsa_memory_free(sys_data); }
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if (dup_sys_data) { hsa_memory_free(dup_sys_data); }
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if (cpuResult) {hsa_memory_free(cpuResult); }
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if (gpuResult) {hsa_memory_free(gpuResult); }
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if (kernArgs) { hsa_memory_free(kernArgs); }
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if (signal.handle) { hsa_signal_destroy(signal); }
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if (queue) { hsa_queue_destroy(queue); }
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} else {
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if (verbosity() > 0) {
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std::cout<< "Test not applicable as system is not large bar."
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"Skipping."<< std::endl;
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std::cout << kSubTestSeparator << std::endl;
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}
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return;
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}
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}
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// Test to check cpu can read & write to GPU memory
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void MemoryAccessTest::CPUAccessToGPUMemoryTest(hsa_agent_t cpuAgent,
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hsa_agent_t gpuAgent,
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hsa_amd_memory_pool_t pool) {
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hsa_status_t err;
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rocrtst::pool_info_t pool_i;
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err = rocrtst::AcquirePoolInfo(pool, &pool_i);
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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if (pool_i.segment == HSA_AMD_SEGMENT_GLOBAL &&
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pool_i.global_flag == HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_COARSE_GRAINED) {
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hsa_amd_memory_pool_access_t access;
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hsa_amd_agent_memory_pool_get_info(cpuAgent, pool,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
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&access);
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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if (!pool_i.alloc_allowed || pool_i.alloc_granule == 0 ||
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pool_i.alloc_alignment == 0) {
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if (verbosity() > 0) {
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std::cout << " Test not applicable. Skipping." << std::endl;
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std::cout << kSubTestSeparator << std::endl;
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}
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return;
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}
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auto gran_sz = pool_i.alloc_granule;
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auto pool_sz = pool_i.size / gran_sz;
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auto max_alloc_size = pool_sz/2;
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unsigned int max_element = max_alloc_size/sizeof(unsigned int);
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unsigned int *gpu_data;
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unsigned int *sys_data;
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sys_data = (unsigned int*)malloc(max_alloc_size);
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memset(sys_data, 0, max_alloc_size);
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for (unsigned int i = 1; i <= max_element; ++i) {
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sys_data[i] = i;
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}
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// err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, sys_data);
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// EXPECT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(pool, max_alloc_size, 0,
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reinterpret_cast<void**>(&gpu_data));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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/*
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if (err == HSA_STATUS_ERROR) {
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err = hsa_amd_memory_pool_free(gpu_data);
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}*/
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err = hsa_amd_agents_allow_access(1, &cpuAgent, NULL, gpu_data);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// EXPECT_EQ(HSA_STATUS_SUCCESS, err);
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memset(gpu_data, 0, max_alloc_size);
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// Verify CPU can read & write to GPU memory
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std::cout<< "Verify CPU can read & write to GPU memory"<< std::endl;
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for (unsigned int i = 1; i <= max_element; ++i) {
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gpu_data[i] = i; // Write to gpu memory directly
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}
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for (unsigned int i = 1; i <= max_element; ++i) {
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if (sys_data[i] != gpu_data[i]) { // Reading GPU memory
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fprintf(stdout, "Values not mathing !! sys_data[%d]:%d ,"
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"gpu_data[%d]\n", sys_data[i], i, gpu_data[i]);
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}
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}
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std::cout<< "CPU have read & write to GPU memory successfully"<< std::endl;
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err = hsa_amd_memory_pool_free(gpu_data);
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free(sys_data);
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} else {
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if (verbosity() > 0) {
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std::cout<< "Test not applicable as system is not large bar."
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"Skipping."<< std::endl;
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std::cout << kSubTestSeparator << std::endl;
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}
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return;
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}
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}
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}
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void MemoryAccessTest::CPUAccessToGPUMemoryTest(void) {
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hsa_status_t err;
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PrintMemorySubtestHeader("CPUAccessToGPUMemoryTest in Memory Pools");
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// find all cpu agents
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std::vector<hsa_agent_t> cpus;
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err = hsa_iterate_agents(rocrtst::IterateCPUAgents, &cpus);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// find all gpu agents
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std::vector<hsa_agent_t> gpus;
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err = hsa_iterate_agents(rocrtst::IterateGPUAgents, &gpus);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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for (unsigned int i = 0 ; i< gpus.size(); ++i) {
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hsa_amd_memory_pool_t gpu_pool;
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err = hsa_amd_agent_iterate_memory_pools(gpus[i],
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|
rocrtst::GetGlobalMemoryPool,
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|
&gpu_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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|
CPUAccessToGPUMemoryTest(cpus[0], gpus[i], gpu_pool);
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|
}
|
|
if (verbosity() > 0) {
|
|
std::cout << "subtest Passed" << std::endl;
|
|
std::cout << kSubTestSeparator << std::endl;
|
|
}
|
|
}
|
|
|
|
void MemoryAccessTest::GPUAccessToCPUMemoryTest(void) {
|
|
hsa_status_t err;
|
|
|
|
PrintMemorySubtestHeader("GPUAccessToCPUMemoryTest in Memory Pools");
|
|
// find all cpu agents
|
|
std::vector<hsa_agent_t> cpus;
|
|
err = hsa_iterate_agents(rocrtst::IterateCPUAgents, &cpus);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
|
|
// find all gpu agents
|
|
std::vector<hsa_agent_t> gpus;
|
|
err = hsa_iterate_agents(rocrtst::IterateGPUAgents, &gpus);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
|
|
for (unsigned int i = 0 ; i< gpus.size(); ++i) {
|
|
GPUAccessToCPUMemoryTest(cpus[0], gpus[i]);
|
|
}
|
|
|
|
if (verbosity() > 0) {
|
|
std::cout << "subtest Passed" << std::endl;
|
|
std::cout << kSubTestSeparator << std::endl;
|
|
}
|
|
}
|
|
|
|
#undef RET_IF_HSA_ERR
|