Chris Freehill
081a2cc875
In several places aql packets were written to queue all at once instead of doing the header atomically. These cases have been fixed. There were a few hsa_signal leaked that have been addressed. There was some duplication of code that has been addressed. Addresses ROCMOPS-456 Change-Id: Ia1869bc370f92e49ac560301df47741d5f76978e
488 linhas
18 KiB
C++
Ficheiro executável
488 linhas
18 KiB
C++
Ficheiro executável
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2018, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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#include <inttypes.h>
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#include <stdlib.h>
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#include <algorithm>
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#include <iostream>
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#include <vector>
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#include "suites/functional/signal_kernel.h"
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#include "common/base_rocr_utils.h"
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#include "common/common.h"
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#include "common/helper_funcs.h"
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#include "common/hsatimer.h"
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#include "common/concurrent_utils.h"
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#include "gtest/gtest.h"
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#include "hsa/hsa.h"
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#include "hsa/hsa_ext_finalize.h"
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static unsigned int NumOfKernels = 1;
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#define ASSERT_MSG(C, err) { \
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if (C == 1) { \
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std::cout << err << std::endl; \
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} \
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}
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SignalKernelTest::SignalKernelTest(SignalKernelType type_) : TestBase() {
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set_num_iteration(10); // Number of iterations to execute of the main test;
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// This is a default value which can be overridden
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// on the command line.
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if (type_ == SET) {
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set_title("RocR Signal Kernel Set Test");
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set_description("This test verifies that the signal is set from kernel");
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} else if (type_ == WAIT) {
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set_title("RocR Signal Wait Test");
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set_description("This test verifies that the signal is re-set from system side");
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} else if (type_ == MULTISET) {
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set_title("RocR Signal Kernel Multi Set Test");
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set_description("This test verifies that the signal is set on multiple work-items");
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} else if (type_ == MULTIWAIT) {
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set_title("RocR Signal Kernel Multi Set Test");
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set_description("This tset verifies that re-set signal from system side, multiple work-items");
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}
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}
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SignalKernelTest::~SignalKernelTest(void) {
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}
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void SignalKernelTest::SetUp(void) {
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hsa_status_t err;
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TestBase::SetUp();
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err = rocrtst::SetDefaultAgents(this);
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = rocrtst::SetPoolsTypical(this);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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return;
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}
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void SignalKernelTest::Run(void) {
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// Compare required profile for this test case with what we're actually
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// running on
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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TestBase::Run();
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}
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void SignalKernelTest::DisplayTestInfo(void) {
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TestBase::DisplayTestInfo();
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}
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void SignalKernelTest::DisplayResults(void) const {
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return;
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}
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void SignalKernelTest::Close() {
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// This will close handles opened within rocrtst utility calls and call
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// hsa_shut_down(), so it should be done after other hsa cleanup
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TestBase::Close();
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}
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// The kernarg data structure
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typedef struct __attribute__ ((aligned(16))) signal_args_s {
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void *signal_values;
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} signal_args_t;
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signal_args_t signal_args;
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void SignalKernelTest::KernelSetFunction(SignalKernelType type_) {
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hsa_status_t status;
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// Get the GPU agents into a vector
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std::vector<hsa_agent_t> agent_list;
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status = hsa_iterate_agents(rocrtst::IterateGPUAgents, &agent_list);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Get CPU agent to get the kern_arg pool
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std::vector<hsa_agent_t> cpu_agent;
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status = hsa_iterate_agents(rocrtst::IterateCPUAgents, &cpu_agent);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Repeat the test for each agent
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unsigned int ii;
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for (ii = 0; ii < agent_list.size(); ++ii) {
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// Check if the queue supports dispatch
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uint32_t features = 0;
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status = hsa_agent_get_info(agent_list[ii], HSA_AGENT_INFO_FEATURE, &features);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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if (0 == (features & HSA_AGENT_FEATURE_KERNEL_DISPATCH)) {
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continue;
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}
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// Find a memory pool that supports fine grained memory
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hsa_amd_memory_pool_t global_pool;
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global_pool.handle = (uint64_t)-1;
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status = hsa_amd_agent_iterate_memory_pools(agent_list[ii], rocrtst::GetGlobalMemoryPool, &global_pool);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Obtain the agent's machine model
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hsa_machine_model_t machine_model;
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status = hsa_agent_get_info(agent_list[ii], HSA_AGENT_INFO_MACHINE_MODEL, &machine_model);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Find a memory pool that supports kernel arguments
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hsa_amd_memory_pool_t kernarg_pool;
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kernarg_pool.handle = (uint64_t)-1;
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status = hsa_amd_agent_iterate_memory_pools(cpu_agent[0], rocrtst::GetKernArgMemoryPool, &kernarg_pool);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Create a queue
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hsa_queue_t* queue;
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status = hsa_queue_create(agent_list[ii], 1024, HSA_QUEUE_TYPE_SINGLE, NULL, NULL, UINT32_MAX, UINT32_MAX, &queue);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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set_kernel_file_name("signal_operations_kernels.hsaco");
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if (type_ == SET) {
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set_kernel_name("signal_st_rlx_kernel");
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} else if (type_ == MULTISET) {
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set_kernel_name("signal_st_rlx_kernel_multi");
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NumOfKernels = 16;
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} else if (type_ == WAIT) {
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set_kernel_name("signal_wait_kernel");
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} else if (type_ == MULTIWAIT) {
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set_kernel_name("signal_wait_kernel_multi");
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NumOfKernels = 16;
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}
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status = rocrtst::LoadKernelFromObjFile(this, &agent_list[ii]);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Allocate the kernel argument buffer from the correct pool
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signal_args_t* kernarg_buffer = NULL;
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status = hsa_amd_memory_pool_allocate(kernarg_pool,
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sizeof(signal_args_t), 0,
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reinterpret_cast<void**>(&kernarg_buffer));
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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status = hsa_amd_agents_allow_access(1, &agent_list[ii], NULL, kernarg_buffer);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Create the completion signal
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hsa_signal_t completion_signal;
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status = hsa_signal_create(1, 0, NULL, &completion_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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hsa_amd_memory_pool_access_t access;
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status = hsa_amd_agent_memory_pool_get_info(cpu_agent[0],
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global_pool,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
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&access);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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hsa_signal_t* kernel_signal;
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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// Create the kernel signal
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status = hsa_amd_memory_pool_allocate(global_pool,
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NumOfKernels*sizeof(hsa_signal_t), 0,
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reinterpret_cast<void**>(&kernel_signal));
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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status = hsa_amd_agents_allow_access(1, &cpu_agent[0], NULL, kernel_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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for (unsigned int k = 0; k < NumOfKernels; ++k) {
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status = hsa_signal_create(1, 0, NULL, kernel_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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}
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// Set the signal_args with kernel_signal, will be accessed from Kernel side
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signal_args.signal_values = reinterpret_cast<void*>(kernel_signal);
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}
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memcpy(kernarg_buffer, &signal_args, sizeof(signal_args_t));
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// Setup the dispatch packet
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hsa_kernel_dispatch_packet_t dispatch_packet;
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memset(&dispatch_packet, 0, sizeof(hsa_kernel_dispatch_packet_t));
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dispatch_packet.workgroup_size_x = NumOfKernels;
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dispatch_packet.workgroup_size_y = 1;
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dispatch_packet.workgroup_size_z = 1;
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dispatch_packet.grid_size_x = NumOfKernels;
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dispatch_packet.grid_size_y = 1;
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dispatch_packet.grid_size_z = 1;
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dispatch_packet.kernel_object = kernel_object();
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dispatch_packet.group_segment_size = group_segment_size();
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dispatch_packet.private_segment_size = private_segment_size();
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dispatch_packet.kernarg_address = kernarg_buffer;
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dispatch_packet.completion_signal = completion_signal;
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// const uint32_t queue_size = queue->size;
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const uint32_t queue_mask = queue->size - 1;
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// write to command queue
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uint64_t index = hsa_queue_load_write_index_relaxed(queue);
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hsa_queue_store_write_index_relaxed(queue, index + 1);
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rocrtst::WriteAQLToQueueLoc(queue, index, &dispatch_packet);
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dispatch_packet.header |= HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE;
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dispatch_packet.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE;
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dispatch_packet.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE;
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dispatch_packet.header |= 1 << HSA_PACKET_HEADER_BARRIER;
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dispatch_packet.setup |= 1 << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS;
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void* q_base = queue->base_address;
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// Set the Aql packet header
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rocrtst::AtomicSetPacketHeader(dispatch_packet.header, dispatch_packet.setup,
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&(reinterpret_cast<hsa_kernel_dispatch_packet_t*>
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(q_base))[index & queue_mask]);
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// ringdoor bell
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hsa_signal_store_relaxed(queue->doorbell_signal, index);
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if (type_ == WAIT) {
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for (unsigned int k = 0; k < NumOfKernels; ++k) {
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// setting the kernel_signal to 0 from system side.
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kernel_signal[k].handle = 0;
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}
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}
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// Wait on the completion signal
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hsa_signal_wait_relaxed(completion_signal, HSA_SIGNAL_CONDITION_EQ, 0, UINT64_MAX, HSA_WAIT_STATE_BLOCKED);
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// Check kernel signal
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for (unsigned int k = 0; k < NumOfKernels; ++k) {
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ASSERT_EQ(0, (int)(kernel_signal[k].handle));
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}
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status = hsa_signal_destroy(completion_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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status = hsa_amd_memory_pool_free(kernel_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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}
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status = hsa_amd_memory_pool_free(kernarg_buffer);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Destroy the queue
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status = hsa_queue_destroy(queue);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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}
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}
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void SignalKernelTest::TestSignalKernelSet(void) {
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KernelSetFunction(SET);
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}
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void SignalKernelTest::TestSignalKernelMultiSet(void) {
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KernelSetFunction(MULTISET);
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}
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void SignalKernelTest::TestSignalKernelWait(void) {
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KernelSetFunction(WAIT);
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}
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void SignalKernelTest::TestSignalKernelMultiWait(void) {
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hsa_status_t status;
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// Get the GPU agents into a vector
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std::vector<hsa_agent_t> agent_list;
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status = hsa_iterate_agents(rocrtst::IterateGPUAgents, &agent_list);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Get CPU agent to get the kern_arg pool
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std::vector<hsa_agent_t> cpu_agent;
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status = hsa_iterate_agents(rocrtst::IterateCPUAgents, &cpu_agent);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Repeat the test for each agent
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unsigned int ii;
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for (ii = 0; ii < agent_list.size(); ++ii) {
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// Check if the queue supports dispatch
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uint32_t features = 0;
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status = hsa_agent_get_info(agent_list[ii], HSA_AGENT_INFO_FEATURE, &features);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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if (0 == (features & HSA_AGENT_FEATURE_KERNEL_DISPATCH)) {
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continue;
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}
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// Find a memory pool that supports fine grained memory
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hsa_amd_memory_pool_t global_pool;
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global_pool.handle = (uint64_t)-1;
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status = hsa_amd_agent_iterate_memory_pools(agent_list[ii], rocrtst::GetGlobalMemoryPool, &global_pool);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Obtain the agent's machine model
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hsa_machine_model_t machine_model;
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status = hsa_agent_get_info(agent_list[ii], HSA_AGENT_INFO_MACHINE_MODEL, &machine_model);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Find a memory pool that supports kernel arguments
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hsa_amd_memory_pool_t kernarg_pool;
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kernarg_pool.handle = (uint64_t)-1;
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status = hsa_amd_agent_iterate_memory_pools(cpu_agent[0], rocrtst::GetKernArgMemoryPool, &kernarg_pool);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Create a queue
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hsa_queue_t* queue;
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status = hsa_queue_create(agent_list[ii], 1024, HSA_QUEUE_TYPE_SINGLE, NULL, NULL, UINT32_MAX, UINT32_MAX, &queue);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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set_kernel_file_name("signal_operations_kernels.hsaco");
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set_kernel_name("signal_wait_kernel_multi");
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status = rocrtst::LoadKernelFromObjFile(this, &agent_list[ii]);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Allocate the kernel argument buffer from the correct pool
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signal_args_t* kernarg_buffer = NULL;
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status = hsa_amd_memory_pool_allocate(kernarg_pool,
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sizeof(signal_args_t), 0,
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reinterpret_cast<void**>(&kernarg_buffer));
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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status = hsa_amd_agents_allow_access(1, &agent_list[ii], NULL, kernarg_buffer);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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// Create the completion signal
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hsa_signal_t completion_signal;
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status = hsa_signal_create(1, 0, NULL, &completion_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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hsa_amd_memory_pool_access_t access;
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status = hsa_amd_agent_memory_pool_get_info(cpu_agent[0],
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global_pool,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
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&access);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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hsa_signal_t* kernel_signal;
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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// Create the kernel signal
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status = hsa_amd_memory_pool_allocate(global_pool,
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NumOfKernels*sizeof(hsa_signal_t), 0,
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reinterpret_cast<void**>(&kernel_signal));
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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status = hsa_amd_agents_allow_access(1, &cpu_agent[0], NULL, kernel_signal);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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for (unsigned int k = 0; k < NumOfKernels; ++k) {
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status = hsa_signal_create(1, 0, NULL, kernel_signal + k);
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ASSERT_EQ(status, HSA_STATUS_SUCCESS);
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}
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// Set the signal_args with kernel_signal, will be accessed from Kernel side
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signal_args.signal_values = reinterpret_cast<void*>(kernel_signal);
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}
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memcpy(kernarg_buffer, &signal_args, sizeof(signal_args_t));
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// Setup the dispatch packet
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hsa_kernel_dispatch_packet_t dispatch_packet;
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memset(&dispatch_packet, 0, sizeof(hsa_kernel_dispatch_packet_t));
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dispatch_packet.workgroup_size_x = NumOfKernels;
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dispatch_packet.workgroup_size_y = 1;
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dispatch_packet.workgroup_size_z = 1;
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dispatch_packet.grid_size_x = NumOfKernels;
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dispatch_packet.grid_size_y = 1;
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dispatch_packet.grid_size_z = 1;
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dispatch_packet.kernel_object = kernel_object();
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dispatch_packet.group_segment_size = group_segment_size();
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dispatch_packet.private_segment_size = private_segment_size();
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dispatch_packet.kernarg_address = kernarg_buffer;
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dispatch_packet.completion_signal = completion_signal;
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// const uint32_t queue_size = queue->size;
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const uint32_t queue_mask = queue->size - 1;
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// write to command queue
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uint64_t index = hsa_queue_load_write_index_relaxed(queue);
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hsa_queue_store_write_index_relaxed(queue, index + 1);
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rocrtst::WriteAQLToQueueLoc(queue, index, &dispatch_packet);
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dispatch_packet.header |= HSA_PACKET_TYPE_KERNEL_DISPATCH << HSA_PACKET_HEADER_TYPE;
|
|
dispatch_packet.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE;
|
|
dispatch_packet.header |= HSA_FENCE_SCOPE_SYSTEM << HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE;
|
|
dispatch_packet.header |= 1 << HSA_PACKET_HEADER_BARRIER;
|
|
dispatch_packet.setup |= 1 << HSA_KERNEL_DISPATCH_PACKET_SETUP_DIMENSIONS;
|
|
|
|
void* q_base = queue->base_address;
|
|
// Set the Aql packet header
|
|
rocrtst::AtomicSetPacketHeader(dispatch_packet.header, dispatch_packet.setup,
|
|
&(reinterpret_cast<hsa_kernel_dispatch_packet_t*>
|
|
(q_base))[index & queue_mask]);
|
|
|
|
|
|
// ringdoor bell
|
|
hsa_signal_store_relaxed(queue->doorbell_signal, index);
|
|
|
|
// setting the kernel_signal to 0 from system side.
|
|
for (unsigned int k = 0; k < NumOfKernels; ++k) {
|
|
kernel_signal[k].handle = 0;
|
|
}
|
|
// Wait on the completion signal
|
|
hsa_signal_wait_relaxed(completion_signal, HSA_SIGNAL_CONDITION_EQ, 0, UINT64_MAX, HSA_WAIT_STATE_BLOCKED);
|
|
|
|
// Check kernel signal
|
|
ASSERT_EQ(0, (int)kernel_signal->handle);
|
|
|
|
// destroy the signal created
|
|
status = hsa_signal_destroy(completion_signal);
|
|
ASSERT_EQ(status, HSA_STATUS_SUCCESS);
|
|
|
|
status = hsa_amd_memory_pool_free(kernarg_buffer);
|
|
ASSERT_EQ(status, HSA_STATUS_SUCCESS);
|
|
|
|
// Destroy the queue
|
|
status = hsa_queue_destroy(queue);
|
|
ASSERT_EQ(status, HSA_STATUS_SUCCESS);
|
|
}
|
|
}
|
|
|