zichguan-amd
13a06f5131
* Enable baseline comparison between workloads from the same path Signed-off-by: zichguan-amd <zichuan.guan@amd.com> * Formatting Signed-off-by: zichguan-amd <zichuan.guan@amd.com> * Change test to verify baseline works with same path Signed-off-by: zichguan-amd <zichuan.guan@amd.com> * Add three-way comparison test case Signed-off-by: zichguan-amd <zichuan.guan@amd.com> --------- Signed-off-by: zichguan-amd <zichuan.guan@amd.com>
6 خطوط
4.6 KiB
Plaintext
6 خطوط
4.6 KiB
Plaintext
pmc: SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES SQ_ACCUM_PREV_HIRES SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TCC_EA_RDREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_GMI_CREDIT_STALL[0] TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] TCC_EA_WRREQ_IO_CREDIT_STALL[0] TCC_EA_RDREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_GMI_CREDIT_STALL[1] TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] TCC_EA_WRREQ_IO_CREDIT_STALL[1] TCC_EA_RDREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_GMI_CREDIT_STALL[2] TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] TCC_EA_WRREQ_IO_CREDIT_STALL[2] TCC_EA_RDREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_GMI_CREDIT_STALL[3] TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] TCC_EA_WRREQ_IO_CREDIT_STALL[3] TCC_EA_RDREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_GMI_CREDIT_STALL[4] TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] TCC_EA_WRREQ_IO_CREDIT_STALL[4] TCC_EA_RDREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_GMI_CREDIT_STALL[5] TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] TCC_EA_WRREQ_IO_CREDIT_STALL[5] TCC_EA_RDREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_GMI_CREDIT_STALL[6] TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] TCC_EA_WRREQ_IO_CREDIT_STALL[6] TCC_EA_RDREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_GMI_CREDIT_STALL[7] TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] TCC_EA_WRREQ_IO_CREDIT_STALL[7] TCC_EA_RDREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_GMI_CREDIT_STALL[8] TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] TCC_EA_WRREQ_IO_CREDIT_STALL[8] TCC_EA_RDREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_GMI_CREDIT_STALL[9] TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] TCC_EA_WRREQ_IO_CREDIT_STALL[9] TCC_EA_RDREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_GMI_CREDIT_STALL[10] TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] TCC_EA_WRREQ_IO_CREDIT_STALL[10] TCC_EA_RDREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_GMI_CREDIT_STALL[11] TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] TCC_EA_WRREQ_IO_CREDIT_STALL[11] TCC_EA_RDREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_GMI_CREDIT_STALL[12] TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] TCC_EA_WRREQ_IO_CREDIT_STALL[12] TCC_EA_RDREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_GMI_CREDIT_STALL[13] TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] TCC_EA_WRREQ_IO_CREDIT_STALL[13] TCC_EA_RDREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_GMI_CREDIT_STALL[14] TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] TCC_EA_WRREQ_IO_CREDIT_STALL[14] TCC_EA_RDREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_GMI_CREDIT_STALL[15] TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] TCC_EA_WRREQ_IO_CREDIT_STALL[15] TCC_EA_RDREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_GMI_CREDIT_STALL[16] TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] TCC_EA_WRREQ_IO_CREDIT_STALL[16] TCC_EA_RDREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_GMI_CREDIT_STALL[17] TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] TCC_EA_WRREQ_IO_CREDIT_STALL[17] TCC_EA_RDREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_GMI_CREDIT_STALL[18] TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] TCC_EA_WRREQ_IO_CREDIT_STALL[18] TCC_EA_RDREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_GMI_CREDIT_STALL[19] TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] TCC_EA_WRREQ_IO_CREDIT_STALL[19] TCC_EA_RDREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_GMI_CREDIT_STALL[20] TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] TCC_EA_WRREQ_IO_CREDIT_STALL[20] TCC_EA_RDREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_GMI_CREDIT_STALL[21] TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] TCC_EA_WRREQ_IO_CREDIT_STALL[21] TCC_EA_RDREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_GMI_CREDIT_STALL[22] TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] TCC_EA_WRREQ_IO_CREDIT_STALL[22] TCC_EA_RDREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_GMI_CREDIT_STALL[23] TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] TCC_EA_WRREQ_IO_CREDIT_STALL[23] TCC_EA_RDREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_GMI_CREDIT_STALL[24] TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] TCC_EA_WRREQ_IO_CREDIT_STALL[24] TCC_EA_RDREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_GMI_CREDIT_STALL[25] TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] TCC_EA_WRREQ_IO_CREDIT_STALL[25] TCC_EA_RDREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_GMI_CREDIT_STALL[26] TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] TCC_EA_WRREQ_IO_CREDIT_STALL[26] TCC_EA_RDREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_GMI_CREDIT_STALL[27] TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] TCC_EA_WRREQ_IO_CREDIT_STALL[27] TCC_EA_RDREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_GMI_CREDIT_STALL[28] TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] TCC_EA_WRREQ_IO_CREDIT_STALL[28] TCC_EA_RDREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_GMI_CREDIT_STALL[29] TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] TCC_EA_WRREQ_IO_CREDIT_STALL[29] TCC_EA_RDREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_GMI_CREDIT_STALL[30] TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] TCC_EA_WRREQ_IO_CREDIT_STALL[30] TCC_EA_RDREQ_IO_CREDIT_STALL[31] TCC_EA_RDREQ_GMI_CREDIT_STALL[31] TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] TCC_EA_WRREQ_IO_CREDIT_STALL[31] CPC_ME1_BUSY_FOR_PACKET_DECODE CPC_CPC_UTCL2IU_STALL SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN GRBM_COUNT GRBM_GUI_ACTIVE
|
|
|
|
gpu:
|
|
range:
|
|
kernel:
|