Amber Lin
4dd9dbb128
When the Thunk is initialized multiple times in the lifetime of a single process
, some global resources are leaked. This can happen when dlopen and dlclose are
used to load the library at runtime, rather than linking the runtime against
the Thunk. This patch adds the destructor to release global resources when
dlclose is called.
Change-Id: Ia00da0d41f095d0b2706f98c0e75effedd596f49
[ROCm/ROCR-Runtime commit: 582b70f9c3]
384 lines
11 KiB
C
384 lines
11 KiB
C
/*
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* Copyright © 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
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* of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including
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* the next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include "libhsakmt.h"
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#include "pmc_table.h"
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#include "linux/kfd_ioctl.h"
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#include <unistd.h>
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#define BITS_PER_BYTE CHAR_BIT
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#define HSA_PERF_MAGIC4CC 0x54415348
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enum perf_trace_state {
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PERF_TRACE_STATE__STOPPED = 0,
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PERF_TRACE_STATE__STARTED
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};
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struct perf_trace {
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uint32_t magic4cc;
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uint32_t gpu_id;
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enum perf_trace_state state;
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};
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extern int amd_hsa_thunk_lock_fd;
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static HsaCounterProperties *counter_props[MAX_NODES] = {NULL};
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void __attribute__ ((destructor)) perfctr_release_global_resources(void);
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static int blockid2uuid(enum perf_block_id block_id, HSA_UUID *uuid)
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{
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int rc = 0;
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switch (block_id) {
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case PERFCOUNTER_BLOCKID__SQ:
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*uuid = HSA_PROFILEBLOCK_AMD_SQ;
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break;
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default:
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/* If we reach this point, it's a bug */
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rc = -1;
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}
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return rc;
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}
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcGetCounterProperties(
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HSAuint32 NodeId, //IN
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HsaCounterProperties** CounterProperties //OUT
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)
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{
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HSAKMT_STATUS rc = HSAKMT_STATUS_SUCCESS;
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uint32_t gpu_id, i, block_id;
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uint16_t dev_id;
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uint32_t counter_props_size = 0;
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uint32_t total_counters = 0;
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uint32_t total_concurrent = 0;
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struct perf_counter_block block = {0};
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if (CounterProperties == NULL)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (validate_nodeid(NodeId, &gpu_id) != 0)
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return HSAKMT_STATUS_INVALID_NODE_UNIT;
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if (counter_props[NodeId] == NULL) {
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dev_id = get_device_id_by_node(NodeId);
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for (i = 0; i < PERFCOUNTER_BLOCKID__MAX; i++) {
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rc = get_block_properties(dev_id, i, &block);
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if (rc != HSAKMT_STATUS_SUCCESS)
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return rc;
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total_concurrent += block.num_of_slots;
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total_counters += block.num_of_counters;
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}
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counter_props_size = sizeof(HsaCounterProperties) +
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sizeof(HsaCounterBlockProperties)*(PERFCOUNTER_BLOCKID__MAX-1) +
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sizeof(HsaCounter)*(total_counters-1);
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counter_props[NodeId] = malloc(counter_props_size);
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if (counter_props[NodeId] == NULL)
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return HSAKMT_STATUS_NO_MEMORY;
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counter_props[NodeId]->NumBlocks = PERFCOUNTER_BLOCKID__MAX;
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counter_props[NodeId]->NumConcurrent = total_concurrent;
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for (block_id = 0; block_id < PERFCOUNTER_BLOCKID__MAX; block_id++)
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{
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rc = get_block_properties(dev_id, block_id, &block);
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if (rc != HSAKMT_STATUS_SUCCESS) {
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free(counter_props[NodeId]);
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return rc;
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}
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/* Filling the SQ block */
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blockid2uuid(block_id, &counter_props[NodeId]->Blocks[block_id].BlockId);
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counter_props[NodeId]->Blocks[block_id].NumCounters = block.num_of_counters;
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counter_props[NodeId]->Blocks[block_id].NumConcurrent = block.num_of_slots;
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for (i = 0; i < block.num_of_counters; i++) {
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counter_props[NodeId]->Blocks[block_id].Counters[i].BlockIndex = block_id;
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counter_props[NodeId]->Blocks[block_id].Counters[i].CounterId = block.counter_ids[i];
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counter_props[NodeId]->Blocks[block_id].Counters[i].CounterSizeInBits = block.counter_size_in_bits;
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counter_props[NodeId]->Blocks[block_id].Counters[i].CounterMask = block.counter_mask;
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counter_props[NodeId]->Blocks[block_id].Counters[i].Flags.ui32.Global = 1;
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counter_props[NodeId]->Blocks[block_id].Counters[i].Type = HSA_PROFILE_TYPE_NONPRIV_IMMEDIATE;
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}
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}
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}
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*CounterProperties = counter_props[NodeId];
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return HSAKMT_STATUS_SUCCESS;
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}
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/**
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Registers a set of (HW) counters to be used for tracing/profiling
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcRegisterTrace(
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HSAuint32 NodeId, //IN
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HSAuint32 NumberOfCounters, //IN
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HsaCounter* Counters, //IN
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HsaPmcTraceRoot* TraceRoot //OUT
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)
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{
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uint32_t gpu_id, i;
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uint64_t min_buf_size = 0;
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uint32_t concurrent_counters[PERFCOUNTER_BLOCKID__MAX] = {0};
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struct perf_trace *trace = NULL;
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if (Counters == NULL || TraceRoot == NULL || NumberOfCounters == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (validate_nodeid(NodeId, &gpu_id) != 0)
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return HSAKMT_STATUS_INVALID_NODE_UNIT;
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/* Calculating the minimum buffer size */
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for (i = 0; i < NumberOfCounters; i++) {
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if (Counters[i].BlockIndex >= PERFCOUNTER_BLOCKID__MAX)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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min_buf_size += Counters[i].CounterSizeInBits/BITS_PER_BYTE;
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concurrent_counters[Counters[i].BlockIndex]++;
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}
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/* Verifying that the number of counters per block is not larger than the amount of slots */
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if (concurrent_counters[PERFCOUNTER_BLOCKID__SQ] > counter_props[NodeId]->Blocks[PERFCOUNTER_BLOCKID__SQ].NumConcurrent)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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trace = malloc(sizeof(trace));
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if (trace == NULL)
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return HSAKMT_STATUS_NO_MEMORY;
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trace->magic4cc = HSA_PERF_MAGIC4CC;
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trace->gpu_id = gpu_id;
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trace->state = PERF_TRACE_STATE__STOPPED;
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TraceRoot->NumberOfPasses = 1;
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TraceRoot->TraceBufferMinSizeBytes = PAGE_ALIGN_UP(min_buf_size);
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TraceRoot->TraceId = PORT_VPTR_TO_UINT64(trace);
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return HSAKMT_STATUS_SUCCESS;
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}
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/**
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Unregisters a set of (HW) counters used for tracing/profiling
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcUnregisterTrace(
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HSAuint32 NodeId, //IN
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HSATraceId TraceId //IN
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)
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{
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uint32_t gpu_id;
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struct perf_trace *trace;
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if (TraceId == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (validate_nodeid(NodeId, &gpu_id) != 0)
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return HSAKMT_STATUS_INVALID_NODE_UNIT;
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trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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if (trace->gpu_id != gpu_id)
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return HSAKMT_STATUS_INVALID_NODE_UNIT;
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/* If the trace is in the running state, stop it */
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if (trace->state == PERF_TRACE_STATE__STARTED) {
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HSAKMT_STATUS status = hsaKmtPmcStopTrace(TraceId);
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if (status != HSAKMT_STATUS_SUCCESS)
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return status;
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}
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free(trace);
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return HSAKMT_STATUS_SUCCESS;
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}
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/**
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Allows a user mode process to get exclusive access to the defined set of (HW) counters
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used for tracing/profiling
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcAcquireTraceAccess(
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HSAuint32 NodeId, //IN
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HSATraceId TraceId //IN
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)
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{
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struct perf_trace *trace;
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if (TraceId == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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if (amd_hsa_thunk_lock_fd > 0) {
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if (lockf( amd_hsa_thunk_lock_fd, F_TLOCK, 0 ) != 0)
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return HSAKMT_STATUS_ERROR;
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else
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return HSAKMT_STATUS_SUCCESS;
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}
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else {
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return HSAKMT_STATUS_ERROR;
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}
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}
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/**
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Allows a user mode process to release exclusive access to the defined set of (HW) counters
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used for tracing/profiling
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcReleaseTraceAccess(
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HSAuint32 NodeId, //IN
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HSATraceId TraceId //IN
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)
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{
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struct perf_trace *trace;
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if (TraceId == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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if (amd_hsa_thunk_lock_fd > 0) {
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if (lockf( amd_hsa_thunk_lock_fd, F_ULOCK, 0 ) != 0)
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return HSAKMT_STATUS_ERROR;
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else
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return HSAKMT_STATUS_SUCCESS;
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}
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else {
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return HSAKMT_STATUS_ERROR;
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}
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}
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/**
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Starts tracing operation on a previously established set of performance counters
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcStartTrace(
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HSATraceId TraceId, //IN
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void* TraceBuffer, //IN (page aligned)
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HSAuint64 TraceBufferSizeBytes //IN (page aligned)
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)
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{
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struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (TraceId == 0 || TraceBuffer == NULL || TraceBufferSizeBytes == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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trace->state = PERF_TRACE_STATE__STARTED;
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return HSAKMT_STATUS_SUCCESS;
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}
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/**
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Forces an update of all the counters that a previously started trace operation has registered
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcQueryTrace(
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HSATraceId TraceId //IN
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)
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{
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struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (TraceId == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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return HSAKMT_STATUS_SUCCESS;
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}
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/**
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Stops tracing operation on a previously established set of performance counters
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*/
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HSAKMT_STATUS
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HSAKMTAPI
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hsaKmtPmcStopTrace(
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HSATraceId TraceId //IN
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)
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{
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struct perf_trace *trace = (struct perf_trace *)PORT_UINT64_TO_VPTR(TraceId);
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if (TraceId == 0)
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return HSAKMT_STATUS_INVALID_PARAMETER;
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if (trace->magic4cc != HSA_PERF_MAGIC4CC)
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return HSAKMT_STATUS_INVALID_HANDLE;
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trace->state = PERF_TRACE_STATE__STOPPED;
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return HSAKMT_STATUS_SUCCESS;
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}
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void perfctr_release_global_resources(void)
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{
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int i;
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for (i=0; i<MAX_NODES; i++)
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if (counter_props[i] != NULL) {
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free(counter_props[i]);
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counter_props[i] = NULL;
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}
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}
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