gobhardw
132 lines
4.0 KiB
C++
132 lines
4.0 KiB
C++
/* Copyright (c) 2023 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef SRC_CORE_NON_GFXIP_COUNTERS_MMIO_H
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#define SRC_CORE_NON_GFXIP_COUNTERS_MMIO_H
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#include <hsa/hsa.h>
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#include "src/core/hardware/hsa_info.h"
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#include <pciaccess.h>
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#include <mutex>
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#include <iostream>
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#include <unistd.h>
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#include <sstream>
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namespace rocmtools {
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namespace mmio {
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#define FUNCTION_START() PrintFunctionPhase(__FUNCTION__, 0)
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#define FUNCTION_END() PrintFunctionPhase(__FUNCTION__, 1)
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// uncomment below to see register write sequences
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// #define DEBUG_TRACE = 1
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void PrintFunctionPhase(const char* function_name, int phase);
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void PrintRegisterData(uint32_t& index_value, uint32_t& data_value, const char* function_name,
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int phase);
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// Index/Data registers
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const static uint32_t INDIRECT_REG_INDEX = 0x38;
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const static uint32_t INDIRECT_REG_DATA = 0x3c;
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typedef enum { DEFAULT_MMAP, DF_PERFMON, UMC_PERFMON, PCIE_PERFMON } mmap_type_t;
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class MMIOManager;
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class MMIO {
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public:
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virtual bool RegisterWriteAPI(uint32_t reg_offset, uint32_t value);
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virtual bool RegisterReadAPI(uint32_t reg_offset, uint32_t& value);
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virtual void SetIndexDataRegisters(const uint32_t index_reg, const uint32_t data_reg) {
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index_reg_addr = (uint32_t*)((char*)pci_memory_ + index_reg);
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data_reg_addr = (uint32_t*)((char*)pci_memory_ + data_reg);
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}
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MMIO(MMIO& other) = delete;
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void operator=(const MMIO&) = delete;
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virtual ~MMIO();
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friend class MMIOManager;
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const Agent::AgentInfo& GetAgentInfo() { return *agent_info_; }
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mmap_type_t Type() { return type_; }
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protected:
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MMIO(const Agent::AgentInfo& info);
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// default constructor; helpful for derived classes
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// which want to setup mmio construction differently
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MMIO() { type_ = DEFAULT_MMAP; };
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const Agent::AgentInfo* agent_info_;
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struct pci_device* pci_device_;
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size_t pci_memory_size_;
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uint32_t* pci_memory_;
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mmap_type_t type_;
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uint32_t* index_reg_addr;
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uint32_t* data_reg_addr;
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};
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// PciePerfmonMMIO has same mmio setup approach as
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// done in MMIO class
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class PciePerfmonMMIO : public MMIO {
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public:
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friend class MMIOManager;
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protected:
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PciePerfmonMMIO(const Agent::AgentInfo& info) : MMIO(info) { type_ = PCIE_PERFMON; };
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};
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// DFPerfmonMMIO has same mmio setup approach as
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// done in MMIO class
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class DFPerfmonMMIO : public MMIO {
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public:
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friend class MMIOManager;
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protected:
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DFPerfmonMMIO(const Agent::AgentInfo& info) : MMIO(info) { type_ = DF_PERFMON; };
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};
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/*
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Class to manage mmio for UMC/DF/PCIe etc.
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The mmio approach for the different IPs may
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be same or different. For eg: UMC and PCIe share
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the same mmio and index/data registers
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*/
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class MMIOManager {
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public:
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static MMIO* CreateMMIO(mmap_type_t type, const Agent::AgentInfo& info);
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static MMIO* GetMMIOInstance(mmap_type_t type, const Agent::AgentInfo& info);
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static void DestroyMMIOInstance(MMIO* instance);
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private:
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static void AddInstance(MMIO* instance);
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static std::map<decltype(hsa_agent_t::handle), std::vector<MMIO*>> mmio_instances_;
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};
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} // namespace mmio
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} // namespace rocmtools
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#endif |