Files
rocm-systems/tests/workloads/mixbench2/mi100/prev_analysis/602.csv
T
JoseSantosAMD 717a21cf84 Update csv headers, and SystemExit codes
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-02-04 12:44:47 -06:00

657 B

1MetricAvgMinMaxUnit
2Wave request Failed (CS)326122.71856287424626930578Cycles
3CS Stall20865.6946107784420739300Cycles
4CS Stall Rate5.41817326083023150.082.06766558397588Pct
5Scratch Stall0.000Cycles
6Insufficient SIMD Waveslots65504.7485029940140685113Simd
7Insufficient SIMD VGPRs638510.4790419162048660107Simd
8Insufficient SIMD SGPRs0.000Simd
9Insufficient CU LDS_Per_Workgroup0.000Cu
10Insufficient CU Barries0.000Cu
11Insufficient Bulky Resource0.000Cu
12Reach CU Threadgroups Limit0.000Cycles
13Reach CU Wave Limit0.000Cycles
14VGPR Writes4.04.04.0Cycles/wave
15SGPR Writes5.0059880239520965.06.0Cycles/wave