rocm-systems/tests/workloads/D_str_inv3/mi200/pmc_perf.csv

1	Index	KernelName	gpu-id	queue-id	queue-index	pid	tid	grd	wgr	lds	scr	vgpr	sgpr	fbar	sig	obj	SQ_CYCLES	SQ_BUSY_CYCLES	SQ_WAVES	SQ_BUSY_CU_CYCLES	SQ_WAVE_CYCLES	SQC_TC_INST_REQ	SQC_TC_DATA_READ_REQ	SQC_TC_DATA_WRITE_REQ	GRBM_COUNT	GRBM_GUI_ACTIVE	TCP_GATE_EN1_sum	TCP_GATE_EN2_sum	TCP_TD_TCP_STALL_CYCLES_sum	TCP_TCR_TCP_STALL_CYCLES_sum	TA_TA_BUSY_sum	TA_SH_FIFO_BUSY_sum	TD_TD_BUSY_sum	TD_TC_STALL_sum	SPI_CSN_WINDOW_VALID	SPI_CSN_BUSY	CPC_CPC_STAT_BUSY	CPC_CPC_STAT_IDLE	CPF_CPF_STAT_BUSY	CPF_CPF_STAT_STALL	TCC_CYCLE_sum	TCC_BUSY_sum	TCC_PROBE_sum	TCC_PROBE_ALL_sum	SQC_TC_DATA_ATOMIC_REQ	SQC_TC_STALL	SQC_TC_REQ	SQC_DCACHE_REQ_READ_16	SQC_ICACHE_REQ	SQC_ICACHE_HITS	SQC_ICACHE_MISSES	SQC_ICACHE_MISSES_DUPLICATE	GRBM_SPI_BUSY	TCP_READ_TAGCONFLICT_STALL_CYCLES_sum	TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum	TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum	TCP_TA_TCP_STATE_READ_sum	TA_SH_FIFO_CMD_BUSY_sum	TA_SH_FIFO_ADDR_BUSY_sum	TD_SPI_STALL_sum	TD_LOAD_WAVEFRONT_sum	SPI_CSN_NUM_THREADGROUPS	SPI_CSN_WAVE	CPC_CPC_TCIU_BUSY	CPC_CPC_TCIU_IDLE	CPF_CPF_TCIU_BUSY	CPF_CPF_TCIU_STALL	TCC_NC_REQ_sum	TCC_UC_REQ_sum	TCC_CC_REQ_sum	TCC_RW_REQ_sum	SQ_LDS_MEM_VIOLATIONS	SQ_LDS_ATOMIC_RETURN	SQ_LDS_IDX_ACTIVE	SQ_WAVES_RESTORED	SQ_WAVES_SAVED	SQ_INSTS_SMEM_NORM	SQ_INSTS_MFMA	SQ_INSTS_VALU_MFMA_I8	TA_BUFFER_COALESCED_READ_CYCLES_sum	TA_BUFFER_COALESCED_WRITE_CYCLES_sum	TCC_EA_ATOMIC_LEVEL_sum	SQ_INSTS_VALU_MFMA_F16	SQ_INSTS_VALU_MFMA_BF16	SQ_INSTS_VALU_MFMA_F32	SQ_INSTS_VALU_MFMA_F64	SQ_VALU_MFMA_BUSY_CYCLES	SQ_INSTS_FLAT_LDS_ONLY	SQ_INSTS_VALU_MFMA_MOPS_I8	SQ_INSTS_VALU_MFMA_MOPS_F16	TA_ADDR_STALLED_BY_TC_CYCLES_sum	TA_TOTAL_WAVEFRONTS_sum	TCC_ATOMIC[0]	TCC_CYCLE[0]	TCC_EA_ATOMIC[0]	TCC_EA_ATOMIC_LEVEL[0]	TCC_ATOMIC[1]	TCC_CYCLE[1]	TCC_EA_ATOMIC[1]	TCC_EA_ATOMIC_LEVEL[1]	TCC_ATOMIC[2]	TCC_CYCLE[2]	TCC_EA_ATOMIC[2]	TCC_EA_ATOMIC_LEVEL[2]	TCC_ATOMIC[3]	TCC_CYCLE[3]	TCC_EA_ATOMIC[3]	TCC_EA_ATOMIC_LEVEL[3]	TCC_ATOMIC[4]	TCC_CYCLE[4]	TCC_EA_ATOMIC[4]	TCC_EA_ATOMIC_LEVEL[4]	TCC_ATOMIC[5]	TCC_CYCLE[5]	TCC_EA_ATOMIC[5]	TCC_EA_ATOMIC_LEVEL[5]	TCC_ATOMIC[6]	TCC_CYCLE[6]	TCC_EA_ATOMIC[6]	TCC_EA_ATOMIC_LEVEL[6]	TCC_ATOMIC[7]	TCC_CYCLE[7]	TCC_EA_ATOMIC[7]	TCC_EA_ATOMIC_LEVEL[7]	TCC_ATOMIC[8]	TCC_CYCLE[8]	TCC_EA_ATOMIC[8]	TCC_EA_ATOMIC_LEVEL[8]	TCC_ATOMIC[9]	TCC_CYCLE[9]	TCC_EA_ATOMIC[9]	TCC_EA_ATOMIC_LEVEL[9]	TCC_ATOMIC[10]	TCC_CYCLE[10]	TCC_EA_ATOMIC[10]	TCC_EA_ATOMIC_LEVEL[10]	TCC_ATOMIC[11]	TCC_CYCLE[11]	TCC_EA_ATOMIC[11]	TCC_EA_ATOMIC_LEVEL[11]	TCC_ATOMIC[12]	TCC_CYCLE[12]	TCC_EA_ATOMIC[12]	TCC_EA_ATOMIC_LEVEL[12]	TCC_ATOMIC[13]	TCC_CYCLE[13]	TCC_EA_ATOMIC[13]	TCC_EA_ATOMIC_LEVEL[13]	TCC_ATOMIC[14]	TCC_CYCLE[14]	TCC_EA_ATOMIC[14]	TCC_EA_ATOMIC_LEVEL[14]	TCC_ATOMIC[15]	TCC_CYCLE[15]	TCC_EA_ATOMIC[15]	TCC_EA_ATOMIC_LEVEL[15]	TCC_ATOMIC[16]	TCC_CYCLE[16]	TCC_EA_ATOMIC[16]	TCC_EA_ATOMIC_LEVEL[16]	TCC_ATOMIC[17]	TCC_CYCLE[17]	TCC_EA_ATOMIC[17]	TCC_EA_ATOMIC_LEVEL[17]	TCC_ATOMIC[18]	TCC_CYCLE[18]	TCC_EA_ATOMIC[18]	TCC_EA_ATOMIC_LEVEL[18]	TCC_ATOMIC[19]	TCC_CYCLE[19]	TCC_EA_ATOMIC[19]	TCC_EA_ATOMIC_LEVEL[19]	TCC_ATOMIC[20]	TCC_CYCLE[20]	TCC_EA_ATOMIC[20]	TCC_EA_ATOMIC_LEVEL[20]	TCC_ATOMIC[21]	TCC_CYCLE[21]	TCC_EA_ATOMIC[21]	TCC_EA_ATOMIC_LEVEL[21]	TCC_ATOMIC[22]	TCC_CYCLE[22]	TCC_EA_ATOMIC[22]	TCC_EA_ATOMIC_LEVEL[22]	TCC_ATOMIC[23]	TCC_CYCLE[23]	TCC_EA_ATOMIC[23]	TCC_EA_ATOMIC_LEVEL[23]	TCC_ATOMIC[24]	TCC_CYCLE[24]	TCC_EA_ATOMIC[24]	TCC_EA_ATOMIC_LEVEL[24]	TCC_ATOMIC[25]	TCC_CYCLE[25]	TCC_EA_ATOMIC[25]	TCC_EA_ATOMIC_LEVEL[25]	TCC_ATOMIC[26]	TCC_CYCLE[26]	TCC_EA_ATOMIC[26]	TCC_EA_ATOMIC_LEVEL[26]	TCC_ATOMIC[27]	TCC_CYCLE[27]	TCC_EA_ATOMIC[27]	TCC_EA_ATOMIC_LEVEL[27]	TCC_ATOMIC[28]	TCC_CYCLE[28]	TCC_EA_ATOMIC[28]	TCC_EA_ATOMIC_LEVEL[28]	TCC_ATOMIC[29]	TCC_CYCLE[29]	TCC_EA_ATOMIC[29]	TCC_EA_ATOMIC_LEVEL[29]	TCC_ATOMIC[30]	TCC_CYCLE[30]	TCC_EA_ATOMIC[30]	TCC_EA_ATOMIC_LEVEL[30]	TCC_ATOMIC[31]	TCC_CYCLE[31]	TCC_EA_ATOMIC[31]	TCC_EA_ATOMIC_LEVEL[31]	SQ_INSTS_VALU_MFMA_MOPS_BF16	SQ_INSTS_VALU_MFMA_MOPS_F32	SQ_INSTS_VALU_MFMA_MOPS_F64	TA_ADDR_STALLED_BY_TD_CYCLES_sum	TA_DATA_STALLED_BY_TC_CYCLES_sum	TCC_EA_RDREQ[0]	TCC_EA_RDREQ_32B[0]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[0]	TCC_EA_RDREQ_GMI_CREDIT_STALL[0]	TCC_EA_RDREQ[1]	TCC_EA_RDREQ_32B[1]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[1]	TCC_EA_RDREQ_GMI_CREDIT_STALL[1]	TCC_EA_RDREQ[2]	TCC_EA_RDREQ_32B[2]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[2]	TCC_EA_RDREQ_GMI_CREDIT_STALL[2]	TCC_EA_RDREQ[3]	TCC_EA_RDREQ_32B[3]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[3]	TCC_EA_RDREQ_GMI_CREDIT_STALL[3]	TCC_EA_RDREQ[4]	TCC_EA_RDREQ_32B[4]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[4]	TCC_EA_RDREQ_GMI_CREDIT_STALL[4]	TCC_EA_RDREQ[5]	TCC_EA_RDREQ_32B[5]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[5]	TCC_EA_RDREQ_GMI_CREDIT_STALL[5]	TCC_EA_RDREQ[6]	TCC_EA_RDREQ_32B[6]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[6]	TCC_EA_RDREQ_GMI_CREDIT_STALL[6]	TCC_EA_RDREQ[7]	TCC_EA_RDREQ_32B[7]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[7]	TCC_EA_RDREQ_GMI_CREDIT_STALL[7]	TCC_EA_RDREQ[8]	TCC_EA_RDREQ_32B[8]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[8]	TCC_EA_RDREQ_GMI_CREDIT_STALL[8]	TCC_EA_RDREQ[9]	TCC_EA_RDREQ_32B[9]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[9]	TCC_EA_RDREQ_GMI_CREDIT_STALL[9]	TCC_EA_RDREQ[10]	TCC_EA_RDREQ_32B[10]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[10]	TCC_EA_RDREQ_GMI_CREDIT_STALL[10]	TCC_EA_RDREQ[11]	TCC_EA_RDREQ_32B[11]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[11]	TCC_EA_RDREQ_GMI_CREDIT_STALL[11]	TCC_EA_RDREQ[12]	TCC_EA_RDREQ_32B[12]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[12]	TCC_EA_RDREQ_GMI_CREDIT_STALL[12]	TCC_EA_RDREQ[13]	TCC_EA_RDREQ_32B[13]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[13]	TCC_EA_RDREQ_GMI_CREDIT_STALL[13]	TCC_EA_RDREQ[14]	TCC_EA_RDREQ_32B[14]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[14]	TCC_EA_RDREQ_GMI_CREDIT_STALL[14]	TCC_EA_RDREQ[15]	TCC_EA_RDREQ_32B[15]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[15]	TCC_EA_RDREQ_GMI_CREDIT_STALL[15]	TCC_EA_RDREQ[16]	TCC_EA_RDREQ_32B[16]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[16]	TCC_EA_RDREQ_GMI_CREDIT_STALL[16]	TCC_EA_RDREQ[17]	TCC_EA_RDREQ_32B[17]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[17]	TCC_EA_RDREQ_GMI_CREDIT_STALL[17]	TCC_EA_RDREQ[18]	TCC_EA_RDREQ_32B[18]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[18]	TCC_EA_RDREQ_GMI_CREDIT_STALL[18]	TCC_EA_RDREQ[19]	TCC_EA_RDREQ_32B[19]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[19]	TCC_EA_RDREQ_GMI_CREDIT_STALL[19]	TCC_EA_RDREQ[20]	TCC_EA_RDREQ_32B[20]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[20]	TCC_EA_RDREQ_GMI_CREDIT_STALL[20]	TCC_EA_RDREQ[21]	TCC_EA_RDREQ_32B[21]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[21]	TCC_EA_RDREQ_GMI_CREDIT_STALL[21]	TCC_EA_RDREQ[22]	TCC_EA_RDREQ_32B[22]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[22]	TCC_EA_RDREQ_GMI_CREDIT_STALL[22]	TCC_EA_RDREQ[23]	TCC_EA_RDREQ_32B[23]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[23]	TCC_EA_RDREQ_GMI_CREDIT_STALL[23]	TCC_EA_RDREQ[24]	TCC_EA_RDREQ_32B[24]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[24]	TCC_EA_RDREQ_GMI_CREDIT_STALL[24]	TCC_EA_RDREQ[25]	TCC_EA_RDREQ_32B[25]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[25]	TCC_EA_RDREQ_GMI_CREDIT_STALL[25]	TCC_EA_RDREQ[26]	TCC_EA_RDREQ_32B[26]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[26]	TCC_EA_RDREQ_GMI_CREDIT_STALL[26]	TCC_EA_RDREQ[27]	TCC_EA_RDREQ_32B[27]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[27]	TCC_EA_RDREQ_GMI_CREDIT_STALL[27]	TCC_EA_RDREQ[28]	TCC_EA_RDREQ_32B[28]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[28]	TCC_EA_RDREQ_GMI_CREDIT_STALL[28]	TCC_EA_RDREQ[29]	TCC_EA_RDREQ_32B[29]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[29]	TCC_EA_RDREQ_GMI_CREDIT_STALL[29]	TCC_EA_RDREQ[30]	TCC_EA_RDREQ_32B[30]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[30]	TCC_EA_RDREQ_GMI_CREDIT_STALL[30]	TCC_EA_RDREQ[31]	TCC_EA_RDREQ_32B[31]	TCC_EA_RDREQ_DRAM_CREDIT_STALL[31]	TCC_EA_RDREQ_GMI_CREDIT_STALL[31]	TA_FLAT_WAVEFRONTS_sum	TA_FLAT_READ_WAVEFRONTS_sum	TCC_EA_RDREQ_IO_CREDIT_STALL[0]	TCC_EA_RDREQ_LEVEL[0]	TCC_EA_WRREQ[0]	TCC_EA_WRREQ_64B[0]	TCC_EA_RDREQ_IO_CREDIT_STALL[1]	TCC_EA_RDREQ_LEVEL[1]	TCC_EA_WRREQ[1]	TCC_EA_WRREQ_64B[1]	TCC_EA_RDREQ_IO_CREDIT_STALL[2]	TCC_EA_RDREQ_LEVEL[2]	TCC_EA_WRREQ[2]	TCC_EA_WRREQ_64B[2]	TCC_EA_RDREQ_IO_CREDIT_STALL[3]	TCC_EA_RDREQ_LEVEL[3]	TCC_EA_WRREQ[3]	TCC_EA_WRREQ_64B[3]	TCC_EA_RDREQ_IO_CREDIT_STALL[4]	TCC_EA_RDREQ_LEVEL[4]	TCC_EA_WRREQ[4]	TCC_EA_WRREQ_64B[4]	TCC_EA_RDREQ_IO_CREDIT_STALL[5]	TCC_EA_RDREQ_LEVEL[5]	TCC_EA_WRREQ[5]	TCC_EA_WRREQ_64B[5]	TCC_EA_RDREQ_IO_CREDIT_STALL[6]	TCC_EA_RDREQ_LEVEL[6]	TCC_EA_WRREQ[6]	TCC_EA_WRREQ_64B[6]	TCC_EA_RDREQ_IO_CREDIT_STALL[7]	TCC_EA_RDREQ_LEVEL[7]	TCC_EA_WRREQ[7]	TCC_EA_WRREQ_64B[7]	TCC_EA_RDREQ_IO_CREDIT_STALL[8]	TCC_EA_RDREQ_LEVEL[8]	TCC_EA_WRREQ[8]	TCC_EA_WRREQ_64B[8]	TCC_EA_RDREQ_IO_CREDIT_STALL[9]	TCC_EA_RDREQ_LEVEL[9]	TCC_EA_WRREQ[9]	TCC_EA_WRREQ_64B[9]	TCC_EA_RDREQ_IO_CREDIT_STALL[10]	TCC_EA_RDREQ_LEVEL[10]	TCC_EA_WRREQ[10]	TCC_EA_WRREQ_64B[10]	TCC_EA_RDREQ_IO_CREDIT_STALL[11]	TCC_EA_RDREQ_LEVEL[11]	TCC_EA_WRREQ[11]	TCC_EA_WRREQ_64B[11]	TCC_EA_RDREQ_IO_CREDIT_STALL[12]	TCC_EA_RDREQ_LEVEL[12]	TCC_EA_WRREQ[12]	TCC_EA_WRREQ_64B[12]	TCC_EA_RDREQ_IO_CREDIT_STALL[13]	TCC_EA_RDREQ_LEVEL[13]	TCC_EA_WRREQ[13]	TCC_EA_WRREQ_64B[13]	TCC_EA_RDREQ_IO_CREDIT_STALL[14]	TCC_EA_RDREQ_LEVEL[14]	TCC_EA_WRREQ[14]	TCC_EA_WRREQ_64B[14]	TCC_EA_RDREQ_IO_CREDIT_STALL[15]	TCC_EA_RDREQ_LEVEL[15]	TCC_EA_WRREQ[15]	TCC_EA_WRREQ_64B[15]	TCC_EA_RDREQ_IO_CREDIT_STALL[16]	TCC_EA_RDREQ_LEVEL[16]	TCC_EA_WRREQ[16]	TCC_EA_WRREQ_64B[16]	TCC_EA_RDREQ_IO_CREDIT_STALL[17]	TCC_EA_RDREQ_LEVEL[17]	TCC_EA_WRREQ[17]	TCC_EA_WRREQ_64B[17]	TCC_EA_RDREQ_IO_CREDIT_STALL[18]	TCC_EA_RDREQ_LEVEL[18]	TCC_EA_WRREQ[18]	TCC_EA_WRREQ_64B[18]	TCC_EA_RDREQ_IO_CREDIT_STALL[19]	TCC_EA_RDREQ_LEVEL[19]	TCC_EA_WRREQ[19]	TCC_EA_WRREQ_64B[19]	TCC_EA_RDREQ_IO_CREDIT_STALL[20]	TCC_EA_RDREQ_LEVEL[20]	TCC_EA_WRREQ[20]	TCC_EA_WRREQ_64B[20]	TCC_EA_RDREQ_IO_CREDIT_STALL[21]	TCC_EA_RDREQ_LEVEL[21]	TCC_EA_WRREQ[21]	TCC_EA_WRREQ_64B[21]	TCC_EA_RDREQ_IO_CREDIT_STALL[22]	TCC_EA_RDREQ_LEVEL[22]	TCC_EA_WRREQ[22]	TCC_EA_WRREQ_64B[22]	TCC_EA_RDREQ_IO_CREDIT_STALL[23]	TCC_EA_RDREQ_LEVEL[23]	TCC_EA_WRREQ[23]	TCC_EA_WRREQ_64B[23]	TCC_EA_RDREQ_IO_CREDIT_STALL[24]	TCC_EA_RDREQ_LEVEL[24]	TCC_EA_WRREQ[24]	TCC_EA_WRREQ_64B[24]	TCC_EA_RDREQ_IO_CREDIT_STALL[25]	TCC_EA_RDREQ_LEVEL[25]	TCC_EA_WRREQ[25]	TCC_EA_WRREQ_64B[25]	TCC_EA_RDREQ_IO_CREDIT_STALL[26]	TCC_EA_RDREQ_LEVEL[26]	TCC_EA_WRREQ[26]	TCC_EA_WRREQ_64B[26]	TCC_EA_RDREQ_IO_CREDIT_STALL[27]	TCC_EA_RDREQ_LEVEL[27]	TCC_EA_WRREQ[27]	TCC_EA_WRREQ_64B[27]	TCC_EA_RDREQ_IO_CREDIT_STALL[28]	TCC_EA_RDREQ_LEVEL[28]	TCC_EA_WRREQ[28]	TCC_EA_WRREQ_64B[28]	TCC_EA_RDREQ_IO_CREDIT_STALL[29]	TCC_EA_RDREQ_LEVEL[29]	TCC_EA_WRREQ[29]	TCC_EA_WRREQ_64B[29]	TCC_EA_RDREQ_IO_CREDIT_STALL[30]	TCC_EA_RDREQ_LEVEL[30]	TCC_EA_WRREQ[30]	TCC_EA_WRREQ_64B[30]	TCC_EA_RDREQ_IO_CREDIT_STALL[31]	TCC_EA_RDREQ_LEVEL[31]	TCC_EA_WRREQ[31]	TCC_EA_WRREQ_64B[31]	TA_FLAT_WRITE_WAVEFRONTS_sum	TA_FLAT_ATOMIC_WAVEFRONTS_sum	TCC_EA_WRREQ_DRAM_CREDIT_STALL[0]	TCC_EA_WRREQ_GMI_CREDIT_STALL[0]	TCC_EA_WRREQ_IO_CREDIT_STALL[0]	TCC_EA_WRREQ_LEVEL[0]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[1]	TCC_EA_WRREQ_GMI_CREDIT_STALL[1]	TCC_EA_WRREQ_IO_CREDIT_STALL[1]	TCC_EA_WRREQ_LEVEL[1]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[2]	TCC_EA_WRREQ_GMI_CREDIT_STALL[2]	TCC_EA_WRREQ_IO_CREDIT_STALL[2]	TCC_EA_WRREQ_LEVEL[2]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[3]	TCC_EA_WRREQ_GMI_CREDIT_STALL[3]	TCC_EA_WRREQ_IO_CREDIT_STALL[3]	TCC_EA_WRREQ_LEVEL[3]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[4]	TCC_EA_WRREQ_GMI_CREDIT_STALL[4]	TCC_EA_WRREQ_IO_CREDIT_STALL[4]	TCC_EA_WRREQ_LEVEL[4]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[5]	TCC_EA_WRREQ_GMI_CREDIT_STALL[5]	TCC_EA_WRREQ_IO_CREDIT_STALL[5]	TCC_EA_WRREQ_LEVEL[5]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[6]	TCC_EA_WRREQ_GMI_CREDIT_STALL[6]	TCC_EA_WRREQ_IO_CREDIT_STALL[6]	TCC_EA_WRREQ_LEVEL[6]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[7]	TCC_EA_WRREQ_GMI_CREDIT_STALL[7]	TCC_EA_WRREQ_IO_CREDIT_STALL[7]	TCC_EA_WRREQ_LEVEL[7]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[8]	TCC_EA_WRREQ_GMI_CREDIT_STALL[8]	TCC_EA_WRREQ_IO_CREDIT_STALL[8]	TCC_EA_WRREQ_LEVEL[8]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[9]	TCC_EA_WRREQ_GMI_CREDIT_STALL[9]	TCC_EA_WRREQ_IO_CREDIT_STALL[9]	TCC_EA_WRREQ_LEVEL[9]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[10]	TCC_EA_WRREQ_GMI_CREDIT_STALL[10]	TCC_EA_WRREQ_IO_CREDIT_STALL[10]	TCC_EA_WRREQ_LEVEL[10]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[11]	TCC_EA_WRREQ_GMI_CREDIT_STALL[11]	TCC_EA_WRREQ_IO_CREDIT_STALL[11]	TCC_EA_WRREQ_LEVEL[11]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[12]	TCC_EA_WRREQ_GMI_CREDIT_STALL[12]	TCC_EA_WRREQ_IO_CREDIT_STALL[12]	TCC_EA_WRREQ_LEVEL[12]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[13]	TCC_EA_WRREQ_GMI_CREDIT_STALL[13]	TCC_EA_WRREQ_IO_CREDIT_STALL[13]	TCC_EA_WRREQ_LEVEL[13]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[14]	TCC_EA_WRREQ_GMI_CREDIT_STALL[14]	TCC_EA_WRREQ_IO_CREDIT_STALL[14]	TCC_EA_WRREQ_LEVEL[14]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[15]	TCC_EA_WRREQ_GMI_CREDIT_STALL[15]	TCC_EA_WRREQ_IO_CREDIT_STALL[15]	TCC_EA_WRREQ_LEVEL[15]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[16]	TCC_EA_WRREQ_GMI_CREDIT_STALL[16]	TCC_EA_WRREQ_IO_CREDIT_STALL[16]	TCC_EA_WRREQ_LEVEL[16]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[17]	TCC_EA_WRREQ_GMI_CREDIT_STALL[17]	TCC_EA_WRREQ_IO_CREDIT_STALL[17]	TCC_EA_WRREQ_LEVEL[17]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[18]	TCC_EA_WRREQ_GMI_CREDIT_STALL[18]	TCC_EA_WRREQ_IO_CREDIT_STALL[18]	TCC_EA_WRREQ_LEVEL[18]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[19]	TCC_EA_WRREQ_GMI_CREDIT_STALL[19]	TCC_EA_WRREQ_IO_CREDIT_STALL[19]	TCC_EA_WRREQ_LEVEL[19]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[20]	TCC_EA_WRREQ_GMI_CREDIT_STALL[20]	TCC_EA_WRREQ_IO_CREDIT_STALL[20]	TCC_EA_WRREQ_LEVEL[20]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[21]	TCC_EA_WRREQ_GMI_CREDIT_STALL[21]	TCC_EA_WRREQ_IO_CREDIT_STALL[21]	TCC_EA_WRREQ_LEVEL[21]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[22]	TCC_EA_WRREQ_GMI_CREDIT_STALL[22]	TCC_EA_WRREQ_IO_CREDIT_STALL[22]	TCC_EA_WRREQ_LEVEL[22]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[23]	TCC_EA_WRREQ_GMI_CREDIT_STALL[23]	TCC_EA_WRREQ_IO_CREDIT_STALL[23]	TCC_EA_WRREQ_LEVEL[23]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[24]	TCC_EA_WRREQ_GMI_CREDIT_STALL[24]	TCC_EA_WRREQ_IO_CREDIT_STALL[24]	TCC_EA_WRREQ_LEVEL[24]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[25]	TCC_EA_WRREQ_GMI_CREDIT_STALL[25]	TCC_EA_WRREQ_IO_CREDIT_STALL[25]	TCC_EA_WRREQ_LEVEL[25]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[26]	TCC_EA_WRREQ_GMI_CREDIT_STALL[26]	TCC_EA_WRREQ_IO_CREDIT_STALL[26]	TCC_EA_WRREQ_LEVEL[26]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[27]	TCC_EA_WRREQ_GMI_CREDIT_STALL[27]	TCC_EA_WRREQ_IO_CREDIT_STALL[27]	TCC_EA_WRREQ_LEVEL[27]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[28]	TCC_EA_WRREQ_GMI_CREDIT_STALL[28]	TCC_EA_WRREQ_IO_CREDIT_STALL[28]	TCC_EA_WRREQ_LEVEL[28]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[29]	TCC_EA_WRREQ_GMI_CREDIT_STALL[29]	TCC_EA_WRREQ_IO_CREDIT_STALL[29]	TCC_EA_WRREQ_LEVEL[29]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[30]	TCC_EA_WRREQ_GMI_CREDIT_STALL[30]	TCC_EA_WRREQ_IO_CREDIT_STALL[30]	TCC_EA_WRREQ_LEVEL[30]	TCC_EA_WRREQ_DRAM_CREDIT_STALL[31]	TCC_EA_WRREQ_GMI_CREDIT_STALL[31]	TCC_EA_WRREQ_IO_CREDIT_STALL[31]	TCC_EA_WRREQ_LEVEL[31]	TA_FLAT_COALESCEABLE_WAVEFRONTS_sum	TCC_HIT[0]	TCC_MISS[0]	TCC_READ[0]	TCC_REQ[0]	TCC_HIT[1]	TCC_MISS[1]	TCC_READ[1]	TCC_REQ[1]	TCC_HIT[2]	TCC_MISS[2]	TCC_READ[2]	TCC_REQ[2]	TCC_HIT[3]	TCC_MISS[3]	TCC_READ[3]	TCC_REQ[3]	TCC_HIT[4]	TCC_MISS[4]	TCC_READ[4]	TCC_REQ[4]	TCC_HIT[5]	TCC_MISS[5]	TCC_READ[5]	TCC_REQ[5]	TCC_HIT[6]	TCC_MISS[6]	TCC_READ[6]	TCC_REQ[6]	TCC_HIT[7]	TCC_MISS[7]	TCC_READ[7]	TCC_REQ[7]	TCC_HIT[8]	TCC_MISS[8]	TCC_READ[8]	TCC_REQ[8]	TCC_HIT[9]	TCC_MISS[9]	TCC_READ[9]	TCC_REQ[9]	TCC_HIT[10]	TCC_MISS[10]	TCC_READ[10]	TCC_REQ[10]	TCC_HIT[11]	TCC_MISS[11]	TCC_READ[11]	TCC_REQ[11]	TCC_HIT[12]	TCC_MISS[12]	TCC_READ[12]	TCC_REQ[12]	TCC_HIT[13]	TCC_MISS[13]	TCC_READ[13]	TCC_REQ[13]	TCC_HIT[14]	TCC_MISS[14]	TCC_READ[14]	TCC_REQ[14]	TCC_HIT[15]	TCC_MISS[15]	TCC_READ[15]	TCC_REQ[15]	TCC_HIT[16]	TCC_MISS[16]	TCC_READ[16]	TCC_REQ[16]	TCC_HIT[17]	TCC_MISS[17]	TCC_READ[17]	TCC_REQ[17]	TCC_HIT[18]	TCC_MISS[18]	TCC_READ[18]	TCC_REQ[18]	TCC_HIT[19]	TCC_MISS[19]	TCC_READ[19]	TCC_REQ[19]	TCC_HIT[20]	TCC_MISS[20]	TCC_READ[20]	TCC_REQ[20]	TCC_HIT[21]	TCC_MISS[21]	TCC_READ[21]	TCC_REQ[21]	TCC_HIT[22]	TCC_MISS[22]	TCC_READ[22]	TCC_REQ[22]	TCC_HIT[23]	TCC_MISS[23]	TCC_READ[23]	TCC_REQ[23]	TCC_HIT[24]	TCC_MISS[24]	TCC_READ[24]	TCC_REQ[24]	TCC_HIT[25]	TCC_MISS[25]	TCC_READ[25]	TCC_REQ[25]	TCC_HIT[26]	TCC_MISS[26]	TCC_READ[26]	TCC_REQ[26]	TCC_HIT[27]	TCC_MISS[27]	TCC_READ[27]	TCC_REQ[27]	TCC_HIT[28]	TCC_MISS[28]	TCC_READ[28]	TCC_REQ[28]	TCC_HIT[29]	TCC_MISS[29]	TCC_READ[29]	TCC_REQ[29]	TCC_HIT[30]	TCC_MISS[30]	TCC_READ[30]	TCC_REQ[30]	TCC_HIT[31]	TCC_MISS[31]	TCC_READ[31]	TCC_REQ[31]	TCC_RW_REQ[0]	TCC_TOO_MANY_EA_WRREQS_STALL[0]	TCC_WRITE[0]	TCC_RW_REQ[1]	TCC_TOO_MANY_EA_WRREQS_STALL[1]	TCC_WRITE[1]	TCC_RW_REQ[2]	TCC_TOO_MANY_EA_WRREQS_STALL[2]	TCC_WRITE[2]	TCC_RW_REQ[3]	TCC_TOO_MANY_EA_WRREQS_STALL[3]	TCC_WRITE[3]	TCC_RW_REQ[4]	TCC_TOO_MANY_EA_WRREQS_STALL[4]	TCC_WRITE[4]	TCC_RW_REQ[5]	TCC_TOO_MANY_EA_WRREQS_STALL[5]	TCC_WRITE[5]	TCC_RW_REQ[6]	TCC_TOO_MANY_EA_WRREQS_STALL[6]	TCC_WRITE[6]	TCC_RW_REQ[7]	TCC_TOO_MANY_EA_WRREQS_STALL[7]	TCC_WRITE[7]	TCC_RW_REQ[8]	TCC_TOO_MANY_EA_WRREQS_STALL[8]	TCC_WRITE[8]	TCC_RW_REQ[9]	TCC_TOO_MANY_EA_WRREQS_STALL[9]	TCC_WRITE[9]	TCC_RW_REQ[10]	TCC_TOO_MANY_EA_WRREQS_STALL[10]	TCC_WRITE[10]	TCC_RW_REQ[11]	TCC_TOO_MANY_EA_WRREQS_STALL[11]	TCC_WRITE[11]	TCC_RW_REQ[12]	TCC_TOO_MANY_EA_WRREQS_STALL[12]	TCC_WRITE[12]	TCC_RW_REQ[13]	TCC_TOO_MANY_EA_WRREQS_STALL[13]	TCC_WRITE[13]	TCC_RW_REQ[14]	TCC_TOO_MANY_EA_WRREQS_STALL[14]	TCC_WRITE[14]	TCC_RW_REQ[15]	TCC_TOO_MANY_EA_WRREQS_STALL[15]	TCC_WRITE[15]	TCC_RW_REQ[16]	TCC_TOO_MANY_EA_WRREQS_STALL[16]	TCC_WRITE[16]	TCC_RW_REQ[17]	TCC_TOO_MANY_EA_WRREQS_STALL[17]	TCC_WRITE[17]	TCC_RW_REQ[18]	TCC_TOO_MANY_EA_WRREQS_STALL[18]	TCC_WRITE[18]	TCC_RW_REQ[19]	TCC_TOO_MANY_EA_WRREQS_STALL[19]	TCC_WRITE[19]	TCC_RW_REQ[20]	TCC_TOO_MANY_EA_WRREQS_STALL[20]	TCC_WRITE[20]	TCC_RW_REQ[21]	TCC_TOO_MANY_EA_WRREQS_STALL[21]	TCC_WRITE[21]	TCC_RW_REQ[22]	TCC_TOO_MANY_EA_WRREQS_STALL[22]	TCC_WRITE[22]	TCC_RW_REQ[23]	TCC_TOO_MANY_EA_WRREQS_STALL[23]	TCC_WRITE[23]	TCC_RW_REQ[24]	TCC_TOO_MANY_EA_WRREQS_STALL[24]	TCC_WRITE[24]	TCC_RW_REQ[25]	TCC_TOO_MANY_EA_WRREQS_STALL[25]	TCC_WRITE[25]	TCC_RW_REQ[26]	TCC_TOO_MANY_EA_WRREQS_STALL[26]	TCC_WRITE[26]	TCC_RW_REQ[27]	TCC_TOO_MANY_EA_WRREQS_STALL[27]	TCC_WRITE[27]	TCC_RW_REQ[28]	TCC_TOO_MANY_EA_WRREQS_STALL[28]	TCC_WRITE[28]	TCC_RW_REQ[29]	TCC_TOO_MANY_EA_WRREQS_STALL[29]	TCC_WRITE[29]	TCC_RW_REQ[30]	TCC_TOO_MANY_EA_WRREQS_STALL[30]	TCC_WRITE[30]	TCC_RW_REQ[31]	TCC_TOO_MANY_EA_WRREQS_STALL[31]	TCC_WRITE[31]	SQC_DCACHE_INPUT_VALID_READYB	SQC_DCACHE_ATOMIC	SQC_DCACHE_REQ_READ_8	SQC_DCACHE_REQ	SQC_DCACHE_HITS	SQC_DCACHE_MISSES	SQC_DCACHE_MISSES_DUPLICATE	SQC_DCACHE_REQ_READ_1	TCP_VOLATILE_sum	TCP_TOTAL_ACCESSES_sum	TCP_TOTAL_READ_sum	TCP_TOTAL_WRITE_sum	TA_SH_FIFO_DATA_BUSY_sum	TA_SH_FIFO_DATA_SFIFO_BUSY_sum	TD_ATOMIC_WAVEFRONT_sum	TD_STORE_WAVEFRONT_sum	SPI_RA_REQ_NO_ALLOC	SPI_RA_REQ_NO_ALLOC_CSN	CPC_CPC_STAT_STALL	CPC_UTCL1_STALL_ON_TRANSLATION	CPF_CPF_STAT_IDLE	CPF_CPF_TCIU_IDLE	TCC_REQ_sum	TCC_STREAMING_REQ_sum	TCC_HIT_sum	TCC_MISS_sum	SQC_DCACHE_REQ_READ_2	SQC_DCACHE_REQ_READ_4	SQ_INSTS_VALU_CVT	SQ_INSTS_VMEM_WR	SQ_INSTS_VMEM_RD	SQ_INSTS_VMEM	SQ_INSTS_SALU	SQ_INSTS_VSKIPPED	TCP_TOTAL_ATOMIC_WITH_RET_sum	TCP_TOTAL_ATOMIC_WITHOUT_RET_sum	TCP_TOTAL_WRITEBACK_INVALIDATES_sum	TCP_TOTAL_CACHE_ACCESSES_sum	TA_SH_FIFO_DATA_TFIFO_BUSY_sum	TA_SQ_TA_CMD_CYCLES_sum	TD_COALESCABLE_WAVEFRONT_sum	SPI_RA_RES_STALL_CSN	SPI_RA_TMP_STALL_CSN	CPC_CPC_UTCL2IU_BUSY	CPC_CPC_UTCL2IU_IDLE	CPF_CMP_UTCL1_STALL_ON_TRANSLATION	TCC_READ_sum	TCC_WRITE_sum	TCC_ATOMIC_sum	TCC_WRITEBACK_sum	SQ_INSTS	SQ_INSTS_VALU	SQ_INSTS_VALU_ADD_F16	SQ_INSTS_VALU_MUL_F16	SQ_INSTS_VALU_FMA_F16	SQ_INSTS_VALU_TRANS_F16	SQ_INSTS_VALU_ADD_F32	SQ_INSTS_VALU_MUL_F32	TCP_UTCL1_TRANSLATION_MISS_sum	TCP_UTCL1_TRANSLATION_HIT_sum	TCP_UTCL1_PERMISSION_MISS_sum	TCP_UTCL1_REQUEST_sum	TA_SP_TA_ADDR_CYCLES_sum	TA_SP_TA_DATA_CYCLES_sum	SPI_RA_WAVE_SIMD_FULL_CSN	SPI_RA_VGPR_SIMD_FULL_CSN	CPC_CPC_UTCL2IU_STALL	CPC_ME1_BUSY_FOR_PACKET_DECODE	TCC_EA_WRREQ_sum	TCC_EA_WRREQ_64B_sum	TCC_EA_WR_UNCACHED_32B_sum	TCC_EA_WRREQ_STALL_sum	SQ_INSTS_VALU_FMA_F32	SQ_INSTS_VALU_TRANS_F32	SQ_INSTS_VALU_ADD_F64	SQ_INSTS_VALU_MUL_F64	SQ_INSTS_VALU_FMA_F64	SQ_INSTS_VALU_TRANS_F64	SQ_INSTS_VALU_INT32	SQ_INSTS_VALU_INT64	TCP_TCP_LATENCY_sum	TCP_TCC_READ_REQ_LATENCY_sum	TCP_TCC_WRITE_REQ_LATENCY_sum	TCP_TCC_READ_REQ_sum	TA_SH_FIFO_ADDR_STARVED_WHILE_BUSY_CYCLES_sum	TA_SH_FIFO_CMD_STARVED_WHILE_BUSY_CYCLES_sum	SPI_RA_SGPR_SIMD_FULL_CSN	SPI_RA_LDS_CU_FULL_CSN	CPC_ME1_DC0_SPI_BUSY	TCC_EA_WRREQ_IO_CREDIT_STALL_sum	TCC_EA_WRREQ_GMI_CREDIT_STALL_sum	TCC_EA_WRREQ_DRAM_CREDIT_STALL_sum	TCC_TOO_MANY_EA_WRREQS_STALL_sum	SQ_INSTS_SMEM	SQ_INSTS_FLAT	SQ_INSTS_LDS	SQ_INSTS_GDS	SQ_INSTS_EXP_GDS	SQ_INSTS_BRANCH	SQ_INSTS_SENDMSG	SQ_WAIT_ANY	TCP_TCC_WRITE_REQ_sum	TCP_TCC_ATOMIC_WITH_RET_REQ_sum	TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum	TCP_TCC_NC_READ_REQ_sum	TA_SH_FIFO_DATA_STARVED_WHILE_BUSY_CYCLES_sum	TA_TA_SH_FIFO_STARVED_sum	SPI_RA_BAR_CU_FULL_CSN	SPI_RA_TGLIM_CU_FULL_CSN	TCC_EA_ATOMIC_sum	TCC_EA_RDREQ_sum	TCC_EA_RDREQ_32B_sum	TCC_EA_RD_UNCACHED_32B_sum	SQ_WAIT_INST_ANY	SQ_ACTIVE_INST_ANY	SQ_ACTIVE_INST_VMEM	SQ_ACTIVE_INST_LDS	SQ_ACTIVE_INST_VALU	SQ_ACTIVE_INST_SCA	SQ_ACTIVE_INST_EXP_GDS	SQ_ACTIVE_INST_MISC	TCP_TCC_NC_WRITE_REQ_sum	TCP_TCC_NC_ATOMIC_REQ_sum	TCP_TCC_UC_READ_REQ_sum	TCP_TCC_UC_WRITE_REQ_sum	TA_BUFFER_WAVEFRONTS_sum	TA_BUFFER_READ_WAVEFRONTS_sum	SPI_RA_WVLIM_STALL_CSN	SPI_SWC_CSC_WR	TCC_EA_RDREQ_IO_CREDIT_STALL_sum	TCC_EA_RDREQ_GMI_CREDIT_STALL_sum	TCC_EA_RDREQ_DRAM_CREDIT_STALL_sum	TCC_TAG_STALL_sum	SQ_ACTIVE_INST_FLAT	SQ_INST_CYCLES_VMEM_WR	SQ_INST_CYCLES_VMEM_RD	SQ_INST_CYCLES_SMEM	SQ_INST_CYCLES_SALU	SQ_THREAD_CYCLES_VALU	SQ_IFETCH	SQ_LDS_BANK_CONFLICT	TCP_TCC_UC_ATOMIC_REQ_sum	TCP_TCC_CC_READ_REQ_sum	TCP_TCC_CC_WRITE_REQ_sum	TCP_TCC_CC_ATOMIC_REQ_sum	TA_BUFFER_WRITE_WAVEFRONTS_sum	TA_BUFFER_ATOMIC_WAVEFRONTS_sum	SPI_VWC_CSC_WR	SPI_RA_BULKY_CU_FULL_CSN	TCC_NORMAL_WRITEBACK_sum	TCC_ALL_TC_OP_WB_WRITEBACK_sum	TCC_NORMAL_EVICT_sum	TCC_ALL_TC_OP_INV_EVICT_sum	SQ_LDS_ADDR_CONFLICT	SQ_LDS_UNALIGNED_STALL	SQ_WAVES_EQ_64	SQ_WAVES_LT_64	SQ_WAVES_LT_48	SQ_WAVES_LT_32	SQ_WAVES_LT_16	SQ_ITEMS	TCP_TCC_RW_READ_REQ_sum	TCP_TCC_RW_WRITE_REQ_sum	TCP_TCC_RW_ATOMIC_REQ_sum	TCP_PENDING_STALL_CYCLES_sum	TA_BUFFER_TOTAL_CYCLES_sum	TA_BUFFER_COALESCABLE_WAVEFRONTS_sum	TCC_EA_RDREQ_DRAM_sum	TCC_EA_WRREQ_DRAM_sum	TCC_EA_RDREQ_LEVEL_sum	TCC_EA_WRREQ_LEVEL_sum	DispatchNs	BeginNs	EndNs	CompleteNs
2	0	__amd_rocclr_fillBufferAligned.kd	0	0	0	122412	122412	33554432	256	0	0	4	32	4160	0x0	0x7f51ad004280	3079536	2990885	524288	38855509	242806577	392	224	0	384941	384941	39123349.0	38188949.0	0.0	4185973.0	31287821.0	30923614.0	38161839.0	37600396.0	3077825	2997287	384941	0	384941	0	12318112.0	9476961.0	0.0	0.0	0	0	616	0	4718592	4714940	112	3540	375370	0.0	0.0	0.0	524288.0	28433996.0	27709423.0	7737.0	524288.0	131072	524288	302	384556	2301	0	56.0	302.0	0.0	4194696.0	0	0	0	0	0	7340032	0	0	0.0	0.0	0.0	0	0	0	0	0	0	0	0	20118996.0	524288.0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	385167	0	0	0	0	0	0.0	20571325.0	32	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	38	0	0	0	0	0	0	0	57	0	0	0	0	0	0	0	4	0	0	0	0	0	0	0	112	0	0	0	0	0	0	0	0	0	0	0	32	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	524288.0	0.0	0	0	129024	129024	0	0	129024	129024	0	27938	129024	129024	0	0	129024	129024	0	333	129024	129024	0	198	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	45606	129024	129024	0	0	129024	129024	0	857	129024	129024	0	499681	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	178	129024	129024	0	324136	129024	129024	0	0	129024	129024	0	879	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	0	129024	129024	0	177	129024	129024	0	0	129024	129024	0	44361	129024	129024	0	0	129024	129024	0	184	129024	129024	524288.0	0.0	44702	0	0	50595208	44461	0	0	50527231	43204	0	0	49691291	45847	0	0	51454259	44297	0	0	51004366	45798	0	0	51423974	44969	0	0	50856202	47949	0	0	52847255	45413	0	0	50832277	46042	0	0	51004325	45188	0	0	50569804	47805	0	0	52251698	44364	0	0	51124656	47693	0	0	51801218	46382	0	0	51345117	48951	0	0	53034810	44143	0	0	50577621	46206	0	0	50828775	42748	0	0	49806759	45713	0	0	51636516	44518	0	0	50999422	45647	0	0	51195141	45341	0	0	50943923	46659	0	0	52695848	45467	0	0	50751157	46280	0	0	50997663	46040	0	0	50669113	48102	0	0	52315468	45604	0	0	51504898	47175	0	0	51823318	46222	0	0	51249056	48307	0	0	52943730	0.0	65536	65568	32	131104	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65646	65538	112	131184	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65536	65568	32	131104	65536	65592	56	131128	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65536	65539	3	131075	65536	65536	0	131072	65536	65648	112	131184	65536	65536	0	131072	65591	65570	89	131161	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65758	65538	224	131296	65536	65537	1	131073	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65536	65568	32	131104	65536	65536	0	131072	65536	65536	0	131072	65536	65536	0	131072	65591	65537	56	131128	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131184	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131296	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131072	0	131072	131128	0	131072	1068133	0	524288	3670016	3663319	224	6473	1048576	33554432.0	33554432.0	0.0	33554432.0	30353415.0	28710885.0	0.0	524288.0	220590	538923	8565	949	0	384873	4195054.0	0.0	2097594.0	2097460.0	1048576	1048576	0	524288	0	524288	7340032	0	0.0	0.0	104.0	8388608.0	29728300.0	2097152.0	0.0	213405	0	1206	387145	0	749.0	4194304.0	0.0	2064387.0	25690112	9437184	0	0	0	0	0	0	13291.0	8242407.0	0.0	8388608.0	2097152.0	4194304.0	9833881	0	0	8974	4128768.0	4128768.0	0.0	1484433.0	0	0	0	0	0	0	5767168	1048576	316467378.0	0.0	1473905488.0	0.0	46.0	0.0	0	0	374361	0.0	0.0	1486125.0	0.0	3670016	524288	0	0	0	2621440	524288	176728168	4194304.0	0.0	0.0	0.0	0.0	1210498.0	0	0	0.0	309.0	0.0	602.0	41918949	24117248	0	0	9437184	11010048	0	3145728	0.0	0.0	0.0	0.0	0.0	0.0	0	1572864	0.0	0.0	0.0	196770.0	524288	524288	0	3670016	7340032	603979776	4718592	0	0.0	0.0	0.0	0.0	0.0	0.0	524288	0	2064384.0	0.0	2031623.0	0.0	0	0	524288	0	0	0	0	33554432	0.0	4194304.0	0.0	18913192.0	0.0	0.0	142.0	4128768.0	1009826.0	1693248639.0	15624327812666	15637372446181	15637372686822	15624471348034