Tony Gutierrez
6e3c375bf1
This builds on a prior change that allowed for allocating a user-mode queue's packet buffer in device memory to also allocate the queue struct in device memory. This provides additional latency benefits particularly for cases where dispatches are performed from the GPU itself. Flags are added to support the various use cases.
103 строки
4.0 KiB
C++
103 строки
4.0 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "core/inc/host_queue.h"
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#include "core/inc/runtime.h"
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#include "core/util/utils.h"
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namespace rocr {
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namespace core {
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HostQueue::HostQueue(core::SharedQueue* shared_queue, hsa_region_t region, uint32_t ring_size,
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hsa_queue_type32_t type, uint32_t features, hsa_signal_t doorbell_signal)
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: Queue(shared_queue, 0), size_(ring_size) {
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HSA::hsa_memory_register(this, sizeof(HostQueue));
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MAKE_NAMED_SCOPE_GUARD(registerGuard,
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[&]() { HSA::hsa_memory_deregister(this, sizeof(HostQueue)); });
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const size_t queue_buffer_size = size_ * sizeof(AqlPacket);
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if (HSA_STATUS_SUCCESS !=
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HSA::hsa_memory_allocate(region, queue_buffer_size, &ring_)) {
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throw AMD::hsa_exception(HSA_STATUS_ERROR_OUT_OF_RESOURCES, "Host queue buffer alloc failed\n");
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}
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MAKE_NAMED_SCOPE_GUARD(bufferGuard, [&]() { HSA::hsa_memory_free(&ring_); });
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assert(IsMultipleOf(ring_, kRingAlignment));
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assert(ring_ != NULL);
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// Fill the ring buffer with invalid packet headers.
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// Leave packet content uninitialized to help track errors.
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for (uint32_t pkt_id = 0; pkt_id < size_; pkt_id++) {
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(((AqlPacket*)ring_)[pkt_id]).dispatch.header = HSA_PACKET_TYPE_INVALID;
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}
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amd_queue_.hsa_queue.base_address = ring_;
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amd_queue_.hsa_queue.size = size_;
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amd_queue_.hsa_queue.doorbell_signal = doorbell_signal;
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amd_queue_.hsa_queue.id = this->GetQueueId();
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amd_queue_.hsa_queue.type = type;
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amd_queue_.hsa_queue.features = features;
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#ifdef HSA_LARGE_MODEL
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AMD_HSA_BITS_SET(
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amd_queue_.queue_properties, AMD_QUEUE_PROPERTIES_IS_PTR64, 1);
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#else
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AMD_HSA_BITS_SET(
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amd_queue_.queue_properties, AMD_QUEUE_PROPERTIES_IS_PTR64, 0);
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#endif
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amd_queue_.write_dispatch_id = amd_queue_.read_dispatch_id = 0;
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AMD_HSA_BITS_SET(
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amd_queue_.queue_properties, AMD_QUEUE_PROPERTIES_ENABLE_PROFILING, 0);
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bufferGuard.Dismiss();
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registerGuard.Dismiss();
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}
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HostQueue::~HostQueue() {
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HSA::hsa_memory_free(shared_queue_);
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HSA::hsa_memory_free(ring_);
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HSA::hsa_memory_deregister(this, sizeof(HostQueue));
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}
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} // namespace core
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} // namespace rocr
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