Jose Santos
34 KiB
34 KiB
| 1 | Dispatch_ID | Kernel_Name | GPU_ID | Grid_Size | Workgroup_Size | LDS_Per_Workgroup | Scratch_Per_Workitem | Arch_VGPR | Accum_VGPR | SGPR | wave_size | obj | TCC_EA_WRREQ_DRAM_CREDIT_STALL[0] | TCC_EA_WRREQ_GMI_CREDIT_STALL[0] | TCC_EA_WRREQ_IO_CREDIT_STALL[0] | TCC_EA_WRREQ_LEVEL[0] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[1] | TCC_EA_WRREQ_GMI_CREDIT_STALL[1] | TCC_EA_WRREQ_IO_CREDIT_STALL[1] | TCC_EA_WRREQ_LEVEL[1] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[2] | TCC_EA_WRREQ_GMI_CREDIT_STALL[2] | TCC_EA_WRREQ_IO_CREDIT_STALL[2] | TCC_EA_WRREQ_LEVEL[2] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[3] | TCC_EA_WRREQ_GMI_CREDIT_STALL[3] | TCC_EA_WRREQ_IO_CREDIT_STALL[3] | TCC_EA_WRREQ_LEVEL[3] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[4] | TCC_EA_WRREQ_GMI_CREDIT_STALL[4] | TCC_EA_WRREQ_IO_CREDIT_STALL[4] | TCC_EA_WRREQ_LEVEL[4] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[5] | TCC_EA_WRREQ_GMI_CREDIT_STALL[5] | TCC_EA_WRREQ_IO_CREDIT_STALL[5] | TCC_EA_WRREQ_LEVEL[5] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[6] | TCC_EA_WRREQ_GMI_CREDIT_STALL[6] | TCC_EA_WRREQ_IO_CREDIT_STALL[6] | TCC_EA_WRREQ_LEVEL[6] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[7] | TCC_EA_WRREQ_GMI_CREDIT_STALL[7] | TCC_EA_WRREQ_IO_CREDIT_STALL[7] | TCC_EA_WRREQ_LEVEL[7] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[8] | TCC_EA_WRREQ_GMI_CREDIT_STALL[8] | TCC_EA_WRREQ_IO_CREDIT_STALL[8] | TCC_EA_WRREQ_LEVEL[8] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[9] | TCC_EA_WRREQ_GMI_CREDIT_STALL[9] | TCC_EA_WRREQ_IO_CREDIT_STALL[9] | TCC_EA_WRREQ_LEVEL[9] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[10] | TCC_EA_WRREQ_GMI_CREDIT_STALL[10] | TCC_EA_WRREQ_IO_CREDIT_STALL[10] | TCC_EA_WRREQ_LEVEL[10] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[11] | TCC_EA_WRREQ_GMI_CREDIT_STALL[11] | TCC_EA_WRREQ_IO_CREDIT_STALL[11] | TCC_EA_WRREQ_LEVEL[11] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[12] | TCC_EA_WRREQ_GMI_CREDIT_STALL[12] | TCC_EA_WRREQ_IO_CREDIT_STALL[12] | TCC_EA_WRREQ_LEVEL[12] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[13] | TCC_EA_WRREQ_GMI_CREDIT_STALL[13] | TCC_EA_WRREQ_IO_CREDIT_STALL[13] | TCC_EA_WRREQ_LEVEL[13] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[14] | TCC_EA_WRREQ_GMI_CREDIT_STALL[14] | TCC_EA_WRREQ_IO_CREDIT_STALL[14] | TCC_EA_WRREQ_LEVEL[14] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[15] | TCC_EA_WRREQ_GMI_CREDIT_STALL[15] | TCC_EA_WRREQ_IO_CREDIT_STALL[15] | TCC_EA_WRREQ_LEVEL[15] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[16] | TCC_EA_WRREQ_GMI_CREDIT_STALL[16] | TCC_EA_WRREQ_IO_CREDIT_STALL[16] | TCC_EA_WRREQ_LEVEL[16] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[17] | TCC_EA_WRREQ_GMI_CREDIT_STALL[17] | TCC_EA_WRREQ_IO_CREDIT_STALL[17] | TCC_EA_WRREQ_LEVEL[17] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[18] | TCC_EA_WRREQ_GMI_CREDIT_STALL[18] | TCC_EA_WRREQ_IO_CREDIT_STALL[18] | TCC_EA_WRREQ_LEVEL[18] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[19] | TCC_EA_WRREQ_GMI_CREDIT_STALL[19] | TCC_EA_WRREQ_IO_CREDIT_STALL[19] | TCC_EA_WRREQ_LEVEL[19] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[20] | TCC_EA_WRREQ_GMI_CREDIT_STALL[20] | TCC_EA_WRREQ_IO_CREDIT_STALL[20] | TCC_EA_WRREQ_LEVEL[20] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[21] | TCC_EA_WRREQ_GMI_CREDIT_STALL[21] | TCC_EA_WRREQ_IO_CREDIT_STALL[21] | TCC_EA_WRREQ_LEVEL[21] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[22] | TCC_EA_WRREQ_GMI_CREDIT_STALL[22] | TCC_EA_WRREQ_IO_CREDIT_STALL[22] | TCC_EA_WRREQ_LEVEL[22] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[23] | TCC_EA_WRREQ_GMI_CREDIT_STALL[23] | TCC_EA_WRREQ_IO_CREDIT_STALL[23] | TCC_EA_WRREQ_LEVEL[23] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[24] | TCC_EA_WRREQ_GMI_CREDIT_STALL[24] | TCC_EA_WRREQ_IO_CREDIT_STALL[24] | TCC_EA_WRREQ_LEVEL[24] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[25] | TCC_EA_WRREQ_GMI_CREDIT_STALL[25] | TCC_EA_WRREQ_IO_CREDIT_STALL[25] | TCC_EA_WRREQ_LEVEL[25] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[26] | TCC_EA_WRREQ_GMI_CREDIT_STALL[26] | TCC_EA_WRREQ_IO_CREDIT_STALL[26] | TCC_EA_WRREQ_LEVEL[26] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[27] | TCC_EA_WRREQ_GMI_CREDIT_STALL[27] | TCC_EA_WRREQ_IO_CREDIT_STALL[27] | TCC_EA_WRREQ_LEVEL[27] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[28] | TCC_EA_WRREQ_GMI_CREDIT_STALL[28] | TCC_EA_WRREQ_IO_CREDIT_STALL[28] | TCC_EA_WRREQ_LEVEL[28] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[29] | TCC_EA_WRREQ_GMI_CREDIT_STALL[29] | TCC_EA_WRREQ_IO_CREDIT_STALL[29] | TCC_EA_WRREQ_LEVEL[29] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[30] | TCC_EA_WRREQ_GMI_CREDIT_STALL[30] | TCC_EA_WRREQ_IO_CREDIT_STALL[30] | TCC_EA_WRREQ_LEVEL[30] | TCC_EA_WRREQ_DRAM_CREDIT_STALL[31] | TCC_EA_WRREQ_GMI_CREDIT_STALL[31] | TCC_EA_WRREQ_IO_CREDIT_STALL[31] | TCC_EA_WRREQ_LEVEL[31] | wave_size_1 | obj_1 | SQ_INSTS_FLAT_LDS_ONLY | SQ_INSTS_VALU_MFMA_MOPS_I8 | SQ_INSTS_VALU_MFMA_MOPS_F16 | SQ_INSTS_VALU_MFMA_MOPS_BF16 | SQ_INSTS_VALU_MFMA_MOPS_F32 | SQ_INSTS_VALU_MFMA_MOPS_F64 | SQC_TC_INST_REQ | SQC_TC_DATA_READ_REQ | TCP_TCC_RW_READ_REQ_sum | TCP_TCC_RW_WRITE_REQ_sum | TCP_TCC_RW_ATOMIC_REQ_sum | TCP_PENDING_STALL_CYCLES_sum | wave_size_2 | obj_2 | SQ_CYCLES | SQ_BUSY_CYCLES | SQ_WAVES | SQ_INSTS_VALU_CVT | SQ_INSTS_VMEM_WR | SQ_INSTS_VMEM_RD | SQ_INSTS_VMEM | SQ_INSTS_SALU | GRBM_COUNT | GRBM_GUI_ACTIVE | TCP_GATE_EN1_sum | TCP_GATE_EN2_sum | TCP_TD_TCP_STALL_CYCLES_sum | TCP_TCR_TCP_STALL_CYCLES_sum | TA_TA_BUSY_sum | TA_BUFFER_WAVEFRONTS_sum | TD_TD_BUSY_sum | TD_TC_STALL_sum | SPI_CSN_WINDOW_VALID | SPI_CSN_BUSY | CPC_CPC_STAT_BUSY | CPC_CPC_STAT_IDLE | CPF_CPF_STAT_BUSY | CPF_CPF_STAT_STALL | TCC_CYCLE_sum | TCC_BUSY_sum | TCC_PROBE_sum | TCC_PROBE_ALL_sum | wave_size_3 | obj_3 | SQ_INSTS_VSKIPPED | SQ_INSTS | SQ_INSTS_VALU | SQ_INSTS_VALU_ADD_F16 | SQ_INSTS_VALU_MUL_F16 | SQ_INSTS_VALU_FMA_F16 | SQ_INSTS_VALU_TRANS_F16 | SQ_INSTS_VALU_ADD_F32 | GRBM_SPI_BUSY | TCP_READ_TAGCONFLICT_STALL_CYCLES_sum | TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum | TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum | TCP_TA_TCP_STATE_READ_sum | TA_BUFFER_READ_WAVEFRONTS_sum | TA_BUFFER_WRITE_WAVEFRONTS_sum | TD_SPI_STALL_sum | TD_LOAD_WAVEFRONT_sum | SPI_CSN_NUM_THREADGROUPS | SPI_CSN_WAVE | CPC_CPC_TCIU_BUSY | CPC_CPC_TCIU_IDLE | CPF_CPF_TCIU_BUSY | CPF_CPF_TCIU_STALL | TCC_NC_REQ_sum | TCC_UC_REQ_sum | TCC_CC_REQ_sum | TCC_RW_REQ_sum | wave_size_4 | obj_4 | TCC_EA_RDREQ_IO_CREDIT_STALL[0] | TCC_EA_RDREQ_LEVEL[0] | TCC_EA_WRREQ[0] | TCC_EA_WRREQ_64B[0] | TCC_EA_RDREQ_IO_CREDIT_STALL[1] | TCC_EA_RDREQ_LEVEL[1] | TCC_EA_WRREQ[1] | TCC_EA_WRREQ_64B[1] | TCC_EA_RDREQ_IO_CREDIT_STALL[2] | TCC_EA_RDREQ_LEVEL[2] | TCC_EA_WRREQ[2] | TCC_EA_WRREQ_64B[2] | TCC_EA_RDREQ_IO_CREDIT_STALL[3] | TCC_EA_RDREQ_LEVEL[3] | TCC_EA_WRREQ[3] | TCC_EA_WRREQ_64B[3] | TCC_EA_RDREQ_IO_CREDIT_STALL[4] | TCC_EA_RDREQ_LEVEL[4] | TCC_EA_WRREQ[4] | TCC_EA_WRREQ_64B[4] | TCC_EA_RDREQ_IO_CREDIT_STALL[5] | TCC_EA_RDREQ_LEVEL[5] | TCC_EA_WRREQ[5] | TCC_EA_WRREQ_64B[5] | TCC_EA_RDREQ_IO_CREDIT_STALL[6] | TCC_EA_RDREQ_LEVEL[6] | TCC_EA_WRREQ[6] | TCC_EA_WRREQ_64B[6] | TCC_EA_RDREQ_IO_CREDIT_STALL[7] | TCC_EA_RDREQ_LEVEL[7] | TCC_EA_WRREQ[7] | TCC_EA_WRREQ_64B[7] | TCC_EA_RDREQ_IO_CREDIT_STALL[8] | TCC_EA_RDREQ_LEVEL[8] | TCC_EA_WRREQ[8] | TCC_EA_WRREQ_64B[8] | TCC_EA_RDREQ_IO_CREDIT_STALL[9] | TCC_EA_RDREQ_LEVEL[9] | TCC_EA_WRREQ[9] | TCC_EA_WRREQ_64B[9] | TCC_EA_RDREQ_IO_CREDIT_STALL[10] | TCC_EA_RDREQ_LEVEL[10] | TCC_EA_WRREQ[10] | TCC_EA_WRREQ_64B[10] | TCC_EA_RDREQ_IO_CREDIT_STALL[11] | TCC_EA_RDREQ_LEVEL[11] | TCC_EA_WRREQ[11] | TCC_EA_WRREQ_64B[11] | TCC_EA_RDREQ_IO_CREDIT_STALL[12] | TCC_EA_RDREQ_LEVEL[12] | TCC_EA_WRREQ[12] | TCC_EA_WRREQ_64B[12] | TCC_EA_RDREQ_IO_CREDIT_STALL[13] | TCC_EA_RDREQ_LEVEL[13] | TCC_EA_WRREQ[13] | TCC_EA_WRREQ_64B[13] | TCC_EA_RDREQ_IO_CREDIT_STALL[14] | TCC_EA_RDREQ_LEVEL[14] | TCC_EA_WRREQ[14] | TCC_EA_WRREQ_64B[14] | TCC_EA_RDREQ_IO_CREDIT_STALL[15] | TCC_EA_RDREQ_LEVEL[15] | TCC_EA_WRREQ[15] | TCC_EA_WRREQ_64B[15] | TCC_EA_RDREQ_IO_CREDIT_STALL[16] | TCC_EA_RDREQ_LEVEL[16] | TCC_EA_WRREQ[16] | TCC_EA_WRREQ_64B[16] | TCC_EA_RDREQ_IO_CREDIT_STALL[17] | TCC_EA_RDREQ_LEVEL[17] | TCC_EA_WRREQ[17] | TCC_EA_WRREQ_64B[17] | TCC_EA_RDREQ_IO_CREDIT_STALL[18] | TCC_EA_RDREQ_LEVEL[18] | TCC_EA_WRREQ[18] | TCC_EA_WRREQ_64B[18] | TCC_EA_RDREQ_IO_CREDIT_STALL[19] | TCC_EA_RDREQ_LEVEL[19] | TCC_EA_WRREQ[19] | TCC_EA_WRREQ_64B[19] | TCC_EA_RDREQ_IO_CREDIT_STALL[20] | TCC_EA_RDREQ_LEVEL[20] | TCC_EA_WRREQ[20] | TCC_EA_WRREQ_64B[20] | TCC_EA_RDREQ_IO_CREDIT_STALL[21] | TCC_EA_RDREQ_LEVEL[21] | TCC_EA_WRREQ[21] | TCC_EA_WRREQ_64B[21] | TCC_EA_RDREQ_IO_CREDIT_STALL[22] | TCC_EA_RDREQ_LEVEL[22] | TCC_EA_WRREQ[22] | TCC_EA_WRREQ_64B[22] | TCC_EA_RDREQ_IO_CREDIT_STALL[23] | TCC_EA_RDREQ_LEVEL[23] | TCC_EA_WRREQ[23] | TCC_EA_WRREQ_64B[23] | TCC_EA_RDREQ_IO_CREDIT_STALL[24] | TCC_EA_RDREQ_LEVEL[24] | TCC_EA_WRREQ[24] | TCC_EA_WRREQ_64B[24] | TCC_EA_RDREQ_IO_CREDIT_STALL[25] | TCC_EA_RDREQ_LEVEL[25] | TCC_EA_WRREQ[25] | TCC_EA_WRREQ_64B[25] | TCC_EA_RDREQ_IO_CREDIT_STALL[26] | TCC_EA_RDREQ_LEVEL[26] | TCC_EA_WRREQ[26] | TCC_EA_WRREQ_64B[26] | TCC_EA_RDREQ_IO_CREDIT_STALL[27] | TCC_EA_RDREQ_LEVEL[27] | TCC_EA_WRREQ[27] | TCC_EA_WRREQ_64B[27] | TCC_EA_RDREQ_IO_CREDIT_STALL[28] | TCC_EA_RDREQ_LEVEL[28] | TCC_EA_WRREQ[28] | TCC_EA_WRREQ_64B[28] | TCC_EA_RDREQ_IO_CREDIT_STALL[29] | TCC_EA_RDREQ_LEVEL[29] | TCC_EA_WRREQ[29] | TCC_EA_WRREQ_64B[29] | TCC_EA_RDREQ_IO_CREDIT_STALL[30] | TCC_EA_RDREQ_LEVEL[30] | TCC_EA_WRREQ[30] | TCC_EA_WRREQ_64B[30] | TCC_EA_RDREQ_IO_CREDIT_STALL[31] | TCC_EA_RDREQ_LEVEL[31] | TCC_EA_WRREQ[31] | TCC_EA_WRREQ_64B[31] | wave_size_5 | obj_5 | SQ_INSTS_SMEM_NORM | SQ_INSTS_MFMA | SQ_INSTS_VALU_MFMA_I8 | SQ_INSTS_VALU_MFMA_F16 | SQ_INSTS_VALU_MFMA_BF16 | SQ_INSTS_VALU_MFMA_F32 | SQ_INSTS_VALU_MFMA_F64 | SQ_VALU_MFMA_BUSY_CYCLES | TCP_TCC_UC_ATOMIC_REQ_sum | TCP_TCC_CC_READ_REQ_sum | TCP_TCC_CC_WRITE_REQ_sum | TCP_TCC_CC_ATOMIC_REQ_sum | SPI_VWC_CSC_WR | SPI_RA_BULKY_CU_FULL_CSN | TCC_EA_RDREQ_LEVEL_sum | TCC_EA_WRREQ_LEVEL_sum | TCC_EA_ATOMIC_LEVEL_sum | wave_size_6 | obj_6 | SQ_ACTIVE_INST_SCA | SQ_ACTIVE_INST_EXP_GDS | SQ_ACTIVE_INST_MISC | SQ_ACTIVE_INST_FLAT | SQ_INST_CYCLES_VMEM_WR | SQ_INST_CYCLES_VMEM_RD | SQ_INST_CYCLES_SMEM | SQ_INST_CYCLES_SALU | TCP_TCP_LATENCY_sum | TCP_TCC_READ_REQ_LATENCY_sum | TCP_TCC_WRITE_REQ_LATENCY_sum | TCP_TCC_READ_REQ_sum | TA_ADDR_STALLED_BY_TD_CYCLES_sum | TA_DATA_STALLED_BY_TC_CYCLES_sum | SPI_RA_SGPR_SIMD_FULL_CSN | SPI_RA_LDS_CU_FULL_CSN | CPC_ME1_DC0_SPI_BUSY | TCC_EA_WRREQ_STALL_sum | TCC_EA_RDREQ_sum | TCC_EA_RDREQ_32B_sum | TCC_EA_RD_UNCACHED_32B_sum | wave_size_7 | obj_7 | SQ_INSTS_VALU_INT64 | SQ_INSTS_SMEM | SQ_INSTS_FLAT | SQ_INSTS_LDS | SQ_INSTS_GDS | SQ_INSTS_EXP_GDS | SQ_INSTS_BRANCH | SQ_INSTS_SENDMSG | TCP_TOTAL_ATOMIC_WITH_RET_sum | TCP_TOTAL_ATOMIC_WITHOUT_RET_sum | TCP_TOTAL_WRITEBACK_INVALIDATES_sum | TCP_TOTAL_CACHE_ACCESSES_sum | TA_BUFFER_COALESCED_READ_CYCLES_sum | TA_BUFFER_COALESCED_WRITE_CYCLES_sum | TD_COALESCABLE_WAVEFRONT_sum | SPI_RA_RES_STALL_CSN | SPI_RA_TMP_STALL_CSN | CPC_CPC_UTCL2IU_BUSY | CPC_CPC_UTCL2IU_IDLE | CPF_CMP_UTCL1_STALL_ON_TRANSLATION | TCC_READ_sum | TCC_WRITE_sum | TCC_ATOMIC_sum | TCC_WRITEBACK_sum | wave_size_8 | obj_8 | TCC_ATOMIC[0] | TCC_CYCLE[0] | TCC_EA_ATOMIC[0] | TCC_EA_ATOMIC_LEVEL[0] | TCC_ATOMIC[1] | TCC_CYCLE[1] | TCC_EA_ATOMIC[1] | TCC_EA_ATOMIC_LEVEL[1] | TCC_ATOMIC[2] | TCC_CYCLE[2] | TCC_EA_ATOMIC[2] | TCC_EA_ATOMIC_LEVEL[2] | TCC_ATOMIC[3] | TCC_CYCLE[3] | TCC_EA_ATOMIC[3] | TCC_EA_ATOMIC_LEVEL[3] | TCC_ATOMIC[4] | TCC_CYCLE[4] | TCC_EA_ATOMIC[4] | TCC_EA_ATOMIC_LEVEL[4] | TCC_ATOMIC[5] | TCC_CYCLE[5] | TCC_EA_ATOMIC[5] | TCC_EA_ATOMIC_LEVEL[5] | TCC_ATOMIC[6] | TCC_CYCLE[6] | TCC_EA_ATOMIC[6] | TCC_EA_ATOMIC_LEVEL[6] | TCC_ATOMIC[7] | TCC_CYCLE[7] | TCC_EA_ATOMIC[7] | TCC_EA_ATOMIC_LEVEL[7] | TCC_ATOMIC[8] | TCC_CYCLE[8] | TCC_EA_ATOMIC[8] | TCC_EA_ATOMIC_LEVEL[8] | TCC_ATOMIC[9] | TCC_CYCLE[9] | TCC_EA_ATOMIC[9] | TCC_EA_ATOMIC_LEVEL[9] | TCC_ATOMIC[10] | TCC_CYCLE[10] | TCC_EA_ATOMIC[10] | TCC_EA_ATOMIC_LEVEL[10] | TCC_ATOMIC[11] | TCC_CYCLE[11] | TCC_EA_ATOMIC[11] | TCC_EA_ATOMIC_LEVEL[11] | TCC_ATOMIC[12] | TCC_CYCLE[12] | TCC_EA_ATOMIC[12] | TCC_EA_ATOMIC_LEVEL[12] | TCC_ATOMIC[13] | TCC_CYCLE[13] | TCC_EA_ATOMIC[13] | TCC_EA_ATOMIC_LEVEL[13] | TCC_ATOMIC[14] | TCC_CYCLE[14] | TCC_EA_ATOMIC[14] | TCC_EA_ATOMIC_LEVEL[14] | TCC_ATOMIC[15] | TCC_CYCLE[15] | TCC_EA_ATOMIC[15] | TCC_EA_ATOMIC_LEVEL[15] | TCC_ATOMIC[16] | TCC_CYCLE[16] | TCC_EA_ATOMIC[16] | TCC_EA_ATOMIC_LEVEL[16] | TCC_ATOMIC[17] | TCC_CYCLE[17] | TCC_EA_ATOMIC[17] | TCC_EA_ATOMIC_LEVEL[17] | TCC_ATOMIC[18] | TCC_CYCLE[18] | TCC_EA_ATOMIC[18] | TCC_EA_ATOMIC_LEVEL[18] | TCC_ATOMIC[19] | TCC_CYCLE[19] | TCC_EA_ATOMIC[19] | TCC_EA_ATOMIC_LEVEL[19] | TCC_ATOMIC[20] | TCC_CYCLE[20] | TCC_EA_ATOMIC[20] | TCC_EA_ATOMIC_LEVEL[20] | TCC_ATOMIC[21] | TCC_CYCLE[21] | TCC_EA_ATOMIC[21] | TCC_EA_ATOMIC_LEVEL[21] | TCC_ATOMIC[22] | TCC_CYCLE[22] | TCC_EA_ATOMIC[22] | TCC_EA_ATOMIC_LEVEL[22] | TCC_ATOMIC[23] | TCC_CYCLE[23] | TCC_EA_ATOMIC[23] | TCC_EA_ATOMIC_LEVEL[23] | TCC_ATOMIC[24] | TCC_CYCLE[24] | TCC_EA_ATOMIC[24] | TCC_EA_ATOMIC_LEVEL[24] | TCC_ATOMIC[25] | TCC_CYCLE[25] | TCC_EA_ATOMIC[25] | TCC_EA_ATOMIC_LEVEL[25] | TCC_ATOMIC[26] | TCC_CYCLE[26] | TCC_EA_ATOMIC[26] | TCC_EA_ATOMIC_LEVEL[26] | TCC_ATOMIC[27] | TCC_CYCLE[27] | TCC_EA_ATOMIC[27] | TCC_EA_ATOMIC_LEVEL[27] | TCC_ATOMIC[28] | TCC_CYCLE[28] | TCC_EA_ATOMIC[28] | TCC_EA_ATOMIC_LEVEL[28] | TCC_ATOMIC[29] | TCC_CYCLE[29] | TCC_EA_ATOMIC[29] | TCC_EA_ATOMIC_LEVEL[29] | TCC_ATOMIC[30] | TCC_CYCLE[30] | TCC_EA_ATOMIC[30] | TCC_EA_ATOMIC_LEVEL[30] | TCC_ATOMIC[31] | TCC_CYCLE[31] | TCC_EA_ATOMIC[31] | TCC_EA_ATOMIC_LEVEL[31] | wave_size_9 | obj_9 | SQ_INSTS_VALU_MUL_F32 | SQ_INSTS_VALU_FMA_F32 | SQ_INSTS_VALU_TRANS_F32 | SQ_INSTS_VALU_ADD_F64 | SQ_INSTS_VALU_MUL_F64 | SQ_INSTS_VALU_FMA_F64 | SQ_INSTS_VALU_TRANS_F64 | SQ_INSTS_VALU_INT32 | TCP_VOLATILE_sum | TCP_TOTAL_ACCESSES_sum | TCP_TOTAL_READ_sum | TCP_TOTAL_WRITE_sum | TA_BUFFER_ATOMIC_WAVEFRONTS_sum | TA_BUFFER_TOTAL_CYCLES_sum | TD_ATOMIC_WAVEFRONT_sum | TD_STORE_WAVEFRONT_sum | SPI_RA_REQ_NO_ALLOC | SPI_RA_REQ_NO_ALLOC_CSN | CPC_CPC_STAT_STALL | CPC_UTCL1_STALL_ON_TRANSLATION | CPF_CPF_STAT_IDLE | CPF_CPF_TCIU_IDLE | TCC_REQ_sum | TCC_STREAMING_REQ_sum | TCC_HIT_sum | TCC_MISS_sum | wave_size_10 | obj_10 | SQC_TC_DATA_WRITE_REQ | SQC_TC_DATA_ATOMIC_REQ | SQC_TC_STALL | SQC_TC_REQ | SQC_DCACHE_REQ_READ_16 | SQC_ICACHE_REQ | SQC_ICACHE_HITS | SQC_ICACHE_MISSES | wave_size_11 | obj_11 | SQC_DCACHE_REQ_READ_1 | SQC_DCACHE_REQ_READ_2 | SQC_DCACHE_REQ_READ_4 | wave_size_12 | obj_12 | SQ_THREAD_CYCLES_VALU | SQ_IFETCH | SQ_LDS_BANK_CONFLICT | SQ_LDS_ADDR_CONFLICT | SQ_LDS_UNALIGNED_STALL | SQ_WAVES_EQ_64 | SQ_WAVES_LT_64 | SQ_WAVES_LT_48 | TCP_TCC_WRITE_REQ_sum | TCP_TCC_ATOMIC_WITH_RET_REQ_sum | TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum | TCP_TCC_NC_READ_REQ_sum | TA_FLAT_WAVEFRONTS_sum | TA_FLAT_READ_WAVEFRONTS_sum | SPI_RA_BAR_CU_FULL_CSN | SPI_RA_TGLIM_CU_FULL_CSN | TCC_EA_RDREQ_DRAM_sum | TCC_TAG_STALL_sum | TCC_NORMAL_WRITEBACK_sum | TCC_ALL_TC_OP_WB_WRITEBACK_sum | wave_size_13 | obj_13 | TCC_RW_REQ[0] | TCC_TOO_MANY_EA_WRREQS_STALL[0] | TCC_WRITE[0] | TCC_RW_REQ[1] | TCC_TOO_MANY_EA_WRREQS_STALL[1] | TCC_WRITE[1] | TCC_RW_REQ[2] | TCC_TOO_MANY_EA_WRREQS_STALL[2] | TCC_WRITE[2] | TCC_RW_REQ[3] | TCC_TOO_MANY_EA_WRREQS_STALL[3] | TCC_WRITE[3] | TCC_RW_REQ[4] | TCC_TOO_MANY_EA_WRREQS_STALL[4] | TCC_WRITE[4] | TCC_RW_REQ[5] | TCC_TOO_MANY_EA_WRREQS_STALL[5] | TCC_WRITE[5] | TCC_RW_REQ[6] | TCC_TOO_MANY_EA_WRREQS_STALL[6] | TCC_WRITE[6] | TCC_RW_REQ[7] | TCC_TOO_MANY_EA_WRREQS_STALL[7] | TCC_WRITE[7] | TCC_RW_REQ[8] | TCC_TOO_MANY_EA_WRREQS_STALL[8] | TCC_WRITE[8] | TCC_RW_REQ[9] | TCC_TOO_MANY_EA_WRREQS_STALL[9] | TCC_WRITE[9] | TCC_RW_REQ[10] | TCC_TOO_MANY_EA_WRREQS_STALL[10] | TCC_WRITE[10] | TCC_RW_REQ[11] | TCC_TOO_MANY_EA_WRREQS_STALL[11] | TCC_WRITE[11] | TCC_RW_REQ[12] | TCC_TOO_MANY_EA_WRREQS_STALL[12] | TCC_WRITE[12] | TCC_RW_REQ[13] | TCC_TOO_MANY_EA_WRREQS_STALL[13] | TCC_WRITE[13] | TCC_RW_REQ[14] | TCC_TOO_MANY_EA_WRREQS_STALL[14] | TCC_WRITE[14] | TCC_RW_REQ[15] | TCC_TOO_MANY_EA_WRREQS_STALL[15] | TCC_WRITE[15] | TCC_RW_REQ[16] | TCC_TOO_MANY_EA_WRREQS_STALL[16] | TCC_WRITE[16] | TCC_RW_REQ[17] | TCC_TOO_MANY_EA_WRREQS_STALL[17] | TCC_WRITE[17] | TCC_RW_REQ[18] | TCC_TOO_MANY_EA_WRREQS_STALL[18] | TCC_WRITE[18] | TCC_RW_REQ[19] | TCC_TOO_MANY_EA_WRREQS_STALL[19] | TCC_WRITE[19] | TCC_RW_REQ[20] | TCC_TOO_MANY_EA_WRREQS_STALL[20] | TCC_WRITE[20] | TCC_RW_REQ[21] | TCC_TOO_MANY_EA_WRREQS_STALL[21] | TCC_WRITE[21] | TCC_RW_REQ[22] | TCC_TOO_MANY_EA_WRREQS_STALL[22] | TCC_WRITE[22] | TCC_RW_REQ[23] | TCC_TOO_MANY_EA_WRREQS_STALL[23] | TCC_WRITE[23] | TCC_RW_REQ[24] | TCC_TOO_MANY_EA_WRREQS_STALL[24] | TCC_WRITE[24] | TCC_RW_REQ[25] | TCC_TOO_MANY_EA_WRREQS_STALL[25] | TCC_WRITE[25] | TCC_RW_REQ[26] | TCC_TOO_MANY_EA_WRREQS_STALL[26] | TCC_WRITE[26] | TCC_RW_REQ[27] | TCC_TOO_MANY_EA_WRREQS_STALL[27] | TCC_WRITE[27] | TCC_RW_REQ[28] | TCC_TOO_MANY_EA_WRREQS_STALL[28] | TCC_WRITE[28] | TCC_RW_REQ[29] | TCC_TOO_MANY_EA_WRREQS_STALL[29] | TCC_WRITE[29] | TCC_RW_REQ[30] | TCC_TOO_MANY_EA_WRREQS_STALL[30] | TCC_WRITE[30] | TCC_RW_REQ[31] | TCC_TOO_MANY_EA_WRREQS_STALL[31] | TCC_WRITE[31] | wave_size_14 | obj_14 | SQ_WAVES_LT_32 | SQ_WAVES_LT_16 | SQ_ITEMS | SQ_LDS_MEM_VIOLATIONS | SQ_LDS_ATOMIC_RETURN | SQ_LDS_IDX_ACTIVE | SQ_WAVES_RESTORED | SQ_WAVES_SAVED | TCP_TCC_NC_WRITE_REQ_sum | TCP_TCC_NC_ATOMIC_REQ_sum | TCP_TCC_UC_READ_REQ_sum | TCP_TCC_UC_WRITE_REQ_sum | TA_FLAT_WRITE_WAVEFRONTS_sum | TA_FLAT_ATOMIC_WAVEFRONTS_sum | SPI_RA_WVLIM_STALL_CSN | SPI_SWC_CSC_WR | TCC_NORMAL_EVICT_sum | TCC_ALL_TC_OP_INV_EVICT_sum | TCC_TOO_MANY_EA_WRREQS_STALL_sum | TCC_EA_ATOMIC_sum | wave_size_15 | obj_15 | TCC_EA_RDREQ[0] | TCC_EA_RDREQ_32B[0] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[0] | TCC_EA_RDREQ_GMI_CREDIT_STALL[0] | TCC_EA_RDREQ[1] | TCC_EA_RDREQ_32B[1] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[1] | TCC_EA_RDREQ_GMI_CREDIT_STALL[1] | TCC_EA_RDREQ[2] | TCC_EA_RDREQ_32B[2] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[2] | TCC_EA_RDREQ_GMI_CREDIT_STALL[2] | TCC_EA_RDREQ[3] | TCC_EA_RDREQ_32B[3] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[3] | TCC_EA_RDREQ_GMI_CREDIT_STALL[3] | TCC_EA_RDREQ[4] | TCC_EA_RDREQ_32B[4] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[4] | TCC_EA_RDREQ_GMI_CREDIT_STALL[4] | TCC_EA_RDREQ[5] | TCC_EA_RDREQ_32B[5] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[5] | TCC_EA_RDREQ_GMI_CREDIT_STALL[5] | TCC_EA_RDREQ[6] | TCC_EA_RDREQ_32B[6] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[6] | TCC_EA_RDREQ_GMI_CREDIT_STALL[6] | TCC_EA_RDREQ[7] | TCC_EA_RDREQ_32B[7] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[7] | TCC_EA_RDREQ_GMI_CREDIT_STALL[7] | TCC_EA_RDREQ[8] | TCC_EA_RDREQ_32B[8] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[8] | TCC_EA_RDREQ_GMI_CREDIT_STALL[8] | TCC_EA_RDREQ[9] | TCC_EA_RDREQ_32B[9] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[9] | TCC_EA_RDREQ_GMI_CREDIT_STALL[9] | TCC_EA_RDREQ[10] | TCC_EA_RDREQ_32B[10] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[10] | TCC_EA_RDREQ_GMI_CREDIT_STALL[10] | TCC_EA_RDREQ[11] | TCC_EA_RDREQ_32B[11] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[11] | TCC_EA_RDREQ_GMI_CREDIT_STALL[11] | TCC_EA_RDREQ[12] | TCC_EA_RDREQ_32B[12] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[12] | TCC_EA_RDREQ_GMI_CREDIT_STALL[12] | TCC_EA_RDREQ[13] | TCC_EA_RDREQ_32B[13] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[13] | TCC_EA_RDREQ_GMI_CREDIT_STALL[13] | TCC_EA_RDREQ[14] | TCC_EA_RDREQ_32B[14] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[14] | TCC_EA_RDREQ_GMI_CREDIT_STALL[14] | TCC_EA_RDREQ[15] | TCC_EA_RDREQ_32B[15] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[15] | TCC_EA_RDREQ_GMI_CREDIT_STALL[15] | TCC_EA_RDREQ[16] | TCC_EA_RDREQ_32B[16] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[16] | TCC_EA_RDREQ_GMI_CREDIT_STALL[16] | TCC_EA_RDREQ[17] | TCC_EA_RDREQ_32B[17] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[17] | TCC_EA_RDREQ_GMI_CREDIT_STALL[17] | TCC_EA_RDREQ[18] | TCC_EA_RDREQ_32B[18] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[18] | TCC_EA_RDREQ_GMI_CREDIT_STALL[18] | TCC_EA_RDREQ[19] | TCC_EA_RDREQ_32B[19] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[19] | TCC_EA_RDREQ_GMI_CREDIT_STALL[19] | TCC_EA_RDREQ[20] | TCC_EA_RDREQ_32B[20] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[20] | TCC_EA_RDREQ_GMI_CREDIT_STALL[20] | TCC_EA_RDREQ[21] | TCC_EA_RDREQ_32B[21] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[21] | TCC_EA_RDREQ_GMI_CREDIT_STALL[21] | TCC_EA_RDREQ[22] | TCC_EA_RDREQ_32B[22] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[22] | TCC_EA_RDREQ_GMI_CREDIT_STALL[22] | TCC_EA_RDREQ[23] | TCC_EA_RDREQ_32B[23] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[23] | TCC_EA_RDREQ_GMI_CREDIT_STALL[23] | TCC_EA_RDREQ[24] | TCC_EA_RDREQ_32B[24] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[24] | TCC_EA_RDREQ_GMI_CREDIT_STALL[24] | TCC_EA_RDREQ[25] | TCC_EA_RDREQ_32B[25] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[25] | TCC_EA_RDREQ_GMI_CREDIT_STALL[25] | TCC_EA_RDREQ[26] | TCC_EA_RDREQ_32B[26] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[26] | TCC_EA_RDREQ_GMI_CREDIT_STALL[26] | TCC_EA_RDREQ[27] | TCC_EA_RDREQ_32B[27] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[27] | TCC_EA_RDREQ_GMI_CREDIT_STALL[27] | TCC_EA_RDREQ[28] | TCC_EA_RDREQ_32B[28] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[28] | TCC_EA_RDREQ_GMI_CREDIT_STALL[28] | TCC_EA_RDREQ[29] | TCC_EA_RDREQ_32B[29] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[29] | TCC_EA_RDREQ_GMI_CREDIT_STALL[29] | TCC_EA_RDREQ[30] | TCC_EA_RDREQ_32B[30] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[30] | TCC_EA_RDREQ_GMI_CREDIT_STALL[30] | TCC_EA_RDREQ[31] | TCC_EA_RDREQ_32B[31] | TCC_EA_RDREQ_DRAM_CREDIT_STALL[31] | TCC_EA_RDREQ_GMI_CREDIT_STALL[31] | wave_size_16 | obj_16 | SQ_WAVE_CYCLES | SQ_WAIT_ANY | SQ_WAIT_INST_ANY | SQ_ACTIVE_INST_ANY | SQ_BUSY_CU_CYCLES | SQ_ACTIVE_INST_VMEM | SQ_ACTIVE_INST_LDS | SQ_ACTIVE_INST_VALU | TCP_UTCL1_TRANSLATION_MISS_sum | TCP_UTCL1_TRANSLATION_HIT_sum | TCP_UTCL1_PERMISSION_MISS_sum | TCP_UTCL1_REQUEST_sum | TA_ADDR_STALLED_BY_TC_CYCLES_sum | TA_TOTAL_WAVEFRONTS_sum | SPI_RA_WAVE_SIMD_FULL_CSN | SPI_RA_VGPR_SIMD_FULL_CSN | CPC_CPC_UTCL2IU_STALL | CPC_ME1_BUSY_FOR_PACKET_DECODE | TCC_EA_WRREQ_sum | TCC_EA_WRREQ_64B_sum | TCC_EA_WR_UNCACHED_32B_sum | TCC_EA_WRREQ_DRAM_sum | wave_size_17 | obj_17 | SQC_ICACHE_MISSES_DUPLICATE | SQC_DCACHE_INPUT_VALID_READYB | SQC_DCACHE_ATOMIC | SQC_DCACHE_REQ_READ_8 | SQC_DCACHE_REQ | SQC_DCACHE_HITS | SQC_DCACHE_MISSES | SQC_DCACHE_MISSES_DUPLICATE | wave_size_18 | obj_18 | TCC_HIT[0] | TCC_MISS[0] | TCC_READ[0] | TCC_REQ[0] | TCC_HIT[1] | TCC_MISS[1] | TCC_READ[1] | TCC_REQ[1] | TCC_HIT[2] | TCC_MISS[2] | TCC_READ[2] | TCC_REQ[2] | TCC_HIT[3] | TCC_MISS[3] | TCC_READ[3] | TCC_REQ[3] | TCC_HIT[4] | TCC_MISS[4] | TCC_READ[4] | TCC_REQ[4] | TCC_HIT[5] | TCC_MISS[5] | TCC_READ[5] | TCC_REQ[5] | TCC_HIT[6] | TCC_MISS[6] | TCC_READ[6] | TCC_REQ[6] | TCC_HIT[7] | TCC_MISS[7] | TCC_READ[7] | TCC_REQ[7] | TCC_HIT[8] | TCC_MISS[8] | TCC_READ[8] | TCC_REQ[8] | TCC_HIT[9] | TCC_MISS[9] | TCC_READ[9] | TCC_REQ[9] | TCC_HIT[10] | TCC_MISS[10] | TCC_READ[10] | TCC_REQ[10] | TCC_HIT[11] | TCC_MISS[11] | TCC_READ[11] | TCC_REQ[11] | TCC_HIT[12] | TCC_MISS[12] | TCC_READ[12] | TCC_REQ[12] | TCC_HIT[13] | TCC_MISS[13] | TCC_READ[13] | TCC_REQ[13] | TCC_HIT[14] | TCC_MISS[14] | TCC_READ[14] | TCC_REQ[14] | TCC_HIT[15] | TCC_MISS[15] | TCC_READ[15] | TCC_REQ[15] | TCC_HIT[16] | TCC_MISS[16] | TCC_READ[16] | TCC_REQ[16] | TCC_HIT[17] | TCC_MISS[17] | TCC_READ[17] | TCC_REQ[17] | TCC_HIT[18] | TCC_MISS[18] | TCC_READ[18] | TCC_REQ[18] | TCC_HIT[19] | TCC_MISS[19] | TCC_READ[19] | TCC_REQ[19] | TCC_HIT[20] | TCC_MISS[20] | TCC_READ[20] | TCC_REQ[20] | TCC_HIT[21] | TCC_MISS[21] | TCC_READ[21] | TCC_REQ[21] | TCC_HIT[22] | TCC_MISS[22] | TCC_READ[22] | TCC_REQ[22] | TCC_HIT[23] | TCC_MISS[23] | TCC_READ[23] | TCC_REQ[23] | TCC_HIT[24] | TCC_MISS[24] | TCC_READ[24] | TCC_REQ[24] | TCC_HIT[25] | TCC_MISS[25] | TCC_READ[25] | TCC_REQ[25] | TCC_HIT[26] | TCC_MISS[26] | TCC_READ[26] | TCC_REQ[26] | TCC_HIT[27] | TCC_MISS[27] | TCC_READ[27] | TCC_REQ[27] | TCC_HIT[28] | TCC_MISS[28] | TCC_READ[28] | TCC_REQ[28] | TCC_HIT[29] | TCC_MISS[29] | TCC_READ[29] | TCC_REQ[29] | TCC_HIT[30] | TCC_MISS[30] | TCC_READ[30] | TCC_REQ[30] | TCC_HIT[31] | TCC_MISS[31] | TCC_READ[31] | TCC_REQ[31] | Start_Timestamp | End_Timestamp |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 0 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7fce36be8ec0 | 0 | 0 | 0 | 998532 | 11 | 0 | 0 | 1083440 | 0 | 0 | 0 | 980959 | 0 | 0 | 0 | 1030903 | 0 | 0 | 0 | 981390 | 0 | 0 | 0 | 1069686 | 0 | 0 | 0 | 1131769 | 0 | 0 | 0 | 1232356 | 0 | 0 | 0 | 1062747 | 0 | 0 | 0 | 1038058 | 0 | 0 | 0 | 1031835 | 0 | 0 | 0 | 1076817 | 0 | 0 | 0 | 1114690 | 0 | 0 | 0 | 1047006 | 0 | 0 | 0 | 1004792 | 0 | 0 | 0 | 1267535 | 0 | 0 | 0 | 1151763 | 0 | 0 | 0 | 1049694 | 0 | 0 | 0 | 992650 | 0 | 0 | 0 | 1084352 | 0 | 0 | 0 | 1062905 | 0 | 0 | 0 | 1080186 | 0 | 0 | 0 | 1067162 | 0 | 0 | 0 | 1109373 | 0 | 0 | 0 | 1033119 | 0 | 0 | 0 | 1094220 | 0 | 0 | 0 | 1044460 | 0 | 0 | 0 | 1100322 | 0 | 0 | 0 | 1071074 | 0 | 0 | 0 | 1056893 | 0 | 0 | 0 | 1127537 | 0 | 0 | 0 | 1109825 | 64 | 0x7fcb418e4ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 168 | 56 | 131072.0 | 131072.0 | 0.0 | 929430.0 | 64 | 0x7ff515f48ec0 | 231824 | 128092 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 28977 | 28977 | 1943011.0 | 1334488.0 | 3205.0 | 166634.0 | 1043391.0 | 0.0 | 1326526.0 | 1027716.0 | 230113 | 136232 | 28977 | 0 | 28977 | 0 | 927264.0 | 483272.0 | 0.0 | 0.0 | 64 | 0x7f9f4b678ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 17627 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 428.0 | 32768.0 | 4096 | 16384 | 352 | 27627 | 1918 | 0 | 56.0 | 5.0 | 0.0 | 204806.0 | 64 | 0x7f24b44c4ec0 | 0 | 1321973 | 4096 | 4096 | 0 | 1354767 | 4096 | 4096 | 0 | 1222472 | 4096 | 4096 | 0 | 1273722 | 4096 | 4096 | 0 | 1223330 | 4096 | 4096 | 0 | 1437590 | 4096 | 4096 | 0 | 1053340 | 4096 | 4096 | 0 | 1197753 | 4096 | 4096 | 0 | 1110670 | 4096 | 4096 | 0 | 1201277 | 4096 | 4096 | 0 | 1283526 | 4096 | 4096 | 0 | 1159739 | 4096 | 4096 | 0 | 1071589 | 4096 | 4096 | 0 | 1339830 | 4096 | 4096 | 0 | 1619403 | 4096 | 4096 | 0 | 1277254 | 4096 | 4096 | 0 | 1217212 | 4096 | 4096 | 0 | 1202885 | 4096 | 4096 | 0 | 1131247 | 4096 | 4096 | 0 | 1569896 | 4096 | 4096 | 0 | 1065897 | 4096 | 4096 | 0 | 1068306 | 4096 | 4096 | 0 | 1195134 | 4096 | 4096 | 0 | 1260756 | 4096 | 4096 | 0 | 1582680 | 4096 | 4096 | 0 | 1030715 | 4096 | 4096 | 0 | 1073841 | 4096 | 4096 | 0 | 1140133 | 4096 | 4096 | 0 | 1528379 | 4096 | 4096 | 0 | 1118522 | 4096 | 4096 | 0 | 1189188 | 4096 | 4096 | 0 | 1318239 | 4096 | 4096 | 64 | 0x7f93502f4ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 38788672.0 | 34533107.0 | 0.0 | 64 | 0x7fc9a0414ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 27474486.0 | 85701973.0 | 38726495.0 | 131072.0 | 0.0 | 193774.0 | 0 | 0 | 14978 | 504.0 | 131082.0 | 0.0 | 12.0 | 64 | 0x7f84c28d0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 10365 | 0 | 816 | 27840 | 0 | 73095.0 | 131072.0 | 0.0 | 65568.0 | 64 | 0x7f78b2f18ec0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 0 | 28493 | 0 | 0 | 64 | 0x7f61d8d50ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 12228 | 18953 | 8358 | 545 | 0 | 26802 | 204457.0 | 0.0 | 73375.0 | 131082.0 | 64 | 0x7fcb203c4ec0 | 0 | 0 | 0 | 224 | 0 | 65536 | 64151 | 56 | 64 | 0x7f8639bc4ec0 | 32768 | 32768 | 0 | 64 | 0x7f80789d4ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131081.0 | 34813.0 | 46193.0 | 19343.0 | 64 | 0x7fa505dc4ec0 | 6369 | 0 | 4096 | 6358 | 0 | 4096 | 6369 | 0 | 4096 | 6400 | 0 | 4096 | 6386 | 0 | 4096 | 6372 | 0 | 4096 | 6356 | 0 | 4096 | 6413 | 0 | 4096 | 6421 | 0 | 4096 | 6370 | 0 | 4096 | 6362 | 0 | 4096 | 6370 | 0 | 4096 | 6404 | 0 | 4096 | 6388 | 0 | 4096 | 6374 | 0 | 4096 | 6358 | 0 | 4096 | 6373 | 0 | 4096 | 6418 | 0 | 4096 | 6367 | 0 | 4096 | 6358 | 0 | 4096 | 6389 | 0 | 4096 | 6394 | 0 | 4096 | 6331 | 0 | 4096 | 6509 | 0 | 4096 | 6345 | 0 | 4096 | 6372 | 0 | 4096 | 6416 | 0 | 4096 | 6366 | 0 | 4096 | 6359 | 0 | 4096 | 6389 | 0 | 4096 | 6396 | 0 | 4096 | 6332 | 0 | 4096 | 64 | 0x7f4979c7cec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65551.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fd080e6cec0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 50 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 155 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4099 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7f2f1f530ec0 | 11133304 | 9932039 | 857201 | 344064 | 1687571 | 0 | 0 | 163840 | 832.0 | 515140.0 | 0.0 | 524288.0 | 304714.0 | 32768.0 | 526086 | 0 | 0 | 11138 | 131072.0 | 131072.0 | 0.0 | 131072.0 | 64 | 0x7f40880acec0 | 1281 | 118966 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7fb6d0d44ec0 | 2298 | 4096 | 2298 | 6394 | 2295 | 4096 | 2295 | 6391 | 2333 | 4096 | 2333 | 6429 | 2304 | 4096 | 2304 | 6400 | 2292 | 4096 | 2292 | 6388 | 2362 | 4097 | 2363 | 6459 | 2288 | 4096 | 2288 | 6384 | 2309 | 4096 | 2309 | 6405 | 2307 | 4097 | 2308 | 6404 | 2300 | 4098 | 2302 | 6398 | 2298 | 4096 | 2298 | 6394 | 2338 | 4096 | 2338 | 6434 | 2308 | 4096 | 2308 | 6404 | 2292 | 4096 | 2292 | 6388 | 2310 | 4096 | 2310 | 6406 | 2290 | 4096 | 2290 | 6386 | 2288 | 4096 | 2288 | 6384 | 2308 | 4096 | 2308 | 6404 | 2292 | 4097 | 2293 | 6389 | 2300 | 4096 | 2300 | 6396 | 2306 | 4096 | 2306 | 6402 | 2354 | 4096 | 2354 | 6450 | 2274 | 4096 | 2274 | 6370 | 2463 | 4098 | 2465 | 6561 | 2299 | 4096 | 2299 | 6395 | 2288 | 4096 | 2288 | 6384 | 2308 | 4096 | 2308 | 6404 | 2295 | 4100 | 2299 | 6395 | 2306 | 4096 | 2306 | 6402 | 2310 | 4096 | 2310 | 6406 | 2358 | 4096 | 2358 | 6454 | 2276 | 4096 | 2276 | 6372 | 200376896683431 | 200376896703751 |
| 3 | 1 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7fce36be8ec0 | 1594 | 0 | 0 | 2720147 | 6 | 0 | 0 | 1869554 | 237 | 0 | 0 | 1993496 | 0 | 0 | 0 | 1923184 | 601 | 0 | 0 | 2130150 | 62 | 0 | 0 | 2018399 | 180 | 0 | 0 | 2134327 | 1167 | 0 | 0 | 2607349 | 2370 | 0 | 0 | 2542742 | 1381 | 0 | 0 | 1945373 | 1665 | 0 | 0 | 2542687 | 0 | 0 | 0 | 1535629 | 118 | 0 | 0 | 1941027 | 523 | 0 | 0 | 1974983 | 904 | 0 | 0 | 2531651 | 1115 | 0 | 0 | 2303815 | 2643 | 0 | 0 | 2702774 | 2608 | 0 | 0 | 2804743 | 157 | 0 | 0 | 1890348 | 0 | 0 | 0 | 1868577 | 0 | 0 | 0 | 1933870 | 221 | 0 | 0 | 2107803 | 0 | 0 | 0 | 1925904 | 0 | 0 | 0 | 2005264 | 0 | 0 | 0 | 1762695 | 2472 | 0 | 0 | 2491189 | 1386 | 0 | 0 | 2448452 | 0 | 0 | 0 | 1781075 | 0 | 0 | 0 | 1755621 | 62 | 0 | 0 | 1883518 | 56 | 0 | 0 | 1937660 | 670 | 0 | 0 | 2204976 | 64 | 0x7fcb418e4ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 1998111.0 | 64 | 0x7ff515f48ec0 | 329808 | 225588 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 41225 | 41225 | 3209855.0 | 2470951.0 | 4763.0 | 361257.0 | 1643901.0 | 0.0 | 2459264.0 | 2150854.0 | 329800 | 234863 | 41225 | 0 | 41225 | 0 | 1319200.0 | 777557.0 | 0.0 | 0.0 | 64 | 0x7f9f4b678ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29613 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 217.0 | 32768.0 | 4096 | 16384 | 302 | 40382 | 2073 | 0 | 56.0 | 9.0 | 0.0 | 200277.0 | 64 | 0x7f24b44c4ec0 | 0 | 3240352 | 2850 | 2850 | 0 | 3441033 | 2884 | 2884 | 0 | 3087288 | 2838 | 2838 | 0 | 3257695 | 2852 | 2852 | 0 | 4152851 | 2874 | 2874 | 0 | 4848014 | 2832 | 2832 | 0 | 3204429 | 2852 | 2852 | 0 | 3818273 | 2784 | 2784 | 0 | 3596741 | 2788 | 2788 | 0 | 4094721 | 2844 | 2844 | 0 | 2945150 | 2884 | 2884 | 0 | 3452935 | 2836 | 2836 | 0 | 3713736 | 2852 | 2852 | 0 | 4089463 | 2882 | 2882 | 0 | 4253109 | 2832 | 2832 | 0 | 3604687 | 2848 | 2848 | 0 | 4138665 | 2800 | 2800 | 0 | 4278658 | 2826 | 2826 | 0 | 3603473 | 2876 | 2876 | 0 | 3381891 | 2860 | 2860 | 0 | 3251591 | 2830 | 2830 | 0 | 3972817 | 2900 | 2900 | 0 | 4679674 | 2828 | 2828 | 0 | 4935258 | 2844 | 2844 | 0 | 4008260 | 2834 | 2834 | 0 | 3531928 | 2800 | 2800 | 0 | 3859378 | 2828 | 2828 | 0 | 4058627 | 2876 | 2876 | 0 | 3551846 | 2864 | 2864 | 0 | 3250186 | 2832 | 2832 | 0 | 3282636 | 2898 | 2898 | 0 | 4206694 | 2828 | 2828 | 64 | 0x7f93502f4ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 123589825.0 | 59871763.0 | 0.0 | 64 | 0x7fc9a0414ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 60639735.0 | 206253529.0 | 51932166.0 | 131072.0 | 0.0 | 519385.0 | 0 | 0 | 25870 | 3094.0 | 131083.0 | 0.0 | 20.0 | 64 | 0x7f84c28d0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 15863 | 0 | 819 | 36741 | 0 | 69975.0 | 131072.0 | 0.0 | 45566.0 | 64 | 0x7f78b2f18ec0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 0 | 42285 | 0 | 0 | 64 | 0x7f61d8d50ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 29844 | 27018 | 9579 | 2859 | 0 | 39240 | 200584.0 | 0.0 | 69498.0 | 131086.0 | 64 | 0x7fcb203c4ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7f8639bc4ec0 | 32768 | 32768 | 0 | 64 | 0x7f80789d4ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131082.0 | 126632.0 | 45557.0 | 0.0 | 64 | 0x7fa505dc4ec0 | 6270 | 0 | 4096 | 6263 | 0 | 4096 | 6266 | 0 | 4096 | 6267 | 0 | 4096 | 6241 | 0 | 4096 | 6241 | 0 | 4096 | 6285 | 0 | 4096 | 6293 | 0 | 4096 | 6292 | 0 | 4096 | 6271 | 0 | 4096 | 6260 | 0 | 4096 | 6265 | 0 | 4096 | 6259 | 0 | 4096 | 6240 | 0 | 4096 | 6243 | 0 | 4096 | 6286 | 0 | 4096 | 6255 | 0 | 4096 | 6294 | 0 | 4096 | 6272 | 0 | 4096 | 6273 | 0 | 4096 | 6235 | 0 | 4096 | 6237 | 0 | 4096 | 6227 | 0 | 4096 | 6242 | 0 | 4096 | 6244 | 0 | 4096 | 6259 | 0 | 4096 | 6297 | 0 | 4096 | 6279 | 0 | 4096 | 6276 | 0 | 4096 | 6231 | 0 | 4096 | 6241 | 0 | 4096 | 6231 | 0 | 4096 | 64 | 0x7f4979c7cec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65552.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fd080e6cec0 | 4097 | 0 | 83 | 0 | 4096 | 0 | 263 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 440 | 0 | 4096 | 0 | 623 | 0 | 4096 | 0 | 523 | 0 | 4096 | 0 | 691 | 0 | 4096 | 0 | 1236 | 0 | 4096 | 0 | 25 | 0 | 4096 | 0 | 2 | 0 | 4096 | 0 | 272 | 0 | 4096 | 0 | 3 | 0 | 4097 | 0 | 2 | 0 | 4096 | 0 | 94 | 0 | 4096 | 0 | 442 | 0 | 4097 | 0 | 113 | 0 | 4097 | 0 | 60 | 0 | 4096 | 0 | 174 | 0 | 4097 | 0 | 362 | 0 | 4096 | 0 | 118 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 496 | 0 | 4096 | 0 | 1319 | 0 | 4096 | 0 | 954 | 0 | 4096 | 0 | 72 | 0 | 4096 | 0 | 33 | 0 | 4099 | 0 | 229 | 0 | 4098 | 0 | 1484 | 0 | 4096 | 0 | 414 | 0 | 4096 | 0 | 105 | 0 | 4096 | 0 | 15 | 0 | 4096 | 0 | 199 | 0 | 64 | 0x7f2f1f530ec0 | 19169341 | 17753380 | 1071897 | 344064 | 2768728 | 0 | 0 | 163840 | 832.0 | 515136.0 | 0.0 | 524288.0 | 658206.0 | 32768.0 | 978464 | 0 | 0 | 13248 | 91430.0 | 91430.0 | 0.0 | 91430.0 | 64 | 0x7f40880acec0 | 0 | 183022 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7fb6d0d44ec0 | 2203 | 4096 | 2203 | 6299 | 2180 | 4096 | 2180 | 6276 | 2183 | 4096 | 2183 | 6279 | 2160 | 4096 | 2160 | 6256 | 2178 | 4096 | 2178 | 6274 | 2203 | 4097 | 2204 | 6300 | 2148 | 4096 | 2148 | 6244 | 2158 | 4096 | 2158 | 6254 | 2163 | 4097 | 2164 | 6260 | 2207 | 4097 | 2208 | 6304 | 2183 | 4096 | 2183 | 6279 | 2183 | 4096 | 2183 | 6279 | 2162 | 4096 | 2162 | 6258 | 2186 | 4096 | 2186 | 6282 | 2146 | 4096 | 2146 | 6242 | 2146 | 4097 | 2147 | 6243 | 2154 | 4096 | 2154 | 6250 | 2177 | 4096 | 2177 | 6273 | 2198 | 4097 | 2199 | 6295 | 2164 | 4096 | 2164 | 6260 | 2171 | 4096 | 2171 | 6267 | 2178 | 4096 | 2178 | 6274 | 2168 | 4096 | 2168 | 6264 | 2169 | 4096 | 2169 | 6265 | 2170 | 4096 | 2170 | 6266 | 2154 | 4096 | 2154 | 6250 | 2175 | 4096 | 2175 | 6271 | 2199 | 4100 | 2203 | 6299 | 2169 | 4100 | 2173 | 6269 | 2174 | 4096 | 2174 | 6270 | 2182 | 4096 | 2182 | 6278 | 2172 | 4096 | 2172 | 6268 | 200376896785031 | 200376896801511 |
| 4 | 2 | vecCopy(double*, double*, double*, int, int) | 2 | 1048576 | 256 | 0 | 0 | 8 | 0 | 16 | 64 | 0x7fce36be8ec0 | 406 | 0 | 0 | 2297015 | 95 | 0 | 0 | 1670061 | 0 | 0 | 0 | 1301013 | 631 | 0 | 0 | 2222911 | 0 | 0 | 0 | 1707719 | 75 | 0 | 0 | 2098806 | 0 | 0 | 0 | 1563213 | 665 | 0 | 0 | 2343553 | 0 | 0 | 0 | 1796945 | 148 | 0 | 0 | 2086040 | 0 | 0 | 0 | 1588797 | 23 | 0 | 0 | 1650979 | 188 | 0 | 0 | 1802622 | 570 | 0 | 0 | 1982464 | 2294 | 0 | 0 | 2585035 | 0 | 0 | 0 | 1776048 | 0 | 0 | 0 | 1648207 | 69 | 0 | 0 | 1905642 | 0 | 0 | 0 | 1750580 | 652 | 0 | 0 | 2373172 | 156 | 0 | 0 | 1930432 | 151 | 0 | 0 | 1780438 | 0 | 0 | 0 | 1728190 | 185 | 0 | 0 | 1786324 | 0 | 0 | 0 | 1554550 | 0 | 0 | 0 | 1542435 | 0 | 0 | 0 | 1682837 | 109 | 0 | 0 | 2210172 | 936 | 0 | 0 | 2359037 | 0 | 0 | 0 | 1611581 | 147 | 0 | 0 | 1812175 | 0 | 0 | 0 | 1638739 | 64 | 0x7fcb418e4ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 56 | 131072.0 | 131072.0 | 0.0 | 2136956.0 | 64 | 0x7ff515f48ec0 | 344104 | 228695 | 16384 | 0 | 16384 | 16384 | 32768 | 49152 | 43012 | 43012 | 3248159.0 | 2501995.0 | 4888.0 | 380369.0 | 1671249.0 | 0.0 | 2491439.0 | 2184921.0 | 344096 | 237615 | 43012 | 0 | 43012 | 0 | 1376384.0 | 790746.0 | 0.0 | 0.0 | 64 | 0x7f9f4b678ec0 | 0 | 393216 | 163840 | 0 | 0 | 0 | 0 | 0 | 29670 | 0.0 | 0.0 | 0.0 | 32768.0 | 0.0 | 0.0 | 201.0 | 32768.0 | 4096 | 16384 | 302 | 41194 | 2052 | 0 | 56.0 | 11.0 | 0.0 | 201187.0 | 64 | 0x7f24b44c4ec0 | 0 | 2742633 | 2856 | 2856 | 0 | 3972046 | 2888 | 2888 | 0 | 3535771 | 2840 | 2840 | 0 | 3286446 | 2836 | 2836 | 0 | 3821916 | 2852 | 2852 | 0 | 4493425 | 2820 | 2820 | 0 | 4766883 | 2868 | 2868 | 0 | 3348808 | 2804 | 2804 | 0 | 2888609 | 2804 | 2804 | 0 | 3156405 | 2854 | 2854 | 0 | 3263170 | 2888 | 2888 | 0 | 3213062 | 2844 | 2844 | 0 | 3120700 | 2832 | 2832 | 0 | 3015277 | 2850 | 2850 | 0 | 4277960 | 2824 | 2824 | 0 | 4497900 | 2860 | 2860 | 0 | 3320978 | 2812 | 2812 | 0 | 5182465 | 2844 | 2844 | 0 | 3174972 | 2858 | 2858 | 0 | 3891725 | 2888 | 2888 | 0 | 3917166 | 2820 | 2820 | 0 | 4111423 | 2860 | 2860 | 0 | 4032120 | 2796 | 2796 | 0 | 3940525 | 2808 | 2808 | 0 | 3999693 | 2810 | 2810 | 0 | 2612443 | 2812 | 2812 | 0 | 4054957 | 2852 | 2852 | 0 | 4818374 | 2866 | 2866 | 0 | 3208529 | 2888 | 2888 | 0 | 3146986 | 2824 | 2824 | 0 | 2777054 | 2864 | 2864 | 0 | 3700566 | 2796 | 2796 | 64 | 0x7f93502f4ec0 | 131072 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384 | 0 | 123389948.0 | 62176176.0 | 0.0 | 64 | 0x7fc9a0414ec0 | 114688 | 0 | 32768 | 32768 | 16384 | 16384 | 65536 | 49152 | 58076389.0 | 202073232.0 | 49908871.0 | 131072.0 | 0.0 | 489706.0 | 0 | 0 | 26137 | 3855.0 | 131085.0 | 0.0 | 24.0 | 64 | 0x7f84c28d0ec0 | 0 | 65536 | 32768 | 0 | 0 | 0 | 16384 | 16384 | 0.0 | 0.0 | 0.0 | 524288.0 | 0.0 | 0.0 | 0.0 | 20354 | 0 | 3698 | 37941 | 0 | 69436.0 | 131072.0 | 0.0 | 45839.0 | 64 | 0x7f78b2f18ec0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 0 | 41837 | 0 | 0 | 64 | 0x7f61d8d50ec0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 114688 | 2097152.0 | 2097152.0 | 1048576.0 | 1048576.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 30337 | 27048 | 9628 | 2838 | 0 | 39591 | 201175.0 | 0.0 | 70088.0 | 131087.0 | 64 | 0x7fcb203c4ec0 | 0 | 0 | 0 | 56 | 0 | 65536 | 65536 | 0 | 64 | 0x7f8639bc4ec0 | 32768 | 32768 | 0 | 64 | 0x7f80789d4ec0 | 10485760 | 65536 | 0 | 0 | 0 | 16384 | 0 | 0 | 131072.0 | 0.0 | 0.0 | 0.0 | 32768.0 | 16384.0 | 0 | 0 | 131083.0 | 94218.0 | 45624.0 | 0.0 | 64 | 0x7fa505dc4ec0 | 6281 | 0 | 4096 | 6255 | 0 | 4096 | 6273 | 0 | 4096 | 6314 | 0 | 4096 | 6242 | 0 | 4096 | 6289 | 0 | 4096 | 6299 | 0 | 4096 | 6308 | 0 | 4096 | 6312 | 0 | 4096 | 6284 | 0 | 4096 | 6261 | 0 | 4096 | 6271 | 0 | 4096 | 6319 | 0 | 4096 | 6243 | 0 | 4096 | 6290 | 0 | 4096 | 6303 | 0 | 4096 | 6285 | 0 | 4096 | 6315 | 0 | 4096 | 6252 | 0 | 4096 | 6246 | 0 | 4096 | 6231 | 0 | 4096 | 6271 | 0 | 4096 | 6275 | 0 | 4096 | 6292 | 0 | 4096 | 6293 | 0 | 4096 | 6288 | 0 | 4096 | 6319 | 0 | 4096 | 6254 | 0 | 4096 | 6250 | 0 | 4096 | 6230 | 0 | 4096 | 6273 | 0 | 4096 | 6281 | 0 | 4096 | 64 | 0x7f4979c7cec0 | 0 | 0 | 1048576 | 0 | 0 | 0 | 0 | 0 | 0.0 | 0.0 | 0.0 | 0.0 | 16384.0 | 0.0 | 0 | 32768 | 65554.0 | 0.0 | 0.0 | 0.0 | 64 | 0x7fd080e6cec0 | 4097 | 0 | 3 | 0 | 4096 | 0 | 568 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 511 | 0 | 4096 | 0 | 93 | 0 | 4096 | 0 | 261 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 3012 | 0 | 4096 | 0 | 379 | 0 | 4096 | 0 | 167 | 0 | 4096 | 0 | 3046 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 124 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 0 | 0 | 4097 | 0 | 20 | 0 | 4097 | 0 | 0 | 0 | 4096 | 0 | 405 | 0 | 4097 | 0 | 1096 | 0 | 4096 | 0 | 381 | 0 | 4096 | 0 | 29 | 0 | 4096 | 0 | 386 | 0 | 4096 | 0 | 400 | 0 | 4096 | 0 | 370 | 0 | 4096 | 0 | 0 | 0 | 4096 | 0 | 183 | 0 | 4099 | 0 | 8 | 0 | 4098 | 0 | 28 | 0 | 4096 | 0 | 79 | 0 | 4096 | 0 | 1 | 0 | 4096 | 0 | 109 | 0 | 4096 | 0 | 0 | 0 | 64 | 0x7f2f1f530ec0 | 19307708 | 18022335 | 941309 | 344064 | 2770543 | 0 | 0 | 163840 | 832.0 | 515146.0 | 0.0 | 524288.0 | 598275.0 | 32768.0 | 949488 | 0 | 0 | 13517 | 91076.0 | 91076.0 | 0.0 | 91076.0 | 64 | 0x7f40880acec0 | 0 | 187732 | 0 | 0 | 65536 | 63800 | 56 | 1680 | 64 | 0x7fb6d0d44ec0 | 2146 | 4096 | 2146 | 6242 | 2188 | 4096 | 2188 | 6284 | 2186 | 4096 | 2186 | 6282 | 2194 | 4096 | 2194 | 6290 | 2182 | 4096 | 2182 | 6278 | 2275 | 4097 | 2276 | 6372 | 2161 | 4096 | 2161 | 6257 | 2163 | 4096 | 2163 | 6259 | 2166 | 4097 | 2167 | 6263 | 2154 | 4097 | 2155 | 6251 | 2190 | 4096 | 2190 | 6286 | 2189 | 4096 | 2189 | 6285 | 2202 | 4096 | 2202 | 6298 | 2181 | 4096 | 2181 | 6277 | 2218 | 4096 | 2218 | 6314 | 2165 | 4097 | 2166 | 6262 | 2145 | 4096 | 2145 | 6241 | 2162 | 4096 | 2162 | 6258 | 2170 | 4097 | 2171 | 6267 | 2166 | 4096 | 2166 | 6262 | 2179 | 4096 | 2179 | 6275 | 2147 | 4096 | 2147 | 6243 | 2188 | 4096 | 2188 | 6284 | 2199 | 4096 | 2199 | 6295 | 2201 | 4096 | 2201 | 6297 | 2145 | 4096 | 2145 | 6241 | 2160 | 4096 | 2160 | 6256 | 2171 | 4100 | 2175 | 6271 | 2165 | 4100 | 2169 | 6265 | 2183 | 4096 | 2183 | 6279 | 2141 | 4096 | 2141 | 6237 | 2188 | 4096 | 2188 | 6284 | 200376896822791 | 200376896838791 |