Andryeyev, German
2305f8ae56
* SWDEV-465041 - Add support for user events with DD User events can be replaced with HSA signals. Add the interface to allocate HSA signal for user events and update the status on CL_COMPLETE. Force pinned path with DD to avoid blocking calls. Pinned memory can be released only when the command is complete. Simplify device enqueue path to use generic kernel arg buffer and signals * Fix notifyCmdQueue() logic for OCL * Avoid blocking calls in OCL with DD * Add event destruciton in a case of the failure.
106 řádky
4.1 KiB
C++
106 řádky
4.1 KiB
C++
/* Copyright (c) 2010 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#pragma once
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#ifndef WITHOUT_HSA_BACKEND
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/*! \addtogroup HSA OCL Stub Implementation
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* @{
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*/
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//! HSA OCL STUB Implementation
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namespace amd::roc {
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//! Device settings
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class Settings : public device::Settings {
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public:
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enum Hmm : uint32_t {
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EnableSystemMemory = 0x01, //!< Forces system memory preference by default
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EnableMallocPrefetch = 0x02, //!< Skips default prefetch after allocation
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EnableSvmTracking = 0x04, //!< Enables SW SVM tracking
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EnableDebugSvm = 0x08 //!< Extra debug flag (reserved for runtime developers)
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};
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union {
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struct {
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uint doublePrecision_ : 1; //!< Enables double precision support
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uint enableLocalMemory_ : 1; //!< Enable GPUVM memory
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uint enableNCMode_ : 1; //!< Enable Non Coherent mode for system memory
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uint imageDMA_ : 1; //!< Enable direct image DMA transfers
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uint imageBufferWar_ : 1; //!< Image buffer workaround for Gfx10
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uint cpu_wait_for_signal_ : 1; //!< Wait for HSA signal on CPU
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uint system_scope_signal_ : 1; //!< HSA signal is visibile to the entire system
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uint fgs_kernel_arg_ : 1; //!< Use fine grain kernel arg segment
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uint barrier_value_packet_ : 1; //!< Barrier value packet functionality
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uint dynamic_queues_ : 1; //!< Dynamic queues management
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uint blocking_blit_ : 1; //!< Blit ops can be blocking on CPU
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uint reserved_ : 21;
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};
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uint value_;
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};
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//! Default max workgroup size for 1D
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int maxWorkGroupSize_;
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//! Preferred workgroup size
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uint preferredWorkGroupSize_;
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uint kernargPoolSize_;
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uint numDeviceEvents_; //!< The number of device events
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uint numWaitEvents_; //!< The number of wait events for device enqueue
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size_t xferBufSize_; //!< Transfer buffer size for image copy optimization
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size_t pinnedXferSize_; //!< Pinned buffer size for transfer
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size_t pinnedMinXferSize_; //!< Minimal buffer size for pinned transfer
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size_t sdmaCopyThreshold_; //!< Use SDMA to copy above this size
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size_t sdma_p2p_threshold_; //!< Use SDMA in P2P above this size
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uint32_t hmmFlags_; //!< HMM functionality control flags
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uint32_t limit_blit_wg_; //!< The number of workgroups for blit execution
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//! Default constructor
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Settings();
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//! Creates settings
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bool create(bool fullProfile, const amd::Isa &isa, bool enableXNACK,
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bool coop_groups = false, bool isXgmi = false,
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bool hasValidHDPFlush = true);
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private:
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//! Disable copy constructor
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Settings(const Settings&);
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//! Disable assignment
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Settings& operator=(const Settings&);
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//! Overrides current settings based on registry/environment
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void override();
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//! Determine how kernel arguments should be implemented given ASIC (host
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//! memory, device memory, device memory with memory ordering workaround)
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void setKernelArgImpl(const amd::Isa& isa, bool isXgmi, bool hasValidHDPFlush);
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};
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/*@}*/} // namespace amd::roc
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#endif /*WITHOUT_HSA_BACKEND*/
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