agunashe
355 lines
17 KiB
C++
355 lines
17 KiB
C++
/* Copyright (c) 2009 - 2021 Advanced Micro Devices, Inc.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE. */
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#ifndef GPUDEFS_HPP_
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#define GPUDEFS_HPP_
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#include "top.hpp"
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#include "gsl_types.h"
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#include "gsl_config.h"
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#include "gsl_ctx.h"
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#include "backend.h"
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#include "GSLDevice.h"
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#include "GSLContext.h"
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extern bool getFuncInfoFromImage(CALimage image, CALfuncInfo* pFuncInfo);
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/*! \addtogroup GPU
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* @{
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*/
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//! GPU Device Implementation
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namespace gpu {
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//! Maximum number of the supported global atomic counters
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static constexpr uint MaxAtomicCounters = 8;
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//! Maximum number of the supported samplers
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static constexpr uint MaxSamplers = 16;
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//! Maximum number of supported read images
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static constexpr uint MaxReadImage = 128;
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//! Maximum number of supported write images
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static constexpr uint MaxWriteImage = 8;
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//! Maximum number of supported read/write images for OCL20
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static constexpr uint MaxReadWriteImage = 64;
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//! Maximum number of supported constant arguments
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static constexpr uint MaxConstArguments = 8;
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//! Maximum number of supported kernel UAV arguments
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static constexpr uint MaxUavArguments = 1024;
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//! Maximum number of pixels for a 1D image created from a buffer
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static constexpr size_t MaxImageBufferSize = 1 << 27;
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//! Maximum number of pixels for a 1D image created from a buffer
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static constexpr size_t MaxImageArraySize = 2048;
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//! Maximum number of supported constant buffers
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static constexpr uint MaxConstBuffers = MaxConstArguments + 8;
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//! Maximum number of constant buffers for arguments
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static constexpr uint MaxConstBuffersArguments = 2;
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//! Define offline CAL implementation
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static constexpr uint CalOfflineImpl = 0xffffffff;
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//! Alignment restriciton for the pinned memory
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static constexpr size_t PinnedMemoryAlignment = 4 * Ki;
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//! HSA path specific defines for images
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static constexpr uint HsaImageObjectSize = 48;
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static constexpr uint HsaImageObjectAlignment = 16;
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static constexpr uint HsaSamplerObjectSize = 32;
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static constexpr uint HsaSamplerObjectAlignment = 16;
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//! HSA path specific defines for images
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static constexpr uint DeviceQueueMaskSize = 32;
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// Supported OpenCL versions
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enum OclVersion { OpenCL10, OpenCL11, OpenCL12, OpenCL20, OpenCL21 };
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struct CalFormat {
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gslChannelOrder channelOrder_; //!< Texel/pixel GSL channel order
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cmSurfFmt type_; //!< Texel/pixel CAL format
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};
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struct MemoryFormat {
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cl_image_format clFormat_; //!< CL image format
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CalFormat calFormat_; //!< CAL image format
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};
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static constexpr MemoryFormat MemoryFormatMap[] = {
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// R
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{{CL_R, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_INTENSITY8}},
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{{CL_R, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R16}},
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{{CL_R, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_sR8}},
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{{CL_R, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_sU16}},
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{{CL_R, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_sR8I}},
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{{CL_R, CL_SIGNED_INT16}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_sR16I}},
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{{CL_R, CL_SIGNED_INT32}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_sR32I}},
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{{CL_R, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R8I}},
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{{CL_R, CL_UNSIGNED_INT16}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R16I}},
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{{CL_R, CL_UNSIGNED_INT32}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R32I}},
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{{CL_R, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R16F}},
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{{CL_R, CL_FLOAT}, {GSL_CHANNEL_ORDER_R, CM_SURF_FMT_R32F}},
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// A
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{{CL_A, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_INTENSITY8}},
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{{CL_A, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R16}},
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{{CL_A, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_sR8}},
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{{CL_A, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_sU16}},
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{{CL_A, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_sR8I}},
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{{CL_A, CL_SIGNED_INT16}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_sR16I}},
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{{CL_A, CL_SIGNED_INT32}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_sR32I}},
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{{CL_A, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R8I}},
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{{CL_A, CL_UNSIGNED_INT16}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R16I}},
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{{CL_A, CL_UNSIGNED_INT32}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R32I}},
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{{CL_A, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R16F}},
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{{CL_A, CL_FLOAT}, {GSL_CHANNEL_ORDER_A, CM_SURF_FMT_R32F}},
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// RG
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{{CL_RG, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG8}},
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{{CL_RG, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG16}},
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{{CL_RG, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_sRG8}},
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{{CL_RG, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_sUV16}},
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{{CL_RG, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_sRG8I}},
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{{CL_RG, CL_SIGNED_INT16}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_sRG16I}},
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{{CL_RG, CL_SIGNED_INT32}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_sRG32I}},
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{{CL_RG, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG8I}},
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{{CL_RG, CL_UNSIGNED_INT16}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG16I}},
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{{CL_RG, CL_UNSIGNED_INT32}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG32I}},
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{{CL_RG, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG16F}},
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{{CL_RG, CL_FLOAT}, {GSL_CHANNEL_ORDER_RG, CM_SURF_FMT_RG32F}},
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// RA
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{{CL_RA, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG8}},
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{{CL_RA, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16}},
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{{CL_RA, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG8}},
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{{CL_RA, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sUV16}},
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{{CL_RA, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG8I}},
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{{CL_RA, CL_SIGNED_INT16}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG16I}},
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{{CL_RA, CL_SIGNED_INT32}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG32I}},
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{{CL_RA, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG8I}},
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{{CL_RA, CL_UNSIGNED_INT16}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16I}},
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{{CL_RA, CL_UNSIGNED_INT32}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG32I}},
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{{CL_RA, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16F}},
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{{CL_RA, CL_FLOAT}, {GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG32F}},
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// RGB
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{{CL_RGB, CL_UNORM_INT_101010}, {GSL_CHANNEL_ORDER_RGB, CM_SURF_FMT_BGR10_X2}},
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// RGBA
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{{CL_RGBA, CL_UNORM_INT_101010}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGB10_X2}},
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// RGBA
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{{CL_RGBA, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA8}},
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{{CL_RGBA, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA16}},
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{{CL_RGBA, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_sRGBA8}},
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{{CL_RGBA, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_sUVWQ16}},
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{{CL_RGBA, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_sRGBA8I}},
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{{CL_RGBA, CL_SIGNED_INT16}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_sRGBA16I}},
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{{CL_RGBA, CL_SIGNED_INT32}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_sRGBA32I}},
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{{CL_RGBA, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA8UI}},
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{{CL_RGBA, CL_UNSIGNED_INT16}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA16UI}},
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{{CL_RGBA, CL_UNSIGNED_INT32}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA32UI}},
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{{CL_RGBA, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA16F}},
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{{CL_RGBA, CL_FLOAT}, {GSL_CHANNEL_ORDER_RGBA, CM_SURF_FMT_RGBA32F}},
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// ARGB
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{{CL_ARGB, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_ARGB, CM_SURF_FMT_RGBA8}},
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{{CL_ARGB, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_ARGB, CM_SURF_FMT_sRGBA8}},
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{{CL_ARGB, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_ARGB, CM_SURF_FMT_sRGBA8I}},
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{{CL_ARGB, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_ARGB, CM_SURF_FMT_RGBA8UI}},
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// BGRA
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{{CL_BGRA, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_BGRA, CM_SURF_FMT_RGBA8}},
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{{CL_BGRA, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_BGRA, CM_SURF_FMT_sRGBA8}},
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{{CL_BGRA, CL_SIGNED_INT8}, {GSL_CHANNEL_ORDER_BGRA, CM_SURF_FMT_sRGBA8I}},
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{{CL_BGRA, CL_UNSIGNED_INT8}, {GSL_CHANNEL_ORDER_BGRA, CM_SURF_FMT_RGBA8UI}},
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// LUMINANCE
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{{CL_LUMINANCE, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_sR8}},
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{{CL_LUMINANCE, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_sU16}},
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{{CL_LUMINANCE, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_INTENSITY8}},
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{{CL_LUMINANCE, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_R16}},
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{{CL_LUMINANCE, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_R16F}},
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{{CL_LUMINANCE, CL_FLOAT}, {GSL_CHANNEL_ORDER_LUMINANCE, CM_SURF_FMT_R32F}},
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// INTENSITY
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{{CL_INTENSITY, CL_SNORM_INT8}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_sR8}},
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{{CL_INTENSITY, CL_SNORM_INT16}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_sU16}},
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{{CL_INTENSITY, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_INTENSITY8}},
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{{CL_INTENSITY, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_R16}},
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{{CL_INTENSITY, CL_HALF_FLOAT}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_R16F}},
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{{CL_INTENSITY, CL_FLOAT}, {GSL_CHANNEL_ORDER_INTENSITY, CM_SURF_FMT_R32F}},
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// sRBGA
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{{CL_sRGBA, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_SRGBA, CM_SURF_FMT_RGBA8_SRGB}},
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{{CL_sRGBA, CL_UNSIGNED_INT8}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_SRGBA, CM_SURF_FMT_RGBA8UI}},
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// sRBG
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{{CL_sRGB, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_SRGB, CM_SURF_FMT_RGBX8UI}},
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{{CL_sRGB, CL_UNSIGNED_INT8}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_SRGB, CM_SURF_FMT_RGBA8UI}},
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// sRBGx
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{{CL_sRGBx, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_SRGBX, CM_SURF_FMT_RGBX8UI}},
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{{CL_sRGBx, CL_UNSIGNED_INT8}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_SRGBX, CM_SURF_FMT_RGBA8UI}},
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// sBGRA
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{{CL_sBGRA, CL_UNORM_INT8}, {GSL_CHANNEL_ORDER_SBGRA, CM_SURF_FMT_RGBA8}},
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{{CL_sBGRA, CL_UNSIGNED_INT8}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_SBGRA, CM_SURF_FMT_RGBA8UI}},
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// DEPTH
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{{CL_DEPTH, CL_FLOAT}, {GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_DEPTH32F}},
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{{CL_DEPTH, CL_UNSIGNED_INT32}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_R32I}},
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{{CL_DEPTH, CL_UNORM_INT16}, {GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_DEPTH16}},
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{{CL_DEPTH, CL_UNSIGNED_INT16}, // This is used only by blit kernel
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{GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_R16I}},
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{{CL_DEPTH_STENCIL, CL_UNORM_INT24},
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{GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_DEPTH24_STEN8}},
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{{CL_DEPTH_STENCIL, CL_FLOAT}, {GSL_CHANNEL_ORDER_REPLICATE_R, CM_SURF_FMT_DEPTH32F_X24_STEN8}}
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};
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struct MemFormatStruct {
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cmSurfFmt format_;
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uint size_;
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uint components_;
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};
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static constexpr MemFormatStruct MemoryFormatSize[] = {
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{CM_SURF_FMT_INTENSITY8, 1,
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1}, /**< 1 component, normalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RG8, 2,
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2}, /**< 2 component, normalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RGBA8, 4,
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4}, /**< 4 component, normalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RGBA8_SRGB, 4,
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4}, /**< 4 component, normalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_R16, 2,
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1}, /**< 1 component, normalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_RG16, 4,
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2}, /**< 2 component, normalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_RGBA16, 8,
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4}, /**< 4 component, normalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_sRGBA8, 4,
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4}, /**< 4 component, normalized signed 8-bit integer value per component */
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{CM_SURF_FMT_sU16, 2,
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1}, /**< 1 component, normalized signed 16-bit integer value per component */
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{CM_SURF_FMT_sUV16, 4,
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2}, /**< 2 component, normalized signed 16-bit integer value per component */
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{CM_SURF_FMT_sUVWQ16, 8,
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4}, /**< 4 component, normalized signed 16-bit integer value per component */
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{CM_SURF_FMT_R32F, 4, 1}, /**< A 1 component, 32-bit float value per component */
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{CM_SURF_FMT_RG32F, 8, 2}, /**< A 2 component, 32-bit float value per component */
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{CM_SURF_FMT_RGBA32F, 16, 4}, /**< A 4 component, 32-bit float value per component */
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{CM_SURF_FMT_sR8, 1,
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1}, /**< 1 component, normalized signed 8-bit integer value per component */
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{CM_SURF_FMT_sRG8, 2,
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2}, /**< 2 component, normalized signed 8-bit integer value per component */
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{CM_SURF_FMT_R8I, 1,
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1}, /**< 1 component, unnormalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RG8I, 2,
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2}, /**< 2 component, unnormalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RGBA8UI, 4,
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4}, /**< 4 component, unnormalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_RGBX8UI, 4,
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4}, /**< 4 component, unnormalized unsigned 8-bit integer value per component */
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{CM_SURF_FMT_sR8I, 1,
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1}, /**< 1 component, unnormalized signed 8-bit integer value per component */
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{CM_SURF_FMT_sRG8I, 2,
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2}, /**< 2 component, unnormalized signed 8-bit integer value per component */
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{CM_SURF_FMT_sRGBA8I, 4,
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4}, /**< 4 component, unnormalized signed 8-bit integer value per component */
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{CM_SURF_FMT_R16I, 2,
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1}, /**< 1 component, unnormalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_RG16I, 4,
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2}, /**< 2 component, unnormalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_RGBA16UI, 8,
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4}, /**< 4 component, unnormalized unsigned 16-bit integer value per component */
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{CM_SURF_FMT_sR16I, 2,
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1}, /**< 1 component, unnormalized signed 16-bit integer value per component */
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{CM_SURF_FMT_sRG16I, 4,
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2}, /**< 2 component, unnormalized signed 16-bit integer value per component */
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{CM_SURF_FMT_sRGBA16I, 8,
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4}, /**< 4 component, unnormalized signed 16-bit integer value per component */
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{CM_SURF_FMT_R32I, 4,
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1}, /**< 1 component, unnormalized unsigned 32-bit integer value per component */
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{CM_SURF_FMT_RG32I, 8,
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2}, /**< 2 component, unnormalized unsigned 32-bit integer value per component */
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{CM_SURF_FMT_RGBA32UI, 16,
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4}, /**< 4 component, unnormalized unsigned 32-bit integer value per component */
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{CM_SURF_FMT_sR32I, 4,
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1}, /**< 1 component, unnormalized signed 32-bit integer value per component */
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{CM_SURF_FMT_sRG32I, 8,
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2}, /**< 2 component, unnormalized signed 32-bit integer value per component */
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{CM_SURF_FMT_sRGBA32I, 16,
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4}, /**< 4 component, unnormalized signed 32-bit integer value per component */
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{CM_SURF_FMT_R16F, 2, 1}, /**< A 1 component, 16-bit float value per component */
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{CM_SURF_FMT_RG16F, 4, 2}, /**< A 2 component, 16-bit float value per component */
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{CM_SURF_FMT_RGBA16F, 8, 4}, /**< A 4 component, 16-bit float value per component */
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{CM_SURF_FMT_BGR10_X2, 4, 4}, /**< 4 component, unnormalized signed 10-bit integer value per
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component packed as (@c XXRRRRRRRRRRGGGGGGGGGGBBBBBBBBBB)*/
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{CM_SURF_FMT_RGB10_X2, 4, 4}, /**< 4 component, unnormalized signed 10-bit integer value per
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component packed as (@c XXRRRRRRRRRRGGGGGGGGGGBBBBBBBBBB)*/
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{CM_SURF_FMT_DEPTH32F, 4, 1}, /**< A one component, 32 float value per component */
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{CM_SURF_FMT_DEPTH16, 2, 1}, /**< A one component, 16 unsigned int value per component */
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{CM_SURF_FMT_DEPTH24_STEN8, 4, 1}, /**< A one component, 32 float value per component */
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{CM_SURF_FMT_DEPTH32F_X24_STEN8, 8,
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2} /**< depth + stencil, 64 bits per element packed as (@c
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XXXXXXXXXXXXXXXXXXXXXXXXSSSSSSSSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD) */
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};
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__inline const MemFormatStruct& memoryFormatSize(cmSurfFmt fmt) {
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for (uint i = 0; i < sizeof(MemoryFormatSize) / sizeof(MemFormatStruct); ++i) {
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if (MemoryFormatSize[i].format_ == fmt) {
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return MemoryFormatSize[i];
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}
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}
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assert(!"Unknown GSL memory format!");
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return MemoryFormatSize[0];
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}
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} // namespace gpu
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#endif // GPUDEFS_HPP_
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