Joe Narlo
3052ad4220
Change copyrights to MIT and remove date Signed-off-by: Joe Narlo <Joseph.Narlo@amd.com> Change-Id: I16f5b412f2b9ddefaaa1771aa714cc18829a1be4
242 lines
9.3 KiB
C++
242 lines
9.3 KiB
C++
/*
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* Copyright (c) Advanced Micro Devices, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef ROCM_SMI_ROCM_SMI_BINARY_PARSER_H_
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#define ROCM_SMI_ROCM_SMI_BINARY_PARSER_H_
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#include "rocm_smi/rocm_smi_common.h"
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#include "rocm_smi/rocm_smi.h"
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#include <cstdint>
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#include <map>
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#include <memory>
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#include <tuple>
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#include <vector>
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/**
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* A binary parser to read the pm table and register table
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*
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*/
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namespace amd::smi {
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// definition for register table
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enum amdgpu_sysfs_reg_offset {
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AMDGPU_SYS_REG_STATE_XGMI = 0x0000,
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AMDGPU_SYS_REG_STATE_WAFL = 0x1000,
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AMDGPU_SYS_REG_STATE_PCIE = 0x2000,
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AMDGPU_SYS_REG_STATE_USR = 0x3000,
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AMDGPU_SYS_REG_STATE_USR_1 = 0x4000,
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AMDGPU_SYS_REG_STATE_END = 0x5000,
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};
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#define FIELD_FLAG_NUM_INSTANCE 0x01
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#define FIELD_FLAG_NUM_SMN 0x02
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#define FIELD_FLAG_INSTANCE_START 0x04
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#define FIELD_FLAG_SMN_START 0x08
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#define FIELD_TYPE_U8 0x01
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#define FIELD_TYPE_U16 0x02
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#define FIELD_TYPE_U32 0x04
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#define FIELD_TYPE_U64 0x08
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struct metric_field {
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uint8_t field_type;
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int field_arr_size;
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const char *field_name;
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uint8_t field_flag;
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};
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struct metric_field xgmi_regs[] = {
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{ FIELD_TYPE_U16, 1, "structure_size", 0 },
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{ FIELD_TYPE_U8, 1, "format_revision", 0 },
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{ FIELD_TYPE_U8, 1, "content_revision", 0 },
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{ FIELD_TYPE_U8, 1, "state_type", 0 },
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{ FIELD_TYPE_U8, 1, "num_instances", FIELD_FLAG_NUM_INSTANCE },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U16, 1, "instance", FIELD_FLAG_INSTANCE_START },
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{ FIELD_TYPE_U16, 1, "state", 0 },
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{ FIELD_TYPE_U16, 1, "num_smn_regs", FIELD_FLAG_NUM_SMN },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U64, 1, "addr", FIELD_FLAG_SMN_START },
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{ FIELD_TYPE_U32, 1, "value", 0 },
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{ FIELD_TYPE_U32, 1, "pad", 0 },
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{ 0, 0, NULL, 0 },
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};
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// check me!
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struct metric_field wafl_regs[] = {
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{ FIELD_TYPE_U16, 1, "structure_size", 0 },
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{ FIELD_TYPE_U8, 1, "format_revision", 0 },
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{ FIELD_TYPE_U8, 1, "content_revision", 0 },
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{ FIELD_TYPE_U8, 1, "state_type", 0 },
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{ FIELD_TYPE_U8, 1, "num_instances", FIELD_FLAG_NUM_INSTANCE },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U16, 1, "instance", FIELD_FLAG_INSTANCE_START },
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{ FIELD_TYPE_U16, 1, "state", 0 },
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{ FIELD_TYPE_U16, 1, "num_smn_regs", FIELD_FLAG_NUM_SMN },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U64, 1, "addr", FIELD_FLAG_SMN_START },
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{ FIELD_TYPE_U32, 1, "value", 0 },
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{ FIELD_TYPE_U32, 1, "pad", 0 },
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{ 0, 0, NULL, 0 },
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};
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struct metric_field pcie_regs[] = {
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{ FIELD_TYPE_U16, 1, "structure_size", 0 },
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{ FIELD_TYPE_U8, 1, "format_revision", 0 },
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{ FIELD_TYPE_U8, 1, "content_revision", 0 },
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{ FIELD_TYPE_U8, 1, "state_type", 0 },
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{ FIELD_TYPE_U8, 1, "num_instances", FIELD_FLAG_NUM_INSTANCE },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U16, 1, "instance", FIELD_FLAG_INSTANCE_START },
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{ FIELD_TYPE_U16, 1, "state", 0 },
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{ FIELD_TYPE_U16, 1, "num_smn_regs", FIELD_FLAG_NUM_SMN },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U16, 1, "device_status", 0 },
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{ FIELD_TYPE_U16, 1, "link_status", 0 },
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{ FIELD_TYPE_U32, 1, "sub_bus_number_latency", 0 },
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{ FIELD_TYPE_U32, 1, "pcie_corr_err_status", 0 },
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{ FIELD_TYPE_U32, 1, "pcie_uncorr_err_status", 0 },
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{ FIELD_TYPE_U64, 1, "addr", FIELD_FLAG_SMN_START },
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{ FIELD_TYPE_U32, 1, "value", 0 },
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{ FIELD_TYPE_U32, 1, "pad", 0 },
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{ 0, 0, NULL, 0 },
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};
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struct metric_field usr_regs[] = {
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{ FIELD_TYPE_U16, 1, "structure_size", 0 },
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{ FIELD_TYPE_U8, 1, "format_revision", 0 },
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{ FIELD_TYPE_U8, 1, "content_revision", 0 },
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{ FIELD_TYPE_U8, 1, "state_type", 0 },
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{ FIELD_TYPE_U8, 1, "num_instances", FIELD_FLAG_NUM_INSTANCE },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U16, 1, "instance", FIELD_FLAG_INSTANCE_START },
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{ FIELD_TYPE_U16, 1, "state", 0 },
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{ FIELD_TYPE_U16, 1, "num_smn_regs", FIELD_FLAG_NUM_SMN },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U64, 1, "addr", FIELD_FLAG_SMN_START },
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{ FIELD_TYPE_U32, 1, "value", 0 },
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{ FIELD_TYPE_U32, 1, "pad", 0 },
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{ 0, 0, NULL, 0 },
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};
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// definition for pm metrics table
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#define FIELD_FLAG_ACCUMULATOR 0x01
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struct metric_field smu_13_0_6_v8[] = {
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{ FIELD_TYPE_U16, 1, "structure_size", 0 },
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{ FIELD_TYPE_U16, 1, "pad", 0 },
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{ FIELD_TYPE_U32, 1, "mp1_ip_discovery_version", 0 },
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{ FIELD_TYPE_U32, 1, "pmfw_version", 0 },
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{ FIELD_TYPE_U32, 1, "pmmetrics_version", 0 },
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{ FIELD_TYPE_U32, 1, "AccumulationCounter", 0 },
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{ FIELD_TYPE_U32, 1, "MaxSocketTemperature", 0 },
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{ FIELD_TYPE_U32, 1, "MaxVrTemperature", 0 },
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{ FIELD_TYPE_U32, 1, "MaxHbmTemperature", 0 },
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{ FIELD_TYPE_U64, 1, "MaxSocketTemperatureAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "MaxVrTemperatureAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "MaxHbmTemperatureAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "SocketPowerLimit", 0 },
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{ FIELD_TYPE_U32, 1, "MaxSocketPowerLimit", 0 },
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{ FIELD_TYPE_U32, 1, "SocketPower", 0 },
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{ FIELD_TYPE_U64, 1, "Timestamp", 0 },
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{ FIELD_TYPE_U64, 1, "SocketEnergyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "CcdEnergyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "XcdEnergyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "AidEnergyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "HbmEnergyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "CclkFrequencyLimit", 0 },
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{ FIELD_TYPE_U32, 1, "GfxclkFrequencyLimit", 0 },
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{ FIELD_TYPE_U32, 1, "FclkFrequency", 0 },
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{ FIELD_TYPE_U32, 1, "UclkFrequency", 0 },
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{ FIELD_TYPE_U32, 4, "SocclkFrequency", 0 },
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{ FIELD_TYPE_U32, 4, "VclkFrequency", 0 },
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{ FIELD_TYPE_U32, 4, "DclkFrequency", 0 },
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{ FIELD_TYPE_U32, 4, "LclkFrequency", 0 },
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{ FIELD_TYPE_U64, 8, "GfxclkFrequencyAcc", FIELD_FLAG_ACCUMULATOR},
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{ FIELD_TYPE_U64, 96, "CclkFrequencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "MaxCclkFrequency", 0 },
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{ FIELD_TYPE_U32, 1, "MinCclkFrequency", 0 },
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{ FIELD_TYPE_U32, 1, "MaxGfxclkFrequency", 0 },
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{ FIELD_TYPE_U32, 1, "MinGfxclkFrequency", 0 },
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{ FIELD_TYPE_U32, 4, "FclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 4, "UclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 4, "SocclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 4, "VclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 4, "DclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 4, "LclkFrequencyTable", 0 },
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{ FIELD_TYPE_U32, 1, "MaxLclkDpmRange", 0 },
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{ FIELD_TYPE_U32, 1, "MinLclkDpmRange", 0 },
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{ FIELD_TYPE_U32, 1, "XgmiWidth", 0 },
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{ FIELD_TYPE_U32, 1, "XgmiBitrate", 0 },
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{ FIELD_TYPE_U64, 8, "XgmiReadBandwidthAcc", 0 },
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{ FIELD_TYPE_U64, 8, "XgmiWriteBandwidthAcc", 0 },
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{ FIELD_TYPE_U32, 1, "SocketC0Residency", 0 },
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{ FIELD_TYPE_U32, 1, "SocketGfxBusy", 0 },
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{ FIELD_TYPE_U32, 1, "DramBandwidthUtilization", 0 },
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{ FIELD_TYPE_U64, 1, "SocketC0ResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "SocketGfxBusyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 1, "DramBandwidthAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "MaxDramBandwidth", 0 },
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{ FIELD_TYPE_U64, 1, "DramBandwidthUtilizationAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 4, "PcieBandwidthAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "ProchotResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "PptResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "SocketThmResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "VrThmResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "HbmThmResidencyAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U32, 1, "GfxLockXCDMak", 0 },
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{ FIELD_TYPE_U32, 8, "GfxclkFrequency", 0 },
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{ FIELD_TYPE_U64, 4, "PublicSerialNumber_AID", 0 },
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{ FIELD_TYPE_U64, 8, "PublicSerialNumber_XCD", 0 },
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{ FIELD_TYPE_U64, 12, "PublicSerialNumber_CCD", 0 },
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{ FIELD_TYPE_U64, 8, "XgmiReadDataSizeAcc", FIELD_FLAG_ACCUMULATOR },
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{ FIELD_TYPE_U64, 8, "XgmiWriteDataSizeAcc", FIELD_FLAG_ACCUMULATOR },
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{ 0, 0, NULL, 0 },
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};
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} // namespace amd::smi
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#endif // ROCM_SMI_ROCM_SMI_BINARY_PARSER_H_
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