Aditya Atluri
0180125a29
1. Added SDWA implementation inside IR file
2. Added device functions to header + used them in test
Change-Id: Ib4e059a58eee201cc82438689e3e9bc5f9d26653
[ROCm/hip commit: 5ef8ef3bd7]
90 行
3.4 KiB
LLVM
90 行
3.4 KiB
LLVM
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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target triple = "amdgcn--amdhsa"
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define linkonce_odr spir_func void @__threadfence() #1 {
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fence syncscope(2) seq_cst
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ret void
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}
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define linkonce_odr spir_func void @__threadfence_block() #1 {
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fence syncscope(3) seq_cst
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ret void
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}
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; Lightning does not support inline asm for 16-bit data types
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; So, bitcast half to short and then extend to 32bit i32
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; After inline asm, convert back to half
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define half @__hip_hc_ir_hadd_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_add_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hsub_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_sub_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hmul_half(half %a, half %b) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = zext i16 %1 to i32
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%4 = zext i16 %2 to i32
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%5 = tail call i32 asm "v_mul_f16 $0, $1, $2","=v,v,v"(i32 %3, i32 %4)
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%6 = trunc i32 %5 to i16
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%7 = bitcast i16 %6 to half
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ret half %7
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}
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define half @__hip_hc_ir_hfma_half(half %a, half %b, half %c) #1 {
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%1 = bitcast half %a to i16
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%2 = bitcast half %b to i16
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%3 = bitcast half %c to i16
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%4 = zext i16 %1 to i32
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%5 = zext i16 %2 to i32
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%6 = zext i16 %3 to i32
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%7 = tail call i32 asm "v_mad_f16 $0, $1, $2, $3","=v,v,v,v"(i32 %4, i32 %5, i32 %6)
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%8 = trunc i32 %7 to i16
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%9 = bitcast i16 %8 to half
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ret half %9
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}
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define i32 @__hip_hc_ir_hadd2_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_add_f16 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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tail call void asm sideeffect "v_add_f16_sdwa $0, $1, $2 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:WORD_1","v,v,v"(i32 %1, i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_hfma2_int(i32 %a, i32 %b, i32 %c) #1 {
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%1 = tail call i32 asm sideeffect "v_mad_f16 $0, $1, $2, $3","=v,v,v,v"(i32 %a, i32 %b, i32 %c)
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tail call void asm sideeffect "v_mul_f16_sdwa $0, $1, $2 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:WORD_1","v,v,v"(i32 %1, i32 %a, i32 %b)
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tail call void asm sideeffect "v_add_f16_sdwa $0, $1, $2 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:WORD_1","v,v,v"(i32 %1, i32 %1, i32 %c)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_hmul2_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_mul_f16 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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tail call void asm sideeffect "v_mul_f16_sdwa $0, $1, $2 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:WORD_1","v,v,v"(i32 %1, i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_hsub2_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_sub_f16 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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tail call void asm sideeffect "v_sub_f16_sdwa $0, $1, $2 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:WORD_1","v,v,v"(i32 %1, i32 %a, i32 %b)
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ret i32 %1
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}
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attributes #1 = { alwaysinline nounwind }
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