Shweta.Khatri
bc9cac97fe
Fix Musl libc NULL errors and unsupported pthread funcs for compatibility. Also ensures cleanup and error handling irrespective of CPU affinity override. Fix submitted by github dev - AngryLoki https://github.com/ROCm/ROCR-Runtime/issues/181 Change-Id: Ia487315e504112be5d3370756f23f6e23b9ae4be
295 řádky
11 KiB
C++
295 řádky
11 KiB
C++
////////////////////////////////////////////////////////////////////////////////
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//
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// The University of Illinois/NCSA
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// Open Source License (NCSA)
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//
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// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
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//
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// Developed by:
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//
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// AMD Research and AMD HSA Software Development
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//
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// Advanced Micro Devices, Inc.
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//
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// www.amd.com
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to
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// deal with the Software without restriction, including without limitation
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// the rights to use, copy, modify, merge, publish, distribute, sublicense,
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// and/or sell copies of the Software, and to permit persons to whom the
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// Software is furnished to do so, subject to the following conditions:
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//
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// - Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimers.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimers in
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// the documentation and/or other materials provided with the distribution.
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// - Neither the names of Advanced Micro Devices, Inc,
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// nor the names of its contributors may be used to endorse or promote
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// products derived from this Software without specific prior written
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// permission.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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// THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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// DEALINGS WITH THE SOFTWARE.
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//
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////////////////////////////////////////////////////////////////////////////////
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#include "core/inc/default_signal.h"
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#include "core/util/timer.h"
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#if defined(__i386__) || defined(__x86_64__)
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#include <mwaitxintrin.h>
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#define MWAITX_ECX_TIMER_ENABLE 0x2 // BIT(1)
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#endif
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namespace rocr {
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namespace core {
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int DefaultSignal::rtti_id_ = 0;
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int BusyWaitSignal::rtti_id_ = 0;
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BusyWaitSignal::BusyWaitSignal(SharedSignal* abi_block, bool enableIPC)
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: Signal(abi_block, enableIPC) {
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signal_.kind = AMD_SIGNAL_KIND_USER;
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signal_.event_mailbox_ptr = uint64_t(NULL);
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}
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hsa_signal_value_t BusyWaitSignal::LoadRelaxed() {
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return hsa_signal_value_t(
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atomic::Load(&signal_.value, std::memory_order_relaxed));
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}
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hsa_signal_value_t BusyWaitSignal::LoadAcquire() {
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return hsa_signal_value_t(
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atomic::Load(&signal_.value, std::memory_order_acquire));
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}
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void BusyWaitSignal::StoreRelaxed(hsa_signal_value_t value) {
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atomic::Store(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::StoreRelease(hsa_signal_value_t value) {
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atomic::Store(&signal_.value, int64_t(value), std::memory_order_release);
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}
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hsa_signal_value_t BusyWaitSignal::WaitRelaxed(hsa_signal_condition_t condition,
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hsa_signal_value_t compare_value, uint64_t timeout,
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hsa_wait_state_t wait_hint) {
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Retain();
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MAKE_SCOPE_GUARD([&]() { Release(); });
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waiting_++;
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MAKE_SCOPE_GUARD([&]() { waiting_--; });
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bool condition_met = false;
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int64_t value;
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debug_warning_n((!g_use_interrupt_wait || isIPC()) &&
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"Use of non-host signal in host signal wait API.", 10);
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timer::fast_clock::time_point start_time, time;
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start_time = timer::fast_clock::now();
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// Set a polling timeout value
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// Should be a few times bigger than null kernel latency
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const timer::fast_clock::duration kMaxElapsed = std::chrono::microseconds(200);
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uint64_t hsa_freq;
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HSA::hsa_system_get_info(HSA_SYSTEM_INFO_TIMESTAMP_FREQUENCY, &hsa_freq);
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const timer::fast_clock::duration fast_timeout =
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timer::duration_from_seconds<timer::fast_clock::duration>(
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double(timeout) / double(hsa_freq));
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#if defined(__i386__) || defined(__x86_64__)
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if (g_use_mwaitx) _mm_monitorx(const_cast<int64_t*>(&signal_.value), 0, 0);
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#endif
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while (true) {
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if (!IsValid()) return 0;
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value = atomic::Load(&signal_.value, std::memory_order_relaxed);
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switch (condition) {
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case HSA_SIGNAL_CONDITION_EQ: {
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condition_met = (value == compare_value);
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break;
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}
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case HSA_SIGNAL_CONDITION_NE: {
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condition_met = (value != compare_value);
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break;
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}
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case HSA_SIGNAL_CONDITION_GTE: {
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condition_met = (value >= compare_value);
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break;
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}
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case HSA_SIGNAL_CONDITION_LT: {
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condition_met = (value < compare_value);
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break;
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}
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default:
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return 0;
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}
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if (condition_met) return hsa_signal_value_t(value);
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time = timer::fast_clock::now();
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if (time - start_time > fast_timeout) {
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value = atomic::Load(&signal_.value, std::memory_order_relaxed);
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return hsa_signal_value_t(value);
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}
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if (time - start_time > kMaxElapsed) {
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os::uSleep(20);
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#if defined(__i386__) || defined(__x86_64__)
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} else if (g_use_mwaitx) {
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_mm_mwaitx(0, 60000, MWAITX_ECX_TIMER_ENABLE); // 60000 ~20us on a 1.5Ghz CPU
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_mm_monitorx(const_cast<int64_t*>(&signal_.value), 0, 0);
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#endif
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}
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}
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}
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hsa_signal_value_t BusyWaitSignal::WaitAcquire(hsa_signal_condition_t condition,
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hsa_signal_value_t compare_value, uint64_t timeout,
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hsa_wait_state_t wait_hint) {
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hsa_signal_value_t ret =
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WaitRelaxed(condition, compare_value, timeout, wait_hint);
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std::atomic_thread_fence(std::memory_order_acquire);
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return ret;
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}
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void BusyWaitSignal::AndRelaxed(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::AndAcquire(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_acquire);
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}
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void BusyWaitSignal::AndRelease(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_release);
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}
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void BusyWaitSignal::AndAcqRel(hsa_signal_value_t value) {
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atomic::And(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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}
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void BusyWaitSignal::OrRelaxed(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::OrAcquire(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_acquire);
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}
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void BusyWaitSignal::OrRelease(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_release);
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}
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void BusyWaitSignal::OrAcqRel(hsa_signal_value_t value) {
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atomic::Or(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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}
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void BusyWaitSignal::XorRelaxed(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::XorAcquire(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_acquire);
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}
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void BusyWaitSignal::XorRelease(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_release);
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}
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void BusyWaitSignal::XorAcqRel(hsa_signal_value_t value) {
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atomic::Xor(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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}
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void BusyWaitSignal::AddRelaxed(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::AddAcquire(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_acquire);
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}
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void BusyWaitSignal::AddRelease(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_release);
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}
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void BusyWaitSignal::AddAcqRel(hsa_signal_value_t value) {
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atomic::Add(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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}
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void BusyWaitSignal::SubRelaxed(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_relaxed);
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}
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void BusyWaitSignal::SubAcquire(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_acquire);
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}
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void BusyWaitSignal::SubRelease(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_release);
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}
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void BusyWaitSignal::SubAcqRel(hsa_signal_value_t value) {
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atomic::Sub(&signal_.value, int64_t(value), std::memory_order_acq_rel);
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}
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hsa_signal_value_t BusyWaitSignal::ExchRelaxed(hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Exchange(&signal_.value, int64_t(value),
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std::memory_order_relaxed));
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}
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hsa_signal_value_t BusyWaitSignal::ExchAcquire(hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Exchange(&signal_.value, int64_t(value),
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std::memory_order_acquire));
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}
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hsa_signal_value_t BusyWaitSignal::ExchRelease(hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Exchange(&signal_.value, int64_t(value),
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std::memory_order_release));
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}
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hsa_signal_value_t BusyWaitSignal::ExchAcqRel(hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Exchange(&signal_.value, int64_t(value),
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std::memory_order_acq_rel));
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}
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hsa_signal_value_t BusyWaitSignal::CasRelaxed(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Cas(&signal_.value, int64_t(value),
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int64_t(expected),
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std::memory_order_relaxed));
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}
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hsa_signal_value_t BusyWaitSignal::CasAcquire(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Cas(&signal_.value, int64_t(value),
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int64_t(expected),
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std::memory_order_acquire));
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}
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hsa_signal_value_t BusyWaitSignal::CasRelease(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Cas(&signal_.value, int64_t(value),
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int64_t(expected),
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std::memory_order_release));
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}
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hsa_signal_value_t BusyWaitSignal::CasAcqRel(hsa_signal_value_t expected,
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hsa_signal_value_t value) {
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return hsa_signal_value_t(atomic::Cas(&signal_.value, int64_t(value),
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int64_t(expected),
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std::memory_order_acq_rel));
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}
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} // namespace core
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} // namespace rocr
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