foreman
2c6bcfbf8d
SWDEV-107271 - [OpenCL][GFXIP9 Bring up] add support for Raven(gfx901) Review: http://ocltc.amd.com/reviews/r/11809/ Affected files ... ... //depot/stg/opencl/drivers/opencl/compiler/lib/backends/common/linker.cpp#154 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/loaders/bif/amuabi/amuABI.h#19 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/loaders/bif/amuabi/amuABIMultiBinary.cpp#19 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/libUtils.cpp#22 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings.h#49 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail.h#40 edit ... //depot/stg/opencl/drivers/opencl/compiler/lib/utils/v0_8/target_mappings_hsail64.h#35 edit ... //depot/stg/opencl/drivers/opencl/compiler/tools/driver/driver.cpp#65 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudefs.hpp#144 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpudevice.cpp#559 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gpusettings.cpp#348 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/GSLDevice.cpp#176 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/gpu/gslbe/src/rt/caltarget.h#4 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldefs.hpp#14 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#35 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#11 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/binary/BIFEnumCheck.cpp#26 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/math/OCLMathFunc.cpp#28 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLDeviceQueries.cpp#42 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLOfflineCompilation.cpp#18 edit ... //depot/stg/opencl/drivers/opencl/tests/ocltst/module/runtime/OCLPerfCounters.cpp#35 edit
609 lines
27 KiB
C++
609 lines
27 KiB
C++
//
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// Copyright (c) 2015 Advanced Micro Devices, Inc. All rights reserved.
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//
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#pragma once
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#include "top.hpp"
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#include "pal.h"
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#include "palGpuMemory.h"
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#include "palImage.h"
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#include "palFormatInfo.h"
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//
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/// Memory Object Type
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//
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enum PalGpuMemoryType {
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PAL_DEPTH_BUFFER = 0, ///< Depth Buffer
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PAL_BUFFER, ///< Pure buffer
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PAL_TEXTURE_3D, ///< 3D texture
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PAL_TEXTURE_2D, ///< 2D texture
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PAL_TEXTURE_1D, ///< 1D texture
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PAL_TEXTURE_1D_ARRAY, ///< 1D Array texture
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PAL_TEXTURE_2D_ARRAY, ///< 2D Array texture
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PAL_TEXTURE_BUFFER, ///< "buffer" texture inside VBO
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};
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struct HwDbgKernelInfo
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{
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uint64_t scratchBufAddr; ///< Handle of GPU local memory for kernel private scratch space
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size_t scratchBufferSizeInBytes; ///< size of memory pointed to by pScratchBuffer,
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uint64_t heapBufAddr; ///< Address of the global heap base
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const void* pAqlDispatchPacket; ///< Pointer to the dipatch packet
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const void* pAqlQueuePtr; ///< pointer to the AQL Queue
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void* trapHandler; ///< address of the trap handler (TBA)
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void* trapHandlerBuffer; ///< address of the trap handler buffer (TMA)
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uint32_t excpEn; ///< excecption mask
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bool trapPresent; ///< trap present flag
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bool sqDebugMode; ///< debug mode flag (GPU single step mode)
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uint32_t mgmtSe0Mask; ///< mask for SE0 (reserving CU for display)
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uint32_t mgmtSe1Mask; ///< mask for SE1 (reserving CU for display)
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uint32_t cacheDisableMask; ///< cache disable mask
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};
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//! Engine types
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enum EngineType
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{
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MainEngine = 0,
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SdmaEngine,
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AllEngines
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};
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struct GpuEvent
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{
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static const unsigned int InvalidID = ((1<<30) - 1);
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EngineType engineId_; ///< type of the id
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unsigned int id; ///< actual event id
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//! GPU event default constructor
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GpuEvent(): engineId_(MainEngine), id(InvalidID) {}
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//! Returns true if the current event is valid
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bool isValid() const { return (id != InvalidID) ? true : false; }
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//! Set invalid event id
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void invalidate() { id = InvalidID; }
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};
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/*! \addtogroup PAL
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* @{
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*/
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//! PAL Device Implementation
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namespace pal {
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//! Maximum number of the supported global atomic counters
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const static uint MaxAtomicCounters = 8;
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//! Maximum number of the supported samplers
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const static uint MaxSamplers = 16;
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//! Maximum number of supported read images
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const static uint MaxReadImage = 128;
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//! Maximum number of supported write images
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const static uint MaxWriteImage = 8;
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//! Maximum number of supported read/write images for OCL20
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const static uint MaxReadWriteImage = 64;
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//! Maximum number of supported constant arguments
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const static uint MaxConstArguments = 8;
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//! Maximum number of supported kernel UAV arguments
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const static uint MaxUavArguments = 1024;
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//! Maximum number of pixels for a 1D image created from a buffer
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const static size_t MaxImageBufferSize = 1 << 27;
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//! Maximum number of pixels for a 1D image created from a buffer
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const static size_t MaxImageArraySize = 2048;
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//! Maximum number of supported constant buffers
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const static uint MaxConstBuffers = MaxConstArguments + 8;
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//! Maximum number of constant buffers for arguments
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const static uint MaxConstBuffersArguments = 2;
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//! Alignment restriciton for the pinned memory
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const static size_t PinnedMemoryAlignment = 4 * Ki;
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//! HSA path specific defines for images
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const static uint HsaImageObjectSize = 48;
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const static uint HsaImageObjectAlignment = 16;
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const static uint HsaSamplerObjectSize = 32;
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const static uint HsaSamplerObjectAlignment = 16;
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//! HSA path specific defines for images
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const static uint DeviceQueueMaskSize = 32;
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struct AMDDeviceInfo {
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const char* targetName_; //!< Target name
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const char* machineTarget_; //!< Machine target
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uint simdPerCU_; //!< Number of SIMDs per CU
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uint simdWidth_; //!< Number of workitems processed per SIMD
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uint simdInstructionWidth_; //!< Number of instructions processed per SIMD
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uint memChannelBankWidth_; //!< Memory channel bank width
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uint localMemSizePerCU_; //!< Local memory size per CU
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uint localMemBanks_; //!< Number of banks of local memory
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uint gfxipVersion_; //!< The core engine GFXIP version
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};
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static const AMDDeviceInfo DeviceInfo[] = {
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/* Unknown */ { "", "unknown", 4, 16, 1, 256, 64 * Ki, 32, 0 },
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/* Tahiti */ { "", "tahiti", 4, 16, 1, 256, 64 * Ki, 32, 600 },
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/* Pitcairn */ { "", "pitcairn", 4, 16, 1, 256, 64 * Ki, 32, 600 },
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/* Capeverde */ { "", "bonaire", 4, 16, 1, 256, 64 * Ki, 32, 700 },
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/* Oland */ { "", "oland", 4, 16, 1, 256, 64 * Ki, 32, 600 },
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/* Hainan */ { "", "hainan", 4, 16, 1, 256, 64 * Ki, 32, 600 },
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/* Bonaire */ { "Bonaire", "bonaire", 4, 16, 1, 256, 64 * Ki, 32, 700 },
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/* Hawaii */ { "Hawaii", "hawaii", 4, 16, 1, 256, 64 * Ki, 32, 701 },
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/* Kalindi */ { "Kalindi", "kalindi", 4, 16, 1, 256, 64 * Ki, 32, 702 },
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/* Spectre */ { "Spectre", "spectre", 4, 16, 1, 256, 64 * Ki, 32, 701 },
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/* Carrizo */ { "Carrizo" , "carrizo", 4, 16, 1, 256, 64 * Ki, 32, 801 },
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/* Stoney */ { "Stoney", "stoney", 4, 16, 1, 256, 64 * Ki, 32, 810 },
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/* Iceland */ { "Iceland", "iceland", 4, 16, 1, 256, 64 * Ki, 32, 800 },
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/* Tonga */ { "Tonga", "tonga", 4, 16, 1, 256, 64 * Ki, 32, 800 },
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/* Fiji */ { "Fiji", "fiji", 4, 16, 1, 256, 64 * Ki, 32, 804 },
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/* Ellesmere */ { "Ellesmere", "ellesmere",4, 16, 1, 256, 64 * Ki, 32, 804 },
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/* Baffin */ { "Baffin", "baffin", 4, 16, 1, 256, 64 * Ki, 32, 804 },
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};
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// The GfxIpDeviceInfo table must match with GfxIpLevel enum
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// (located in //depot/stg/pal/inc/core/palDevice.h).
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static const AMDDeviceInfo GfxIpDeviceInfo[] = {
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/* Unknown */ { "unknown", "unknown", 4, 16, 1, 256, 64 * Ki, 32, 000 },
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/* GFX600 */ { "gfx600", "gfx600", 4, 16, 1, 256, 64 * Ki, 32, 600 },
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/* GFX700 */ { "gfx700", "gfx700", 4, 16, 1, 256, 64 * Ki, 32, 700 },
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/* GFX800 */ { "gfx800", "gfx800", 4, 16, 1, 256, 64 * Ki, 32, 800 },
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/* GFX801 */ { "gfx801", "gfx801", 4, 16, 1, 256, 64 * Ki, 32, 801 },
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/* GFX900 */ { "gfx900", "gfx900", 4, 16, 1, 256, 64 * Ki, 32, 900 },
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};
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static const AMDDeviceInfo Gfx901DeviceInfo =
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/* GFX901 */ { "gfx901", "gfx901", 4, 16, 1, 256, 64 * Ki, 32, 901 };
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enum gfx_handle {
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gfx700 = 700,
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gfx701 = 701,
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gfx702 = 702,
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gfx800 = 800,
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gfx801 = 801,
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gfx804 = 804,
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gfx810 = 810,
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gfx900 = 900,
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gfx901 = 901
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};
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static const char* Gfx700 = "AMD:AMDGPU:7:0:0";
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static const char* Gfx701 = "AMD:AMDGPU:7:0:1";
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static const char* Gfx800 = "AMD:AMDGPU:8:0:0";
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static const char* Gfx801 = "AMD:AMDGPU:8:0:1";
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static const char* Gfx804 = "AMD:AMDGPU:8:0:4";
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static const char* Gfx810 = "AMD:AMDGPU:8:1:0";
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static const char* Gfx900 = "AMD:AMDGPU:9:0:0";
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static const char* Gfx901 = "AMD:AMDGPU:9:0:1";
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// Supported OpenCL versions
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enum OclVersion {
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OpenCL10,
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OpenCL11,
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OpenCL12,
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OpenCL20
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};
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struct MemoryFormat {
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cl_image_format clFormat_; //!< CL image format
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Pal::ChNumFormat palFormat_; //!< PAL image format
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Pal::ChannelMapping palChannel_; //!< PAL channel mapping
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};
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static const MemoryFormat
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MemoryFormatMap[] = {
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// R
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{ { CL_R, CL_UNORM_INT8 },
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Pal::ChNumFormat::X8_Unorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_UNORM_INT16 },
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Pal::ChNumFormat::X16_Unorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_SNORM_INT8 },
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Pal::ChNumFormat::X8_Snorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_SNORM_INT16 },
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Pal::ChNumFormat::X16_Snorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_SIGNED_INT8 },
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Pal::ChNumFormat::X8_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_SIGNED_INT16 },
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Pal::ChNumFormat::X16_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_SIGNED_INT32 },
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Pal::ChNumFormat::X32_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_UNSIGNED_INT8 },
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Pal::ChNumFormat::X8_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_UNSIGNED_INT16 },
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Pal::ChNumFormat::X16_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_UNSIGNED_INT32 },
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Pal::ChNumFormat::X32_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_HALF_FLOAT },
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Pal::ChNumFormat::X16_Float,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_R, CL_FLOAT },
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Pal::ChNumFormat::X32_Float,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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// A
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{ { CL_A, CL_UNORM_INT8 },
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Pal::ChNumFormat::X8_Unorm,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_UNORM_INT16 },
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Pal::ChNumFormat::X16_Unorm,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_SNORM_INT8 },
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Pal::ChNumFormat::X8_Snorm,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_SNORM_INT16 },
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Pal::ChNumFormat::X16_Snorm,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_SIGNED_INT8 },
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Pal::ChNumFormat::X8_Sint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_SIGNED_INT16 },
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Pal::ChNumFormat::X16_Sint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_SIGNED_INT32},
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Pal::ChNumFormat::X32_Sint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_UNSIGNED_INT8 },
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Pal::ChNumFormat::X8_Uint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_UNSIGNED_INT16 },
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Pal::ChNumFormat::X16_Uint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_UNSIGNED_INT32},
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Pal::ChNumFormat::X32_Uint,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_HALF_FLOAT },
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Pal::ChNumFormat::X16_Float,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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{ { CL_A, CL_FLOAT },
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Pal::ChNumFormat::X32_Float,
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{ Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::Zero,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::X } },
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// RG
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{ { CL_RG, CL_UNORM_INT8 },
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Pal::ChNumFormat::X8Y8_Unorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_UNORM_INT16 },
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Pal::ChNumFormat::X16Y16_Unorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_SNORM_INT8 },
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Pal::ChNumFormat::X8Y8_Snorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_SNORM_INT16 },
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Pal::ChNumFormat::X16Y16_Snorm,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_SIGNED_INT8 },
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Pal::ChNumFormat::X8Y8_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_SIGNED_INT16 },
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Pal::ChNumFormat::X16Y16_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_SIGNED_INT32},
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Pal::ChNumFormat::X32Y32_Sint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_UNSIGNED_INT8 },
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Pal::ChNumFormat::X8Y8_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_UNSIGNED_INT16 },
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Pal::ChNumFormat::X16Y16_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_UNSIGNED_INT32},
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Pal::ChNumFormat::X32Y32_Uint,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_HALF_FLOAT },
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Pal::ChNumFormat::X16Y16_Float,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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{ { CL_RG, CL_FLOAT },
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Pal::ChNumFormat::X32Y32_Float,
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{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
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Pal::ChannelSwizzle::Zero, Pal::ChannelSwizzle::One } },
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/*
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// RA
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{ { CL_RA, CL_UNORM_INT8 },
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{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG8 } },
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{ { CL_RA, CL_UNORM_INT16 },
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{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16 } },
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{ { CL_RA, CL_SNORM_INT8 },
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{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG8 } },
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{ { CL_RA, CL_SNORM_INT16 },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sUV16 } },
|
|
|
|
{ { CL_RA, CL_SIGNED_INT8 },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG8I } },
|
|
{ { CL_RA, CL_SIGNED_INT16 },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG16I } },
|
|
{ { CL_RA, CL_SIGNED_INT32},
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_sRG32I } },
|
|
{ { CL_RA, CL_UNSIGNED_INT8 },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG8I } },
|
|
{ { CL_RA, CL_UNSIGNED_INT16 },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16I } },
|
|
{ { CL_RA, CL_UNSIGNED_INT32},
|
|
{ GSL_CHANNEL_ORDER_RA , CM_SURF_FMT_RG32I } },
|
|
|
|
{ { CL_RA, CL_HALF_FLOAT },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG16F } },
|
|
{ { CL_RA, CL_FLOAT },
|
|
{ GSL_CHANNEL_ORDER_RA, CM_SURF_FMT_RG32F } },
|
|
*/
|
|
// RGB
|
|
{ { CL_RGB, CL_UNORM_INT_101010 },
|
|
Pal::ChNumFormat::X10Y10Z10W2_Unorm,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_RGB, CL_UNSIGNED_INT8 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::One } },
|
|
|
|
// RGBA
|
|
{ { CL_RGBA, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_UNORM_INT16 },
|
|
Pal::ChNumFormat::X16Y16Z16W16_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
|
|
{ { CL_RGBA, CL_SNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_SNORM_INT16 },
|
|
Pal::ChNumFormat::X16Y16Z16W16_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
|
|
{ { CL_RGBA, CL_SIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Sint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_SIGNED_INT16 },
|
|
Pal::ChNumFormat::X16Y16Z16W16_Sint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_SIGNED_INT32 },
|
|
Pal::ChNumFormat::X32Y32Z32W32_Sint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_UNSIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_UNSIGNED_INT16 },
|
|
Pal::ChNumFormat::X16Y16Z16W16_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_UNSIGNED_INT32},
|
|
Pal::ChNumFormat::X32Y32Z32W32_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
|
|
{ { CL_RGBA, CL_HALF_FLOAT },
|
|
Pal::ChNumFormat::X16Y16Z16W16_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_RGBA, CL_FLOAT },
|
|
Pal::ChNumFormat::X32Y32Z32W32_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
|
|
// ARGB
|
|
{ { CL_ARGB, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Unorm,
|
|
{ Pal::ChannelSwizzle::Y, Pal::ChannelSwizzle::Z,
|
|
Pal::ChannelSwizzle::W, Pal::ChannelSwizzle::X } },
|
|
{ { CL_ARGB, CL_SNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Snorm,
|
|
{ Pal::ChannelSwizzle::Y, Pal::ChannelSwizzle::Z,
|
|
Pal::ChannelSwizzle::W, Pal::ChannelSwizzle::X } },
|
|
{ { CL_ARGB, CL_SIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Sint,
|
|
{ Pal::ChannelSwizzle::Y, Pal::ChannelSwizzle::Z,
|
|
Pal::ChannelSwizzle::W, Pal::ChannelSwizzle::X } },
|
|
{ { CL_ARGB, CL_UNSIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::Y, Pal::ChannelSwizzle::Z,
|
|
Pal::ChannelSwizzle::W, Pal::ChannelSwizzle::X } },
|
|
|
|
// BGRA
|
|
{ { CL_BGRA, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Unorm,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
{ { CL_BGRA, CL_SNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Snorm,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
{ { CL_BGRA, CL_SIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Sint,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
{ { CL_BGRA, CL_UNSIGNED_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
|
|
// LUMINANCE
|
|
{ { CL_LUMINANCE, CL_SNORM_INT8 },
|
|
Pal::ChNumFormat::X8_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_LUMINANCE, CL_SNORM_INT16 },
|
|
Pal::ChNumFormat::X16_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_LUMINANCE, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_LUMINANCE, CL_UNORM_INT16 },
|
|
Pal::ChNumFormat::X16_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_LUMINANCE, CL_HALF_FLOAT },
|
|
Pal::ChNumFormat::X16_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
{ { CL_LUMINANCE, CL_FLOAT },
|
|
Pal::ChNumFormat::X32_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::One } },
|
|
|
|
// INTENSITY
|
|
{ { CL_INTENSITY, CL_SNORM_INT8 },
|
|
Pal::ChNumFormat::X8_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_INTENSITY, CL_SNORM_INT16 },
|
|
Pal::ChNumFormat::X16_Snorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_INTENSITY, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_INTENSITY, CL_UNORM_INT16 },
|
|
Pal::ChNumFormat::X16_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_INTENSITY, CL_HALF_FLOAT },
|
|
Pal::ChNumFormat::X16_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_INTENSITY, CL_FLOAT },
|
|
Pal::ChNumFormat::X32_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
|
|
// sRBGA
|
|
{ { CL_sRGBA, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Srgb,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
{ { CL_sRGBA, CL_UNSIGNED_INT8 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::W } },
|
|
|
|
// sRBG
|
|
{ { CL_sRGB, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Srgb,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::One } },
|
|
{ { CL_sRGB, CL_UNSIGNED_INT8 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::One } },
|
|
|
|
// sRBGx
|
|
{ { CL_sRGBx, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Srgb,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::One } },
|
|
{ { CL_sRGBx, CL_UNSIGNED_INT8 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::One } },
|
|
|
|
// sBGRA
|
|
{ { CL_sBGRA, CL_UNORM_INT8 },
|
|
Pal::ChNumFormat::X8Y8Z8W8_Srgb,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
{ { CL_sBGRA, CL_UNSIGNED_INT8 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X8Y8Z8W8_Uint,
|
|
{ Pal::ChannelSwizzle::Z, Pal::ChannelSwizzle::Y,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::W } },
|
|
|
|
// DEPTH
|
|
{ { CL_DEPTH, CL_FLOAT },
|
|
Pal::ChNumFormat::X32_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_DEPTH, CL_UNSIGNED_INT32 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X32_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
|
|
{ { CL_DEPTH, CL_UNORM_INT16 },
|
|
Pal::ChNumFormat::X16_Unorm,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_DEPTH, CL_UNSIGNED_INT16 }, // This is used only by blit kernel
|
|
Pal::ChNumFormat::X16_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
|
|
{ { CL_DEPTH_STENCIL, CL_UNORM_INT24 },
|
|
Pal::ChNumFormat::X32_Uint,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } },
|
|
{ { CL_DEPTH_STENCIL, CL_FLOAT },
|
|
Pal::ChNumFormat::X32_Float,
|
|
{ Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X,
|
|
Pal::ChannelSwizzle::X, Pal::ChannelSwizzle::X } }
|
|
};
|
|
|
|
} // namespace pal
|
|
|