Aditya Atluri
60ec83c683
1. Split hip_ir.ll to hip_hc.ll and hip_hc_gfx803.ll a. hip_hc.ll contains arch generic ir implementations b. hip_hc_gfx803.ll contains gfx803 (fiji, polaris) specific ir 2. HIPCC can now parse --amdgpu-target=*. a. Usage: hipcc --amdgpu-target=gfx803 --amdgpu-target=gfx701 b. TODO: Convert to --amdgpu-target=gfx803,gfx701 3. With LLC in HCC able to generate native f16 isa, removed inline half asm math ops 4. Fixed threadfence and threadfence_block to use functions in rocdl Change-Id: Ic9a9e3e04139b0d75d2c2a263c030ca77adc1019
31 wiersze
1.0 KiB
LLVM
31 wiersze
1.0 KiB
LLVM
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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target triple = "amdgcn--amdhsa"
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define i32 @__hip_hc_ir_mul24_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_mul_i32_i24 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_umul24_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_mul_u32_u24 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_mulhi_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_mul_hi_i32 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_umulhi_int(i32 %a, i32 %b) #1 {
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%1 = tail call i32 asm sideeffect "v_mul_hi_u32 $0, $1, $2","=v,v,v"(i32 %a, i32 %b)
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ret i32 %1
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}
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define i32 @__hip_hc_ir_usad_int(i32 %a, i32 %b, i32 %c) #1 {
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%1 = tail call i32 asm sideeffect "v_sad_u32 $0, $1, $2, $3","=v,v,v,v"(i32 %a, i32 %b, i32 %c)
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ret i32 %1
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}
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attributes #1 = { alwaysinline nounwind }
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