611911020c
Fix register COMPUTE_PGM_RSRC2 in Dispatch code. Bit 6 (called TRAP_PRESENT on pre-GFX12) should not be set on GFX12 as it has a different meaning (DYNAMIC_VGPR). Minor instructions changes for CopyOnSignalIsa and WriteAndSignalIsa shaders. Change-Id: Ib4e75e3c92f220210bc45778738d81b91efb9d5e Signed-off-by: David Belanger <david.belanger@amd.com> Signed-off-by: Chris Freehill <cfreehil@amd.com>