Chris Freehill
9d70b6a420
In several places aql packets were written to queue all at once
instead of doing the header atomically. These cases have been
fixed.
There were a few hsa_signal leaked that have been addressed.
There was some duplication of code that has been addressed.
Addresses ROCMOPS-456
Change-Id: Ia1869bc370f92e49ac560301df47741d5f76978e
[ROCm/ROCR-Runtime commit: 081a2cc875]
545 wiersze
19 KiB
C++
Executable File
545 wiersze
19 KiB
C++
Executable File
/*
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* =============================================================================
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* ROC Runtime Conformance Release License
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* =============================================================================
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* The University of Illinois/NCSA
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* Open Source License (NCSA)
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*
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* Copyright (c) 2018, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Developed by:
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*
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* AMD Research and AMD ROC Software Development
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*
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* Advanced Micro Devices, Inc.
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*
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* www.amd.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal with the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimers.
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* - Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimers in
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* the documentation and/or other materials provided with the distribution.
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* - Neither the names of <Name of Development Group, Name of Institution>,
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* nor the names of its contributors may be used to endorse or promote
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* products derived from this Software without specific prior written
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* permission.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS WITH THE SOFTWARE.
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*
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*/
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#include <fcntl.h>
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#include <algorithm>
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#include <iostream>
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#include <vector>
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#include <memory>
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#include <string>
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#include "suites/functional/memory_atomics.h"
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#include "common/base_rocr_utils.h"
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#include "common/common.h"
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#include "common/helper_funcs.h"
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#include "common/hsatimer.h"
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#include "gtest/gtest.h"
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#include "hsa/hsa.h"
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#include "hsa/hsa_ext_finalize.h"
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static const uint32_t kNumBufferElements = 256;
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static const int kValue = 5;
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MemoryAtomic::MemoryAtomic(AtomicTest testtype) :
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TestBase() {
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set_num_iteration(10); // Number of iterations to execute of the main test;
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// This is a default value which can be overridden
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// on the command line.
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testtype_ = testtype;
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std::string name;
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std::string desc;
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name = "RocR Memory Atomic Test";
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desc = "";
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if (testtype_ == ADD) {
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name += " For ADD";
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desc += " This test will do Add kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == SUB) {
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name += " For Sub";
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desc += " This test will do Sub kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == AND) {
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name += " For And";
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desc += " This test will do AND kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == OR) {
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name += " For Or";
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desc += " This test will do OR kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == XOR) {
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name += " For Xor";
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desc += " This test will do XOR kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == MIN) {
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name += " For Minimum";
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desc += " This test will do Minimum kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == MAX) {
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name += " For Maximum";
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desc += " This test will do Maximum kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == XCHG) {
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name += " For Exchange";
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desc += " This test will do Xchg kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == INC) {
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name += " For Increment";
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desc += " This test will do Increment kernel atomic"
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" operation on GPU and system memory.";
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} else if (testtype_ == DEC) {
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name += " For Decremnet";
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desc += " This test will do decrement kernel atomic"
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" operation on GPU and system memory.";
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}
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set_title(name);
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set_description(desc);
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memset(&aql(), 0, sizeof(hsa_kernel_dispatch_packet_t));
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}
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MemoryAtomic::~MemoryAtomic(void) {
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}
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// Any 1-time setup involving member variables used in the rest of the test
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// should be done here.
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void MemoryAtomic::SetUp(void) {
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hsa_status_t err;
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TestBase::SetUp();
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err = rocrtst::SetDefaultAgents(this);
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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err = rocrtst::SetPoolsTypical(this);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Fill up the kernel packet except header
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err = rocrtst::InitializeAQLPacket(this, &aql());
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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return;
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}
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void MemoryAtomic::Run(void) {
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// Compare required profile for this test case with what we're actually
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// running on
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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TestBase::Run();
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}
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void MemoryAtomic::DisplayTestInfo(void) {
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TestBase::DisplayTestInfo();
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}
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void MemoryAtomic::DisplayResults(void) const {
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// Compare required profile for this test case with what we're actually
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// running on
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if (!rocrtst::CheckProfile(this)) {
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return;
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}
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return;
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}
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void MemoryAtomic::Close() {
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// This will close handles opened within rocrtst utility calls and call
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// hsa_shut_down(), so it should be done after other hsa cleanup
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TestBase::Close();
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}
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typedef struct __attribute__ ((aligned(16))) args_t {
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int *a;
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int *b;
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int *c;
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int d;
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int n;
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} args;
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static const char kSubTestSeparator[] = " **************************";
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static const int kMemoryAllocSize = 4096;
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void MemoryAtomic::MemoryAtomicTest(hsa_agent_t cpuAgent,
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hsa_agent_t gpuAgent) {
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hsa_status_t err;
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// Get Global Memory Pool on the gpuAgent to allocate gpu buffers
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hsa_amd_memory_pool_t gpu_pool;
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err = hsa_amd_agent_iterate_memory_pools(gpuAgent,
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rocrtst::GetGlobalMemoryPool,
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&gpu_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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hsa_amd_memory_pool_access_t access;
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hsa_amd_agent_memory_pool_get_info(cpuAgent, gpu_pool,
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HSA_AMD_AGENT_MEMORY_POOL_INFO_ACCESS,
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&access);
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// hsa objects
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hsa_queue_t *queue = NULL; // command queue
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// get queue size
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uint32_t queue_size = 0;
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err = hsa_agent_get_info(gpuAgent,
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HSA_AGENT_INFO_QUEUE_MAX_SIZE, &queue_size);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// create queue
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err = hsa_queue_create(gpuAgent,
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queue_size, HSA_QUEUE_TYPE_MULTI,
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NULL, NULL, 0, 0, &queue);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Find a memory pool that supports kernel arguments.
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hsa_amd_memory_pool_t kernarg_pool;
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err = hsa_amd_agent_iterate_memory_pools(cpuAgent,
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rocrtst::GetKernArgMemoryPool,
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&kernarg_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allocate the host side buffers
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// (refSysdata,oldValues,oldrefdata,kernArg) on system memory
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// this is ref sys data on which atomics operation need to done
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int *refSysdata = NULL;
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// This is oldrefdata which will be required to compare the returned old values after atomics operation
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int *oldrefdata = NULL;
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// This is returned old values
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int *oldValues = NULL;
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// This is expected data set
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int *expecteddata = NULL;
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// Array size for the data
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int arraySize = kMemoryAllocSize/sizeof(int);
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// Get System Memory Pool on the cpuAgent to allocate host side buffers
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hsa_amd_memory_pool_t global_pool;
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err = hsa_amd_agent_iterate_memory_pools(cpuAgent,
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rocrtst::GetGlobalMemoryPool,
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&global_pool);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&oldValues));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&refSysdata));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&oldrefdata));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_memory_pool_allocate(global_pool,
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kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&expecteddata));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allocate the kernel argument buffer from the kernarg_pool.
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args *kernArguments = NULL;
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err = hsa_amd_memory_pool_allocate(kernarg_pool, sizeof(args_t), 0,
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reinterpret_cast<void **>(&kernArguments));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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memset(oldValues, 0, kMemoryAllocSize);
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memset(expecteddata, 0, kMemoryAllocSize);
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// this signal will be used for copying the data memory from To and fro from GPU
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// on Non-largebar system
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hsa_signal_t copy_signal;
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// for the dGPU, we have coarse grained local memory,
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// so allocate memory for it on the GPU's GLOBAL segment .
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// Get local memory of GPU to allocate device side buffers on which atomics operation need to done
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int *gpuRefData = NULL;
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// On non-Large bar system acess to GPU pool not allowed to directly so pinned memory
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// g_gpuRefData is pointer to GPU Memory allocated on non-large bar where
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// gpuRefData would be pointer to host allocated memory on non-large bar
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int *g_gpuRefData = NULL;
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// Pointer to the location where to store the new address
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int *device_ptr = NULL;
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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err = hsa_amd_memory_pool_allocate(gpu_pool, kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&gpuRefData));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Allow cpuAgent access to all allocated GPU memory.
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err = hsa_amd_agents_allow_access(1, &cpuAgent, NULL, gpuRefData);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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memset(gpuRefData, 0, kMemoryAllocSize);
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} else {
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err = hsa_signal_create(1, 0, NULL, ©_signal);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Alocate the System Memory and get pointer gpuRefData
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err = hsa_amd_memory_pool_allocate(global_pool, kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&gpuRefData));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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memset(gpuRefData, 0, kMemoryAllocSize);
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// Alocate the GPU Memory and get pointer g_gpuRefData
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err = hsa_amd_memory_pool_allocate(gpu_pool, kMemoryAllocSize, 0,
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reinterpret_cast<void **>(&g_gpuRefData));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Pinned the Host memory and get the pointer to new adress which is accesible to GPU agent
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err = hsa_amd_memory_lock(gpuRefData, kMemoryAllocSize, &gpuAgent, 1, reinterpret_cast<void **>(&device_ptr));
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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}
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// initialize the host buffers & gpuRefData buffer
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for (int i = 0; i < arraySize; ++i) {
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unsigned int seed = time(NULL);
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refSysdata[i] = 6 + rand_r(&seed) % 1;
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gpuRefData[i] = 6 + rand_r(&seed) % 1;
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oldrefdata[i] = refSysdata[i];
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}
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// Sync the data from system memory to GPU memory on non-largebar
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if (access == HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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hsa_signal_store_relaxed(copy_signal, 1);
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err = hsa_amd_memory_async_copy(g_gpuRefData, gpuAgent, device_ptr,
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gpuAgent, kMemoryAllocSize, 0, NULL, copy_signal);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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while (hsa_signal_wait_acquire(copy_signal, HSA_SIGNAL_CONDITION_LT, 1, (uint64_t)(-1), HSA_WAIT_STATE_ACTIVE)) {}
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}
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// Allow gpuAgent access to all allocated system memory.
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, oldValues);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, refSysdata);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, oldrefdata);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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err = hsa_amd_agents_allow_access(1, &gpuAgent, NULL, kernArguments);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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kernArguments->a = refSysdata;
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if (access != HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
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kernArguments->b = gpuRefData;
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} else {
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kernArguments->b = g_gpuRefData;
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}
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kernArguments->c = oldValues;
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if (testtype_ != INC && testtype_ != DEC) {
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kernArguments->d = kValue;
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}
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// Create the executable, get symbol by name and load the code object
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set_kernel_file_name("atomicOperations_kernels.hsaco");
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if (testtype_ == ADD) {
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set_kernel_name("test_atomic_add");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] + kValue;
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}
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} else if (testtype_ == SUB) {
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set_kernel_name("test_atomic_sub");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] - kValue;
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}
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} else if (testtype_ == AND) {
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set_kernel_name("test_atomic_and");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] & kValue;
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}
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} else if (testtype_ == OR) {
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set_kernel_name("test_atomic_or");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] | kValue;
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}
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} else if (testtype_ == XOR) {
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set_kernel_name("test_atomic_xor");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] ^ kValue;
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}
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} else if (testtype_ == MIN) {
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set_kernel_name("test_atomic_min");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = std::min(oldrefdata[i], kValue);
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}
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} else if (testtype_ == MAX) {
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set_kernel_name("test_atomic_max");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = std::max(oldrefdata[i], kValue);
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}
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} else if (testtype_ == INC) {
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set_kernel_name("test_atomic_inc");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] + 4;
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}
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} else if (testtype_ == DEC) {
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set_kernel_name("test_atomic_dec");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = oldrefdata[i] - 4;
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}
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} else if (testtype_ == XCHG) {
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set_kernel_name("test_atomic_xchg");
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// set the expected data result set from kernel
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for (int i = 0; i < arraySize; ++i) {
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expecteddata[i] = kValue;
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}
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} else {
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if (verbosity() > 0) {
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std::cout<< "No test specified" <<std::endl;
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}
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}
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err = rocrtst::LoadKernelFromObjFile(this, &gpuAgent);
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ASSERT_EQ(err, HSA_STATUS_SUCCESS);
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// Fill up the kernel packet except header
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err = rocrtst::InitializeAQLPacket(this, &aql());
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ASSERT_EQ(HSA_STATUS_SUCCESS, err);
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aql().workgroup_size_x = 256;
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aql().workgroup_size_y = 1;
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aql().workgroup_size_z = 1;
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aql().grid_size_x = arraySize;
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aql().kernarg_address = kernArguments;
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aql().kernel_object = kernel_object();
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const uint32_t queue_mask = queue->size - 1;
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// Load index for writing header later to command queue at same index
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uint64_t index = hsa_queue_load_write_index_relaxed(queue);
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hsa_queue_store_write_index_relaxed(queue, index + 1);
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rocrtst::WriteAQLToQueueLoc(queue, index, &aql());
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aql().header = HSA_PACKET_TYPE_KERNEL_DISPATCH;
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aql().header |= HSA_FENCE_SCOPE_SYSTEM <<
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HSA_PACKET_HEADER_ACQUIRE_FENCE_SCOPE;
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aql().header |= HSA_FENCE_SCOPE_SYSTEM <<
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HSA_PACKET_HEADER_RELEASE_FENCE_SCOPE;
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void* q_base = queue->base_address;
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// Set the Aql packet header
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rocrtst::AtomicSetPacketHeader(aql().header, aql().setup,
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&(reinterpret_cast<hsa_kernel_dispatch_packet_t*>
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(q_base))[index & queue_mask]);
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// ringdoor bell
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hsa_signal_store_relaxed(queue->doorbell_signal, index);
|
|
|
|
// wait for the signal and reset it for future use
|
|
while (hsa_signal_wait_scacquire(aql().completion_signal, HSA_SIGNAL_CONDITION_LT, 1,
|
|
(uint64_t)-1, HSA_WAIT_STATE_ACTIVE)) { }
|
|
|
|
hsa_signal_store_relaxed(aql().completion_signal, 1);
|
|
|
|
// Sync the data from GPU memory to system memory on non-largebar
|
|
if (access == HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
|
|
hsa_signal_store_relaxed(copy_signal, 1);
|
|
err = hsa_amd_memory_async_copy(device_ptr, gpuAgent, g_gpuRefData,
|
|
gpuAgent, kMemoryAllocSize, 0, NULL, copy_signal);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
while (hsa_signal_wait_acquire(copy_signal, HSA_SIGNAL_CONDITION_LT, 1, (uint64_t)(-1), HSA_WAIT_STATE_ACTIVE)) { }
|
|
}
|
|
|
|
// compare results with expected results
|
|
for (int i = 0; i < arraySize; ++i) {
|
|
ASSERT_EQ(refSysdata[i], expecteddata[i]);
|
|
ASSERT_EQ(gpuRefData[i], expecteddata[i]);
|
|
ASSERT_EQ(oldValues[i], oldrefdata[i]);
|
|
}
|
|
|
|
if (refSysdata) {
|
|
err = hsa_memory_free(refSysdata);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
if (oldrefdata) {
|
|
err = hsa_memory_free(oldrefdata);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
if (oldValues) {
|
|
err = hsa_memory_free(oldValues);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
if (access == HSA_AMD_MEMORY_POOL_ACCESS_NEVER_ALLOWED) {
|
|
err = hsa_amd_memory_unlock(gpuRefData);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
// Destroy the copy signal
|
|
err = hsa_signal_destroy(copy_signal);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
if (g_gpuRefData) {
|
|
err = hsa_memory_free(g_gpuRefData);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
}
|
|
if (gpuRefData) {
|
|
err = hsa_memory_free(gpuRefData);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
if (kernArguments) {
|
|
err = hsa_memory_free(kernArguments);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
if (queue) {
|
|
err = hsa_queue_destroy(queue);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
}
|
|
}
|
|
|
|
void MemoryAtomic::MemoryAtomicTest(void) {
|
|
hsa_status_t err;
|
|
// find all cpu agents
|
|
std::vector<hsa_agent_t> cpus;
|
|
err = hsa_iterate_agents(rocrtst::IterateCPUAgents, &cpus);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
|
|
// find all gpu agents
|
|
std::vector<hsa_agent_t> gpus;
|
|
err = hsa_iterate_agents(rocrtst::IterateGPUAgents, &gpus);
|
|
ASSERT_EQ(err, HSA_STATUS_SUCCESS);
|
|
|
|
for (unsigned int i = 0 ; i< gpus.size(); ++i) {
|
|
MemoryAtomicTest(cpus[0], gpus[i]);
|
|
}
|
|
}
|
|
|