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rocm-systems/tests/workloads/kernels/mi200/prev_analysis/602.csv
T
JoseSantosAMD 717a21cf84 Update csv headers, and SystemExit codes
Signed-off-by: JoseSantosAMD <Jose.Santos@amd.com>
2024-02-04 12:44:47 -06:00

638 B

1MetricAvgMinMaxUnit
2Wave request Failed (CS)381751.3712574855182390380Cycles
3CS Stall287028.544910179608079241Cycles
4CS Stall Rate47.046018235262930.0153.9875955913479Pct
5Scratch Stall0.000Cycles
6Insufficient SIMD Waveslots12620403.9940119760383533081Simd
7Insufficient SIMD VGPRs0.000Simd
8Insufficient SIMD SGPRs0.000Simd
9Insufficient CU LDS_Per_Workgroup0.000Cu
10Insufficient CU Barries0.000Cu
11Insufficient Bulky Resource0.000Cu
12Reach CU Threadgroups Limit0.000Cycles
13Reach CU Wave Limit0.000Cycles
14VGPR Writes4.04.04.0Cycles/wave
15SGPR Writes2.00598802395209572.03.0Cycles/wave